Power- Switching Converters Second Edition Simon Ang University of Arkansas Fayetteville, Arkansas, U.S.A. Alejandro Oliva Universidad Nacional del Sur Bahia Blanco, Argentina Taylor &. Francis Taylor & Francis Croup Boca Raton London New York Singapore A CRC title, part of the Taylor & Francis imprint, a member of the Taylor & Francis Croup, the academic division of T&F Informa pic. Published in 2005 by CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2005 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group No claim to original U.S. Government works Printed in the United States of America on acid-free paper 10 987654321 International Standard Book Number-10: 0-8247-2245-0 (Hardcover) International Standard Book Number-13: 978-0-8247-2245-6 (Hardcover) Library of Congress Card Number 2004059348 This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use. No part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copyright.com (http://www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC) 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and registration for a variety of users. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Library of Congress Cataloging-in-Publication Data Ang, Simon S., 1957- Power-switching converters / Simon Ang, Alejandro Oliva - 2nd ed. p. cm. — (Electrical and computer engineering) Includes bibliographical references and index. ISBN 0-8247-2245-0 (alk. paper) 1. Power electronics. 2. Electric current converters. 3. Switching circuits. I. Oliva, Alejandro. II. Title. III. Series. TK7881.15.A54 2004 621.31'7-dc22 .' 2004059348 T&F informa Visit the Taylor & Francis Web site at http://wvm.tayloranaTrancis.com Taylor & Francis Group and the CRC Press Web site at is the Academic Division of T&F Informa pic. http://www.crcpress.coni Preface to the Second Edition In this second edition, Dr. Simon Ang welcomes co-author, Dr. Alejandro Oliva of the Universidad National del Sur, Argentina. Much new material and many references have been added. Several chapters have been com- pletely revised, and two new chapters on interleaved converters and switched capacitor converters have been added. The discrete-time modeling method has been included in the dynamic analysis of switching converters. Design case studies have been replaced with new cases. This book is intended to be used as a textbook for a senior-level electrical engineering course on switching converters. The introductory course would cover the basic switching converter topologies described m Chapters 1 to 4, followed by an introduction to basic control techniques presented in Chapter 5. The instructor may choose to skip to Chapters 7 and 8 on interleaved converters and switching capacitor converters, respectively. Chapter 6 covers the closed-loop control and stability considerations in the design of switching converters. It discusses the dynamic analysis of switching converters based on state-space averaging and linearization. This chapter is divided into two parts. The first part covers continuous-time x Preface models and control techniques, while the second part introduces discrete- time models based on sampled-data modeling. Many of the topics presented in this chapter can be skipped and covered later in a more advanced level course. Chapter 9 provides tools for the simulation of switching converters. It introduces both PSpice and MATLAB simulations of switching converters. This chapter may be partially taught after Chapter 2 and concurrently with Chapters 4 to 6. The discussion of switching converters is not complete until a switching converter is analyzed, designed, and finally prototyped. Chapter 10 contains complete design examples, including experimental designs, which may be used as technical reference or for a class project. Supplementary information and material, updated periodically, are available on the download page at http://www.crcpress.com. These include class slides, selected PSpice examples, and MATLAB scripts. The PSpice examples are designed to run on the OrCAD 10.0 demo software. Several individuals have contributed to this second edition of Power- Switching Converters by providing assistance, suggestions, and criticisms. We appreciate the collaboration of Dr. Juan Carlos Balda for his detailed and constructive criticism, which improve the accuracy and content of Chapter 6. We would like to thank Dr. Roberto M. Schupbach for his thorough reading and error detection in the MATLAB code. Graciela Rodriguez (Mrs. Oliva) gave up her vacations to offer invaluable help with the figures and equations. Several design case studies in Chapter 10 were adapted from the class projects of our former graduate students at the University of Arkansas, in particular, those of Kien Truong and Lan Phuong Bui Pham. We gratefully acknowledge Claudio Frate for preparing most of the figures in the text. Finally, we like to sincerely express our gratitude to our families for their support and love. Simon S. Ang Alejandro R. Oliva Editors Simon S. Ang has been a professor of electrical engineering at the University of Arkansas at Fayetteville since 1988. He received his B.S.E.E. from the University of Arkansas at Fayetteville in 1980, his M.S.E.E. from Georgia Tech, Atlanta in 1981, and his Ph.D. in electrical engineering from Southern Methodist University, Dallas, Texas in 1985. He was with Texas Instru- ments, Dallas from 1981 to 1988. Dr. Ang has published in more than 200 journals and proceedings papers and holds four U.S. patents. His research interests are switching converters, bio-sensors, and MEMS. Alejandro R. Ouva has been an assistant professor at the Universidad Nacional del Sur, Bahia Blanca, Argentina, since 1999. He received his B.S.E.E. from the Universidad Nacional del Sur in 1987, his M.S.E.E. in 1996, and his Ph.D. in electrical engineering from the University of Arkansas at Fayetteville in 2004. From 1987 to 1988 Dr. Oliva worked for Hidronor S.A., developing a database for modeling large hydraulic plants. He has been associated with the Universidad Nacional del Sur since 1988, and from 1994 to 1996, he worked for the University of Arkansas at Fayetteville on an EPRI/CSW power quality research project. He has published in more than 30 journals and proceedings. His main research interests are power electron- ics and DSP control. Contents Preface to the Second Edition IX 1 1. Introduction to Switching Converters * 1.1 Introduction ^ 1 .2 Industry Trends 2 1 .3 Linear Converter 1.3.1 Linear Series-Pass Regulator 3 1.3.2 Linear Shunt Regulator 5 1 .4 Switching Converters 1 .4. 1 Basic Switching Converter with Resistive Load 8 1 .4.2 Basic Switching Converter with R^ Load 1 1 1 . 5 Principles of Steady-State Converter Analysis 1 3 1 .5. 1 Inductor Volt-Second Balance * 3 1.5.2 Capacitor Charge Balance 14 Problems l5 References 2. Basic Switching Converter Topologies 17 2.1 Introduction *' 2.2 Buck Converter J° 2.2.1 Continuous Mode 19 xiv Contents 2.2.2 Discontinuous Mode 24 2.3 Synchronous Rectifier 31 2.4 Boost Converter 32 2.4.1 Continuous Mode 33 2.4.2 Discontinuous Mode 38 2.5 Buck-Boost Converter 42 2.5.1 Continuous Mode 45 2.5.2 Discontinuous Mode 49 2.6 Cfik Converter 52 Mode 1 (0 < t < t on ) 53 Mode 2 (t on <t<T) 55 2.7 Converter Realization with Nonideal Components 61 2.7.1 Inductor Model 61 2.7.2 Semiconductor Losses 62 2.7.3 Capacitor Model 63 Problems 64 References 66 3. Resonant Converters 69 3.1 Introduction 69 3.2 Parallel Resonant Circuit — A Review 71 3.3 Series Resonant Circuit — A Review 72 3.4 Classification of Quasi-Resonant Switches 73 3.5 Zero-Current-Switching Quasi-Resonant Buck Converter 77 Mode 1 (0 < / < fj) 78 Mode 2 (r, < t < t 2 ) 79 Mode 3 (t 2 < t < ti) 83 Mode 4 (r 3 < / < T s ) 83 3.6 Zero-Current-Switching Quasi-Resonant Boost Converter 87 Mode 1 (0 < / < *,) 88 Mode 2 (f i < t < r 2 ) 89 Mode 3 (t 2 < t < f 3 ) 91 Mode 4 (r 3 < * < T s ) 92 3.7 Zero-Voltage-Switching Quasi-Resonant Buck Converter 94 Mode 1 (0 < / < /,.) 95 Mode 2 (/, < t < r 2 ) 96 Mode 3 (r 2 < / < t 3 ) 98 Mode 4 (f 3 < t < T s ) 98 3.8 Zero-Voltage-Switching Quasi-Resonant Boost Converter 101 Mode 1 (0 < r < *i) 101 Mode 2 (r, < t < t 2 ) 102 Contents xv 3.9 Mode 3 (/ 2 < t < r 3 ) Mode 4 (/ 3 < t < T s ) Series-Loaded Resonant Converter 3.10 4. Discontinuous Mode (0 </< 0.5f„) Continuous Mode {f s > f„ or Above-Resonant Mode) Continuous Mode (0.5/„ </</„ or Below-Resonant Mode) Parallel-Loaded Resonant Converter 3.10.1 Discontinuous Mode (0 <f< 0.5f„) Continuous Mode (f s >fi or Above-Resonant Mode) Continuous Mode (0.5/„ <f s <f n or Below-Resonant Mode) 3.9.1 3.9.2 3.9.3 3.10.2 3.10.3 Problems References Transformerized Switching Converters 4.1 Introduction 4.2 Forward Converter Mode 1 (0 < t < r,) Mode 2 (t on <t<T s ) 4.3 Push-Pull Converter 4.4 Half-Bridge Switching Converter 4.5 Full-Bridge Switching Converter 4.6 Flyback Converter 4.7 Zero-Current-Switching Quasi-Resonant Half-Bridge Converter Mode 1 (0 < r < f,) Mode 2 (<i <t<t 2 ) Mode 3 (t 2 < t < r 3 ) Mode 4 (f 3 < t < TJT) Problems References 5. Control Schemes of Switching Converters 5.1 Introduction 5.2 Pulse-Width Modulation 5.2.1 Voltage-Mode PWM Scheme 5.2.2 Current-Mode PWM Scheme 5.2.2.1 Instability for D > 50% 5.2.2.2 Compensation with External Ramp 104 105 107 108 110 113 116 117 121 123 126 128 129 129 130 131 132 136 140 143 145 151 152 153 154 155 158 159 161 161 162 162 169 171 172 - v l Contents 5.3 Hysteresis Control: Switching Current Source 172 5.3.1 Steady-State Analysis During t on 175 5.4 Commercial Integrated Circuit Controllers 177 5.4.1 Fixed-Frequency Voltage-Mode SG3524 Controller l" 77 5.4.2 Variable-Frequency Vohage-Mode TL497 Controller 180 5.4.3 Fixed-Frequency Current-Mode UC3842 PWM Controller 181 5.4.4 TinySwitch-II Family of Low Power Off-Line Switchers 185 5.5 Control Schemes for Resonant Converters 187 5.5.1 Off-Line Controllers for Resonant Converters 190 5.5.1.1 L6598 Operation 190 Problems 195 References 196 6. Dynamic Analysis of Switching Converters 199 6.1 Introduction 199 6.2 Continuous-Time Linear Models 201 6.2.1 Switching Converter Analysis Using Classical Control Techniques 201 6.2. 1 . 1 Basic Linear Model of the Open-Loop Switching Converter 201 6.2.1.2 PWM Modulator Model 202 6.2.1.3 Averaged Switching Converter Models 207 6.2.1.4 Switch=Losses 210 6.2.1.5 SwitcFFDelay 210 6.2.1.6 Output Filter Model 211 6.2.2 Summary of Small-Signal Models of Switching Converters 221 6.2.3 Review of Negative Feedback Using Classical-Control Techniques 221 6.2.3.1 Closed-Loop Gain 221 6.2.3.2 Stability Analysis 225 6.2.3.3 Linear Model of the Closed-Loop Switching Converter 227 6.2.4 Feedback Compensation in a Buck Converter with Output Capacitor ESR 236 6.2.5 Feedback Compensation in a Buck Converter with no Output Capacitor ESR 240 Contents xvu 6.3 6.2.6 Linear Model of the Voltage Regulator Including External Perturbances 6.2.7 Output Impedance and Stability 6.2.8 State-Space Representation of Switching Converters 6.2.8.1 Review of Linear System Analysis 6.2.9 State-Space Averaging 6.2.9.1 State-Space Averaged Model for an Ideal Buck Converter 6.2.9.2 State-Space Averaged Model for the Discontinuous-Mode Buck Converter 6.2.9.3 State-Space Averaged Model for a Buck Converter with a Capacitor ESR 6.2.9.4 State-Space Averaged Model for an Ideal Boost Converter 6.2.10 Switching Converter Transfer Functions 6.2. 1 0. 1 Source-to-State Transfer Functions 6.2. 1 0.2 Open-Loop Transfer Functions 6.2. 1 0.3 Loop Compensations in Buck Converter 6.2.11 Complete State Feedback 6.2. 1 1 . 1 Design of a Control System with Complete State Feedback 6.2.11.2 Pole Selection 6.2. 1 1 .3 Feedback Gains 6.2.12 Input EMI Filters 6.2.12.1 Stability Considerations Discrete-Time Models Introduction Continuous-Time and Discrete-Time Domains Continuous-Time State-Space Model Discrete-Time Model of the Switching Converter Design of a Discrete Control System with Complete State Feedback 6.3.5.1 Pole Selection 6.3.5.2 Feedback Gains Voltage Mode Control 6.3.6.1 Extended-State Model for a Tracking Regulator Current Mode Control 6.3.7.1 Extended-State Model for a Tracking Regulator 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 Problems References 242 243 245 245 247 248 255 263 268 276 276 281 283 286 286 288 288 292 293 302 302 302 303 306 308 309 309 309 311 312 314 315 318 cviii Contents 7. Interleaved Converters 321 7.1 Introduction 321 7.2 Interleaved Buck Converter 322 7.2.1 State-Space Averaged Model 324 7.3 Interleaved Boost Converter 326 7.3.1 State-Space Averaged Model 326 7.4 Interleaved Converter Operation Based on Current-Mode 331 7.4.1 Ripple Calculations 332 7.4.2 Number of Converters 334 7.5 Power Factor Correction 334 Problems 338 References 338 8. Switched Capacitor Converters 341 8.1 Introduction 341 8.2 Unidirectional Power Flow SCC 342 8.2.1 Basic Step-Up Converter 342 8.2.2 Basic Step-Down Converter 344 8.2.3 Basic Inverting Converter 345 8.3 Alternative Switched Capacitor Converter Topologies 347 8.3.1 Step-Down Converter 348 8.4 State— Space Averaging Model 350 8.4.1 Step-Up Converter 352 8.4.2 n-Stage Step-Down SCC 353 8.4.3 n-Stage Step-Up SCC 355 8.5 Bi-Directional Power Flow SCC 356 8.5.1 Step-Up Step-Down Converter 356 8.5.1.1 Step-Down Operation 357 8.5.1.2 Step-Up Operation 358 8.5.2 Luo Converter 359 8.6 Resonant Converters 365 8.6.1 Zero-Current Switching 365 8.6.1.1 Condition of Zero-Current Switching 368 8.7 Losses on Switched-Capacitor Power Converters 369 Problems 370 References .371 Contents XIX 9. Simulation of Switching Converters 373 9.1 Introduction 373 9.2 PSpice Circuit Representation 374 9.3 PSpice Simulations Using .CIR 375 9.3.1 An Ideal Open-Loop Buck Converter 3 75 9.3.2 Buck Converter with an Ideal Switch 381 9.4 PSpice Simulations Using Schematics Entry 386 9.4.1 Boost Converter 387 9.4.2 PSpice Simulations Using Behavioral Modeling 388 9.4.2.1 Control System Parts 389 9.4.2.2 PSpice-Equivalent Parts 389 9.4.3 Examples of ABM Blocks Use 392 9.4.4 PSpice Simulations Using Control Blocks 397 9.4.4.1 Voltage-Mode PWM Boost Converter 399 9.4.5 PSpice Simulations Using Vendor Models 402 9.5 Small-Signal Analysis of Switching Converters 403 9.5.1 Open-Loop Transfer Function 407 9.5.2 Input Impedance 4 °9 9.5.3 Output Impedance 409 9.5.4 Small-Signal Transient Analysis 409 9.5.5 Measuring the Loop Gain 411 9.5.6 Frequency Compensation 412 9.5.6.1 PID Compensation 413 9.5.6.2 PI Compensation 418 9.6 Creating Capture Symbols for PSpice Simulation 4 22 9.7 Solving Convergence Problems 422 9.7.1 DC Analysis Error Messages 423 9.7.2 Transient Analysis Error Messages 423 9.7.3 Solutions to Convergence Problems 424 9.7.4 Bias Point (DC) Convergence 424 9.7.5 Checking Circuit Topology and Connectivity 424 9.7.5.1 Setting up the Options for the Analog Simulation 42 -> 9.7.6 Transient Convergence 426 9.7.6.1 Circuit Topology and Connectivity 42 6 9.7.6.2 PSpice Options 427 9.8 Switching Converter Simulation Using MATLAB 428 9.8.1 Working with Transfer Functions 428 9.8.2 Working with Matrices 431 9.9 Switching Converter Simulation Using Simulink 433 9.9.1 Transfer Function Example Using Simulink 434 9.9.2 State-Space Example Using Simulink 436 xx Contents Problems 436 References 437 10. Switching Converter Design: Case Studies 439 10.1 Introduction 439 10.2 Voltage-Mode Discontinuous-Conduction-Mode Buck Converter Design 441 10.2.1 Controller Design 442 10.2.2 Small-Signal Model 443 10.2.3 Design of the Compensation Network and Error Amplifier 446 10.2.3.1 MATLAB Program to Calculate the Compensation Network 448 10.2.4 The Closed-Loop Buck Converter 452 10.2.5 Simulation Results 452 10.2.6 Experimental Results 452 10.2.6.1 Open-Loop Experimental Data 454 10.2.6.2 Open-Loop Load Regulation 454 10.2.6.3 Bode Plot of the Loop Gain 455 10.2.6.4 Closed-Loop Experimental Results 456 10.2.6.5 Closed-Loop Line and the Load Regulations 457 10.3 Digital Control of a Voltage-Mode Synchronous Buck Converter 460 10.3.1 Circuit Parameters 461 10.3.2 Closed-Loop Pole Selection 462 10.3.3 Discrete-Time Model 463 10.3.4 Feedback Gains 465 10.3.5 Control Strategy 466 10.3.6 Analog Model for PSpice Simulations 467 10.3.7 Simulation Results 470 10.3.8 Sensitivity of the Closed-Loop Poles Due to Load Variations 470 10.3.9 Experimental Results 472 10.4 Digital Control of a Current-Mode Synchronous Buck Converter . 473 10.4.1 Continuous-Time State Model 474 10.4.2 Obtaining the Discrete-Time Model 475 10.4.3 Current-Mode Instability 476 10.4.4 Extended-State Model for a Tracking Regulator 476 Contents xxi 10.4.5 Feedback Gains 477 10.4.5.1 MATLAB Design File 477 10.4.6 Control Strategy 479 10.4.7 Simulation Results 479 10.4.8 Sensitivity of the Closed-Loop Poles Due to Load Variations 48 * 10.4.9 Experimental Results 481 10.4.10 DSP Program 482 10.5 UC3842-Based Flyback Design 489 10.5.1 Design Specifications 490 10.5.2 Discontinuous Conduction Mode 4 90 10.5.3 Preliminary Calculations 492 10.5.4 Open-Loop Simulations 493 10.5.5 Current Loop 494 10.5.6 Voltage Loop 494 10.5.6.1 Current-Sensing Resistor and Filtering 495 10.5.6.2 Dissipative Snubber 496 10.5.6.3 The Error Amplifier 496 10.5.6.4 The Bias Circuit 497 10.5.7 Small Signal Model 498 10.5.8 Frequency Compensation 4 " 10.5.8.1 Closed-Loop Simulations 500 10.5.9 EMI Filter Design 502 10.5.10 Printed Circuit Board Design 504 10.5.11 Experimental Results 506 10.6 TopSwitch-Based Flyback Design 508 10.6.1 Design Specifications 509 10.6.2 Preliminary Calculations 509 10.6.3 Experimental Results 51 ° 10.6.3.1 Line Regulation 513 10.6.3.2 Load Regulation 513 10.7 TinySwitch-Based Flyback Design 513 10.7.1 Experimental Results 514 10.7.1.1 Waveforms 514 10.7.1.2 Line Regulation 516 10.7.1.3 Load Regulation 516 10.8 Switching Audio Amplifier 5 *° 10.8.1 Case Study 521 10.8.1.1 The Output Stage 522 XXII 10.8.1.2 The Error Amplifier 523 10.8.1.3 PWM Modulator 523 10.8.1.4 The Feedback Loop 526 10.8.1.5 Evaluation 526 532 References Index 533 Introduction to Switching Converters 1.1 INTRODUCTION A switching converter-^or switch-mode power converter is a power elec- tronic system, which converts one level of electrical energy into another level of electrical energy at the load, by switching action. Switching con- verters have been in existence since the 1950s. However, the unavailability of reliable and low-cost power switching transistors had limited their usage primarily to the military and space applications. The advances and avail- ability of modern power semiconductor devices in the early 1970s have made the switching converter a popular choice in power supplies. In DC- DC switching converter circuits, semiconductor switches control the dy- namic transfer of power, from the input direct current (DC) source to the load, by connecting the source to the load for some predetermined duration. These switching converters find applications in high-efficiency power supplies and DC motor drives. In comparison to linear voltage converters, or linear voltage regulators, switching power supplies have higher energy efficiency and a higher power packing density. New and 2 Power-Switching Converters improved power semiconductor devices such as power MOSFETs and insulated-gate bipolar transistors (IGBTs), integrated magnetics, newer topologies, and VLSI pulse-width-modulating integrated circuits, which pack more control and supervisory features in a smaller volume, have contributed to the increased power packing density of switching converters. 1.2 INDUSTRY TRENDS Over the past few years, the DC-DC switching converter technology has undergone tremendous changes. The required supply voltage for many inte- grated circuits and their associated electronic systems decreases from the historic 5 V standard to less than 1.5 V. At the same time, the load current levels have simultaneously risen to levels that would have been unimaginable just a few years ago. Some electronic systems are now requiring 2.5 V at 60 A, 1 .8 V at 60 A or 1 V at 1 00 A from the power supply. In the near future, supply voltages for some microprocessors will move towards 0.5 V and currents up to 400 A are expected. A normal dynamic requirement for a DC-DC switching converter is to provide a peak output voltage in response to a load transient of 75-100-75 A at a slew rate of 100 A/fi-sec with only 60mV of deviation. At the same time, the converter should recover to within ± 1 .5% of output voltage in less than 4 jtsec. These requirements are making it very difficult to deliver high current, low voltage power from a centralized power supply. Designers are now increasingly turning to distributed power supply architectures to provide lower voltages at high currents from a DC-DC converter to power today's complex loads. A distributed power system generates a high-voltage DC bus (e.g., 48 V) and distributes this voltage at a lower current around the electronics system to the various loads. Near each load, one or more modular DC-DC switching converters convert the bus voltage to a low-voltage source (e.g., 1 V) needed by the load circuitry. Besides reducing the voltage, the modular DC-DC switching converter also provides electrical isolation and increased load transient performance. Distributed power systems eliminate the mech- anical and cost problems of the thick copper buses required in a centralized power supply system. The lower voltage draws a larger current and has less tolerance for deviations in its voltage [1]. In 1999, the measure for high density was 25 W/in. 3 at 5 V. By 2001 , this had increased to 40 W/in. 3 at 3.3 V. Nowadays, power densities of greater than 50 W/in. 3 are achievable, while high-power density is considered to be around 90 W/in. 3 The continuing evolution in magnetic components and its integration with passives has played a key role in increasing the power Introduction to Switching Converters J density without sacrificing performance [2]. A dramatic increase in converter efficiency and power density was accomplished by synchronous rectification, especially for low-voltage converters. The combination of synchronous rec- tifiers and interleaving techniques led to commercial converters that can achieve efficiencies higher than 92%, while efficiencies of 85% are routinely obtainable [1]. Interleaving (or multiphase) converters ofTer several advantages over a single power stage, including lower current ripple on the input and output capacitors, faster transient response to load changes, and improved power handling capabilities at greater than 90% power efficiency. Commercial controllers can operate each phase at a switching frequency in the MHz range, resulting in effective size reduction [3]. The new generation of switching converter controllers is based on DSP technology to implement the digital control, monitoring, and communication functions into a single DSP chip, simplifying designs and resulting in a considerable part count reduction. This simplified design allows for the control of multiple power supply products with a single control architecture, which is customized for each power supply through software. The computational power of the DSP can be used to achieve higher efficiencies, by implementing soft- switching techniques, such as zero-voltage switching (ZVS) and zero-cur- rent switching (ZCS). In addition, more efficient topologies that take advantage of advanced nonlinear digital control techniques may be used to obtain optimum performance over the complete operating range of the power supply [4]. 1.3 LINEAR CONVERTER There are two types of linear converters or voltage regulators: series and shunt. They differ only in the way that their output voltage is regu- lated. 1.3.1 Linear Series-Pass Regulator The series-pass regulator shown in Figure 1.1 is essentially an electrically variable resistance in the form of a transistor operating in its linear mode in series with the output load. An error amplifier senses the DC output voltage across a sampling resistor network R t and R 2 and compares it with a reference voltage F ref . The error amplifier output voltage drives the base of the series-pass NPN transistor via a current amplifier. The output voltage is regulated by modu- lating the base-drive of the series-pass NPN transistor. An increase in the sampling voltage across R 2 decreases the base drive of. the series-pass Power-Switching Converters Series-pass NPN transistor X^T Base Driver Error Amplifier Reference Voltage 1 Figure 1 .1 Series-pass voltage regulator. transistor such that a smaller current is delivered to the output and hence, the output voltage drops. The regulated output voltage, V oul , is F out =F ref (l+^). (1.1) This is the relationship of a noninverting operational amplifier circuit, assuming that the series-pass transistor is ideal. A change in the input voltage results in a change in the equivalent resistance J? s of the series-pass transistor. The product of this resistance and the load current, 7j oa d» creates a changing differential voltage, V ditt , which compensates for a changing input voltage A V in . The output voltage can be expressed as K „t = F ir V 6 iff, and Pdiff = /load-Rs, (1.2) (1.3) or 'out — *in /foad-Ks- Thus, for a changing input voltage AV in AJ? S = ^load (1.4) (1.5) Introduction to Switching Converters 5 assuming that V out and V in are fixed, and for a changing load current AR s = - R f Iload . (1-6) /load Any change inJhe input voltage will essentially be absorbed across the series- pass transistor. The stability of the output voltage is mainly determined by the gain of the open-loop feedback amplifier. A series-pass regulator provides a simple and inexpensive way to obtain a source of regulated voltage. However, it can only provide a lower regulated voltage than its input source voltage. Even though its output voltage always has one DC common with the input voltage, frequently DC isolation between input and output is required. The major drawback of the series-pass regulator is the excessive power dissipation in the series-pass transistor in high-current applications. The power dissipated across the collector-emitter junction of the series-pass transistor is ^diss = (V in - K out )/ Ioad . (I- 7 ) It is evident that as the input voltage increases for a constant regulated output voltage, the power dissipated in the series-pass transistor increases. The effi- ciency of this regulator, disregarding any fluctuations of the input and output voltages, is -font Fpul -Head _ *out (18) ••in ' in-'load 'in This is plotted in Figure 1.2 for a 5-V regulator and assuming a "drop-out" voltage of 2.5 V. The "drop-out" voltage is the minimum magnitude of input voltage above^the regulated output voltage required for voltage regulation. Low drop-out (0.5 to 1 V) regulators are usually designed with a PNP series- pass transistor. Ascan be seen, the maximum efficiency of a 5-V series-pass regulator is about 67%. The efficiency drops as the input voltage increases. It is only 42% with a 12-V input voltage. It is evident that its efficiency increases with increasing output voltage. 1.3.2 Linear Shunt Regulator The shunt regulator employs a shunt element that varies its shunt current requirement to account for varying input voltages Or changing load condi- tions. A basic shunt regulator is shown in Figure 1.3. The output voltage of the shunt regulator is given by fr'out=K iD -(/, oad + / s ) J R s , 0-9) Power-Switching Converters 0.75 Figure 1.2 Efficiency versus input voltage for a 5-V series-pass regulator with a drop-out voltage of 2.5 V. ■ J Wr 's -\ ' Shunt transistor H 1 ^0 ^0 load — ^»— Error Amplifier Base Driver Reference Voltage "X" 1 ^0 1 Figure 1.3 Shunt voltage regulator. Introduction to Switching Converters where 7 S is the shunt current. The shunt regulator is less sensitive to input voltage transients, therefore, it does not reflect load current transients back to the source, and it is inherently short-circuit proof. The efficiency of the linear shunt regulator is *oiitJioad __ ^load hoa& R s (1.10) V ~ ^inWoad + /s) /load+/s ^in As can be seen, the efficiency of the linear shunt regulator decreases with increasing /** due to larger power dissipation in R s . The efficiency also decreases with increasing shunt current, / s . In general, the efficiency of the shunt regulator is smaller than that of the series-pass regulator. Despite many drawbacks, linear voltage regulators such as the 1.5-A, 5-V UA7805CKC series regulator and TL431CP shunt regulator are com- mercially available at relatively low costs. They are most cost effective for low-power applications. However, power dissipation becomes a major prob- lem for applications above an output current of about 5 A. 1.4 SWITCHING CONVERTERS A simple DC-DC switching converter circuit consists of two semiconductor switches (usually one switching transistor and one switching diode), one inductor, and one capacitor, as shown in Figure 1.4. The arrangement of these switches and storage elements defines the topology of the switching converter. In the case that the load is a direct-current motor, the DC-DC switching converter is commonly known as a chopper or a DC motor drive system. The principal merits of the switching converter are its high conver- sion efficiency and its high power packing density, which result in significant weight reduction. However, switching converters often require complex control circuits, and noise or electromagnetic interference (EMI) filters. An input line filter is often required in some applications. Figure 1.4 Basic switching converter components. 8 Power-Switching Converters 1.4.1 Basic Switching Converter with Resistive Load The fundamental concept of the switching converter can be understood from the simple switching circuit shown in Figure 1.5(a). The switch opens and closes for durations of DTand (1-D)T, respectively. D, the duty cycle, is the ratio of the on-time t on to the switching period T, viz., D — -/ f (1.11) where f s is the switching frequency. During the interval DT, the load resistor is connected to the input power source V s . However, the load resistor is disconnected from the input power source during the interval (J—D)T. The resulting voltage across the load resistor v out (r) is a chopped version of the input power source V s as shown in Figure 1.5(b). The average output voltage V a is given by DT 4 J K*. VJOT DV S . (112) Thus, the average output voltage is proportional to the duty cycle D. When the duty cycle is one, the output voltage will be the same as the input voltage. In this case, there is no switching action and the switch is closed at all times. The average load current 7 a is found from Ohm's law: (1.13) (1-D)T DT == 14 DT (a) T (b) ->~t Figure 1.5 (a) Fundamental switching converter circuit, (b) Voltage waveform across output resistor, /J L . Introduction to Switching Converters The root-mean-square value of the output voltage is V. out.rms DT I f VMt=V s VD. (1-14) The average input power of this switching converter, assuming a V^ drop across the switching transistor, is simply The output power P Q is p^LjiJ^zJ^dt^^^J^L. 0-16) -*r— u ' = t— rt Thus, the conversion efficiency is ■P, _ K s - K re (U7) ^ Pin Ks ' As can be seen from Equation (1 .17), the conversion efficiency increases with increasing input voltage, V s . This is in contrast to the series-pass linear converter. The output voltage can also be expressed in terms of a Fourier series as CO CO V ov , t (t) = a + Y^a n cos (2on/i0 + Yl b " sin ^ 2m, f^' {lAS) n=l where a is the average value 2w a n = if /(0 cos(27rn/ s 0d(w0 - 1 9 > and 2ir b n = i J /(0 sin(2,r«/- s 0d(w0. ( ] - 20 ) 10 Power-Switching Converters Now consider the case Z> = 0.5; the cosine terms are zero since the voltage waveform is an odd function and the Fourier series reduces to n=\ V s [1 - cos (2£>«7r)]sin(2-»7w/ s mt (1-21) The first term in Equation (1.21) (i.e., DV S ) is the average, or DC value, of the output voltage. The magnitude of the fundamental component (f s ) of the output voltage is calculated as Foi = K s( l-co S ^) = 0637 ^ (1.22) or 63.7% of the input source voltage V s . Similarly, the third harmonic (3/ s ) is 0.2 1 K s or 2 1 % of V s . Figure 1 .6 shows the harmonic spectrum of the output voltage of the fundamental switching converter with a 50% duty cycle. Since the current waveform follows the voltage waveform, the harmonic content is similar to the voltage waveform except that it is divided by the load resist- ance. The discontinuous input source current contributes to EMI. There is no practical application for this simple switching converter (except for resistive heating) due to the high harmonic contents of its output voltage. A typical switching converter would have a low-pass filter between the DV* 0.637 V s 0.21 K 1 0.127 V. ± 24 34 44 54 64 Figure 1 .6 Harmonic spectrum of the output voltage for the fundamental switch- ing converter. Introduction to Switching Converters switch and the load to filter out the frequency components starting at/ s and keeping only the DC component. 1 .4.2 Basic Switching Converter with #? L Load With an R L load such as a DC motor and the addition of a second switch as shown in Figure 1 .7 the current waveform flowing through the load can be made to be continuous. The second switch is necessary since the inductor current cannot be interrupted abruptly without causing high-voltage spikes. The operation of this switching converter can be divided into two modes: S, on/S 2 off (mode 1) for 0<t<t on and 5, off/5 2 on (mode 2) for t on <t<T. The equivalent circuit for mode 1 and the voltage across the J? L load are shown in Figure 1.8(a) and (b), respectively. During mode 1, current flows from the input source V s to the _R L load. Using KirchofPs voltage law, at (1.23) where V emf is the back emf of the DC motor. The current f,(0 during this mode of operation can be solved using the Laplace transformation assuming that the initial current is /,, i.e., i,(* = 0) = /,. Taking the Laplace transform- ation of Equation (1.23) with the initial condition of J u we have ^ = J?/, (s) + Llsl^s) - /,] + — 5 s (1.24) Figure 1 .7 Simple switching converter with an /? L load. 12 Power-Switching Converters ON ->2 6 OFF' \ Vrl •'•i "*»r DT a) T (b) -> f Figure 1.8 (a) Equivalent circuit for mode 1 with S, on/S 2 off. (b) Voltage waveform across the i?L load. Solving for Ji(s~): [s s + (R/L)J + - R \s s + (R/L)J ' s+(R/L)' Taking the inverse Laplace transform, the current i'i(f) becomes cn-fwfi-e-'x) h (0 = f L + h e~' T (1.25) (1.26) for 0<t<t on . During mode 2, Si is switched off while S 2 is switched on. The equivalent circuit is shown in Figure 1 .9(a). The load current, i 2 (f), continues to flow through S 2 - From the Kirchoffs voltage law, 0=iW 2 (0 + £-^+^cn.r- (1.27) Assuming an initial current of i 2 and solving Equation (1.27), the current i 2 (t) is hit) :/2e -'f_%£ (l-e-'z). (1.28) For a large inductance value compared to the resistance value, or a large time constant (L/R), i 2 (t) decreases linearly. Hence, the current waveforms for i,(0 and i 2 (t) are almdst linear as shown in Figure 1.9(b). Equations (1.26) and (1.28) are valid only for continuous current flow in the inductor. The load currents i"i(f) and i 2 (t) would be continuous if the time constant, L/R is much greater than the switching period, T. This means that the switching frequency, f s , of the switching converter must be much larger than RIL. Introduction to Switching Converters 13 v s m *• t Figure 1 .9 Equivalent circuit for mode 2 with S, off/Sj on. (b) Current waveform through the RL load. 1 .5 PRINCIPLES OF STEADY-STATE CONVERTER ANALYSIS If the duty cycle D is held constant at a fixed switching frequency over a large enough number of switching cycles; for example, n cycles, then the current and voltage waveforms would reach a point where they would start repeating every T seconds. This means that the current and voltage wave- forms become periodic, with period T; or f((n + 1)7) = UnT) and v((« + 1)7) = v(«7). This condition is known as the steady state. There are two very important principles that describe the steady-state operation of switch- ing converters: the volt-second balance-on the inductor and the charge balance on the capacitor. These two properties will be used throughout the book to analyze the steady-state operation of various switching con- verters. 1.5.1 Inductor Volt-Second Balance The steady-state condition imposes a periodic behavior of the current flow- ing through the inductor; thus, (1-29) i h (nT) = i L ((n+i)T). Also, v L = L diL dt ' (1.30) 14 Power-Switching Converters Integration over one switching period yields: (n+\)T i L ((« + 1)70 - i\XnT) = j- J v L (0df 0-31) nT Since the left-hand side of Equation (1.31) is zero, then the right-hand side must be zero too, i.e., (n+l)T 0= [ v h (t)dt. (132) nT " "" • Equation (1.32) states that the integral of the voltage across the inductor along a switching period must be zero for the steady state. The integral has units of volts-second; giving the name of volt-second balance to this prop- erty. An intuitive analysis shows that if the integral of the voltage across the inductor along a switching period would not be zero, then the current amplitude would continuously increase. 1 .5.2 Capacitor Charge Balance A similar analysis can be applied to the capacitor. The equation defining the relationship between the voltage across and the current flowing through a capacitor is: ; c (o = ^f- o- 33 > The integration of this equation over one switching period yields: (77+1)7- v c ((n+l)T)-v c (nT) = ^ J Ut)dt. (1.34) nT Since the left-hand side of Equation (1.34) is zero, then the right-hand side must also be zero; i.e., (/i+i)r 0= [ kWt. (I- 35 ) nT Equation (1.35) states that the integral of the current flowing through the capacitor along a switching period must be zero for the steady state. The Introduction to Switching Converters 15 integral has units of Ampere-second; giving the name of Amp-second balance (or charge balance) to this property. An intuitive analysis shows that if the integral of the current flowing through the capacitor (or the accumulated charge) over a switching period would not be zero, then its voltage amplitude would continuously increase. PROBLEMS 1.1. A linear shunt regulator shown in Figure 1.3 has an input supply of 12 V. The load requirements are a constant 5-V supply to some logic circuitry at a current of 0.5 A. As an engineer, you are required to select the appropriate R s value, given that the shunt current, I s , is 10% of the load current, 7 L - Determine the efficiency of the shunt regulator, neglecting the power dissipation across the sampling resistors R-, and R 2 . What effects do the choice of i? s have on the efficiency? 1.2. The fundamental switching converter shown in Figure 1.7 has a resist- ance value of 1 n and an inductance of 1 H, V s = 3.72 V, and a K ref =0 V. During the interval of <t<\ sec, S, is on and S 2 is off. Si is off and S 2 is on during the interval of l<f<2sec. The current flowing through the inductor at the beginning of the switching cycle is 1 A. Determine the peak-to-peak ripple current in the inductor during the first switching cycle. Draw and label the waveforms for the current flowing through the inductor and the voltage across the resistor. 1.3. The fundamental switching converter of Figure 1.5 converter has a resistive load of 10 ft and an input voltage of 48V. The switching frequency is 1 kHz with a duty cycle of 50%. The semiconductor switch has a voltage drop of 1 V in its on-state, (a) Determine the average output voltage and the rms output voltage of this switching converter, (b) Using Fourier series, express the output voltage in terms of their fundamental component and the next two higher harmonics. Find the rms value of the fundamental component of the output voltage. 1 .4. Determine the duty cycle for the maximum ripple current to occur in a fundamental switching converter shown in Figure 1.7 with an i? L load. Also determine the maximum ripple current for this converter. 1.5. For the converter of Problem 2, draw the voltage across the inductor and calculate its integral along a switching period. 1.6. Repeat Problem 2 fori) = 0.25. 1 .7. Consider a power converter that has reached the steady state, (a) Show that the average power absorbed by the inductor in one switching;Cycle is zero, (b) Show that the average power absorbed by the capacitor in one switching cycle is zero. 26 Power-Switching Converters REFERENCES 1. L. Brush. DC-DC converters targeting new directions, Special EDN supplement, Power Technology, Part I: Powering OEM Systems, Cahners, January 2002. 2. A. Bindra, Integrated magnetic components continue to play a vital role, Power Electronics Technology, March 5, 2003. 3. PETech Staff, Multiphase dc-dc controllers, Power Electronics Technol- ogy, November 3, 2003. 4. S. Choudhury and M. Harrison, DSPs simplify digital control imple- mentation of SMPS, Texas Instruments, Dallas, Power Electronics Tech- nology, July 1,2003. Basic Switching Converter Topologies 2.1 INTRODUCTION The word topology referslo-the science of place. The topological properties of a circuit are those invariant with stretching, squeezing, bending, or twisting of the circuit graph. Two networks are topologically equivalent if they differ only in the circuit elements that make up their branches [1]. The switching converter consists of a number of storage elements and switches which are connected in a topology such that the periodic switching actions of the switches control the dynamic transfer of power from the input to the output to produce a desired DC conversion at the output. The storage elements (inductor and capacitor), in general, have to be connected in such a way that they form a low-pass filter to yield a low output ripple voltage. The two fundamental topologies of switching converters are the buck converter and the boost converter. Most of the other topologies are either buck-derived or boost-derived converters since they are the topological equivalent to the buck or the boost converter. The buck-boost converter is a unique cascade com- bination of the buck and boost converters that results in output voltage 17 18 Power-Switching Converters inversion. The forward converter and the push-pull converter are examples of buck-derived switching converters. Flyback and Cuk switching converters are derived from the buck-boost converter. The resonant converter employs a resonating inductor-capacitor (LC) tank circuit to shape the voltage or current waveform of its switching transistor from the typical rectangular pulses into a sinusoidal waveform. Other topologies, such-as the single- ended primary inductance converter (SEPIC), are a derivative of the Cuk converter. The analyses of the buck, boost, buck-boost, Cuk, and resonant switch- ing converters are performed in steady-state. Steady-state signifies that the duty cycle D is held constant at a fixed switching frequency over a sequence of switching cycles; for example, n cycles: this feads to the current and voltage periodicity requirements of i'(0) = i{nT) and v(0) = v(nT), where n is the num- ber of switching cycles during steady-state operation. It is important to realize that switching converters are inherently nonlinear electronic systems due to their switching actions. The linearization and state-space averaging techniq- ue for the small-signal analysis of the switching converter is presented in Chapter 6. 2.2 BUCK CONVERTER The basic buck converter using a power MOSFET is shown in Figure 2.1 . In a buck converter, the average output voltage V a is lower than its input voltage, V s . The operation of the buck converter can be divided into two modes, depending on the switching actions of its switching transistor. According to the continuity of the current flowing through the output inductor, the buck converter can be operating either in the continuous mode orin the discon- tinuous mode. 4to Cfe -» in - k -|* 4.(9 ywYV + V L (0 fc(0 ' t 'a ' ' WO Vs tL h^H /*. i v^n + v c (0t c VM.v m ra. Figure 2.1 Circuit schematic of a buck converter. Basic Switching Converter Topologies 19 2.2.1 Continuous Mode Model (0<t<t on ) At the beginning of a switching cycle (at t = 0) during mode 1, the switching transistor Q s is switched on. The equivalent circuit for mode 1 is shown in Figure 2.2. Since the input voltage (V s ) is greater than the average output voltage K a , the current in the inductor i L (0 ramps upward during this interval. The voltage across the inductor L is related to the rate of rise of its current and is given by: di v,(') = L-. (2.1) For a large inductance value, the inductor current i L {i) rises linearly from J, to h during t om therefore, K s - K, = L A =L ^, 'on 'on and the duration of mode 1 is LAI *on — (v s -v a y (2.2) (2.3) Thus, mode 1 is characterized by the storage of energy in the magnetic field of the inductor. Mode2(t on <t<T) Mode 2 begins when the switching transistor Q s is switched off at ' = f on . Its equivalent circuit is shown in Figure 2.3. 4(0 = 1(9 r L V L (0 V s -= v (t),V a Figure 2.2 Mode 1 equivalent circuit for the buck converter (0 < t ^ t on ). 20 Power-Switching Converters i(0 L V L {Q + fcO f t DfwS =F C ■^p— Figure 2.3 Mode 2 equivalent circuit for the buck converter (t on < t t~ T). Since it is not possible to change the current flowing through the inductor instantaneously, the voltage polarity across the inductor immedi- ately reverses trying to maintain the same current I 2 , which had been flowing just prior to switching off of the switching transistor Q s . This phenomenon is called inductive kick. The freewheeling diode Aw conducts since it is forward- biased just as the inductor voltage reverses its polarity. A high-negative voltage spike would appear at the source of the switching transistor Q s if it were not for the presence of D [w . The inductor current falls, as the energy stored in it is transferred to the capacitor and expended by the load. The voltage across the inductor v L (t) is now — V a and its current falls linearly from I2 to I\ in time f fr, K a =L / 1-/2 -'off (2.4) V a =L—. 'off The duration of mode 2 is (2.5) 'off LM (2.6) and the peak-to-peak current ripple in the inductor is (2.7) Basic Switching Converter Topologies 21 The peak-to-peak current ripple in the inductor, AI, is the same during < t £ r on and /„„ s / < T for steady-state operation, A/ = (K - VJlon _ Vat off ^2.8) Substituting f on = DT and t ofT = (1 - Z>)r into Equation (2.8) gives ( V s - V a )DT = K a (l - Z))r (29) or V.=^=V,D. (2-10) The average output voltage K a of the buck converter is the product of the duty cycle D and the input voltage V s . The duty cycle of a voltage regulator implemented with a buck converter is periodically changing in order to maintain a constant average output voltage V a during a load change or an input voltage fluctuation. This periodic change in the duty cycle is accom- plished using a negative feedback scheme with pulse-width modulation discussed in Chapter 5. The on time t on and off time r ofr are defined as LAI LAI '°«- K s -K a ; to "~ V a ■ The switching period T is the sum of t on and r off : (2-11) r = I = , „„ + ,„„- (2-12) LAI LAI _ LV S AI (213) v s -v a v a v a (v s -v a y The current ripple in the inductor, AI, can then be expressed as , _ K 3 (K S - V a )T _ PK S (1 - D) (214) LV S f s L Thus, the peak-to-peak current ripple in the inductor is inversely propor- tional to its inductance value and switching frequency f s . Using KirchofFs current law, the inductor current is i L = i c + io. ( 215 > 22 Power-Switching Converters The average capacitor current I c is zero for a switching period since the output capacitor is charged and discharged by the same amount during steady-state operation. The average inductor current I L is equal to the average output current I a , then charging of the output capacitor occurs whenever i L (i) is greater than I a (i.e., i c (f) is flowing into the capacitor) and discharging of the output capacitor occurs whenever i^XO is less than / a . The change in inductor current, assuming a constant load current, is M L = Af c + Afo =i Ai c - < 2 - 16 ) The charging and discharging intervals, therefore, must be equal dur- ing a switching cycle and are both equal to half the switching period. The average charging or discharging current, which flows for (t on /2) + (/ ff/2) = (772) is i -— (2.17) l c - 4 - The capacitor voltage v c (f) is Vc(») = v c (0)+1 J i c (t)dt (2-18) The capacitor ripple voltage Av c is given by: T/2 , 1 f M „ TM A/ ...„ Av c = v c (0 - v c (0) = - J -dr = — = w ^. (2.19) o Substituting A7 from Equation (2.14) into Equation (2.19), the capacitor ripple voltage is aVc_ f s L Sf s C- 8/2LC • The capacitor ripple voltage Av c is also equal to the output ripple voltage Av , since the output capacitor is connected directly across the load: It can be seen that the output ripple voltage is inversely proportional to/ s 2 and the LC product. Hence, to decrease the output ripple voltage, the product of LC should be large and the switching frequency should be high. Since the output inductor L, and the output capacitor, C, form a low-pass filter in the buck converter, the choice of the values of L and C determines Basic Switching Converter Topologies 23 the cutoff frequency of the output low-pass filter and ultimately determines the amount of switching ripples and spikes in the output. Switching waveforms for the buck converter operating in the continu- ous mode are shown in Figure 2.4. The input current is discontinuous, and a smoothing input filter, consisting of a series inductor and a shunt capacitor, is normally required to reduce electromagnetic interference (EMI). The output inductor current is continuous, due to the freewheeling action of the freewheeling diode. During the on-time, the output capacitor is initially discharged because the output inductor current is smaller than the required load current, /„(*)- However, as the output inductor current increases beyond the current required by the load, the output capacitor is charged. The / 2 -' a 'l-'a Vc(0 = K)(0 - ' Av c -*-t -»-f -*-t DT T Figure 2.4 Buck converter switching waveforms. w 24 Power-Switching Converters maximum capacitor charging current, I 2 — l a , occurs at the end of the on- time, i.e., DT. The maximum capacitor discharging current, I\ — I a , occurs at the end of the switching cycle. It should be noted that the capacitor ripple voltage lags its current by 90°. Neglecting the switching losses, the efficiency of the buck converter can be calculated in terms of conduction losses in the NPN switching transistor Q s and the freewheeling diode £> fw . The conduction losses are JW = Pq, + Pd*. = ll Ron *-f + /o (l - y) Vd*, (2.21) where R on is the on-state resistance of the switching transistor Q s and V Dfm is the diode forward drop, which is current dependent. Thus, the efficiency of the buck converter is (Pout + Ploss) ( V a + /o-Ro„# + (!-/>) VdJ ' (2.22) It is evident that a higher efficiency is achieved by minimizing the R on and the V^. 2.2.2 Discontinuous Mode For a given value of load resistance, the ratio of the peak inductor current 7^ to the average inductor current I L becomes larger as the inductance becomes smaller according to Equation (2.14). The value of L for which z' L = at one and only one point per cycle is defined as the critical inductance, L c . When this happens, the stored energy in the inductor is completely expended just prior to the beginning of the next switching cycle. The peak inductor current, I Lp , is twice the average inductor current, I L , i.e., /,, = 2I L = ^J^-^^i!^, (2.23) The critical inductance L c can be found by assuming an ideal buck converter whereby the input power is equal to its output power. The input power is given as P m =VJs=VJ L D: (2.24) since I s = DI L . The output power is Pom=-^, (2-25) Basic Switching Converter Topologies 25 therefore, VJ L D = %. (226) The average inductor current I L can be found from Equation (2.23), and is _AI_ (V s -V a )D (227) JL 2 2/ s Lc ' Substituting 1 L from Equation (2.27) into Equation (2.26) results in ^ AVs-V^D 2 Vl (2 .2 8 ) s 2/sL,: R • Substituting D = {VJV S ) into the numerator of the left-hand side of the above equation yields V^l-D^ VJ (229) 2fsLc R ' simplifying gives 2f % U ~ R The critical inductance L c is then (2.30) L c = m ~ D \ (2-31) 2/ s As can be seen, the critical inductance L c is directly proportional to the load resistance R and inversely proportional to the switching frequency / s . As/ S increases, L c decreases. Increasing the load current or decreasing the load resistance R also reduces L c . It is important for the inductance not to go below L c when designing for a large load swing. The inductor current i L (f) is not continuous when L is less than L c . The buck converter is said to be operat- ing in its discontinuous conduction mode when this occurs. For a constant inductance L, the buck converter will be operating in the discontinuous mode if the load resistance R is greater than its critical loadxesistance Re- Thus, 26 Power-Switching Converters where R nom is a design parameter and is defined in Ref. 2. This design parameter is evident from Equation (2.31). It is necessary to modify the mode 2 equivalent circuit to account for the energy in the inductor expended before the start of the next switch- ing cycle. Figure 2.5(a) and (b) shows the mode 2 equivalent circuits for the buck switching converter operating in the discontinuous mode. Define t 2 , which is less than the switching period T, as the time at which i L (t) goes to zero as shown in Figure 2.6. From the finite current constraint [1] or the constant volt-second requirement in an inductor, the £ D|w =P C {a)t on <t^t 2 -o o- ZSD,, (a) tz< t ■& T Figure 2.5 Discontinuous mode 2 equivalent circuits for the buck converter. -> t Figure 2.6 Discontinuous-mode inductor current waveform. Basic Switching Converter Topologies *' average inductor voltage per cycle for the buck converter operating in the discontinuous mode is zero in accordance with the equation: ( V % - F a )/ on / s - K a (r 2 - r on y s = 0. (233) Since the average capacitor current I c per switching cycle is zero, for steady- state operation, then the average inductor current I L is equal to the average output current 7 a : J Lf>hfs = _Pa (2.34) 2 R' The voltage across the inductor is related to the rate of increase of its current, thus (K s -K a ) = L^L. (2-35) 'on Simplifying (2.33) and multiplying by/ s gives V.t^f, - V a t 2 fs = 0. (2.36) Solving for trf s in Equation (2.34) and I Lp in Equation (2.35) and substitut- ing into Equation (2.36), we have V 2 +V V— ^2__ v 2 — ^h—=Q. (237) K a + r.". (1 _ D)L V s (!_£))£ The open-loop voltage conversion ratio VJV S of the buck converter in the discontinuous mode of operation can be obtained by solving the above quadratic equation: V s 2L(1 - D)/L c or K, V % 1 + y/\ + (4L(1 - D)/D 2 L C ) ,L<L C . (2.39) Figure 2.7 shows the voltage conversion ratio versus the duty cycle of the buck converter operating in the continuous and discontinuous modes for several values of L/L c . 28 Power-Switching Converters 0.2 1 i 1 ' Discontinuous mode — i i j ^x 0.8 L/L c = 0A ^ yS yf 0.6 / / ^s. Continuous mode 0.4 L/Lc = 0.5 0.2 0.4 0.6 0.8 Figure 2.7 Open-loop voltage conversions ratio versus duty cycle of the buck converter operating in continuous and discontinuous modes. In the discontinuous mode of operation, the average output voltage increases rapidly at small L/L c values with increasing duty cycle and then asymptotically reaches the input supply voltage V s . As the L/L c value approaches 1, the voltage conversion ratio versus duty cycle plot becomes more linear. The voltage conversion ratio versus duty cycle in the continuous mode of operation (UL C > 1) is linear with a slope equal to 1. The time t 2 at which the inductor current reduces to zero can be obtained by substituting Equation (2.38) into Equation (2.36). Thus, ti = (21.(1 - £>)/L</ s ) V(4Z.(1 - D)/L c ) + £P - D for L< L c (2.40) Figure 2.8 shows the t 2 IT ratio versus the duty cycle of the buck converter in the discontinuous mode of operation. As shown, t-JT decreases with decreasing LIL C values for a constant duty cycle. Furthermore, t 2 /T decreases more rapidly for small L/L c values, as the duty cycle decreases. The energy stored in the inductor is less because of small LIL C values in the discontinuous mode; therefore, the discharge time Basic Switching Converter Topologies 29 \ \ UL c = 0.5 \ \ ULc-- = 0.3 \ ui^ -0.1 i 1 Figure 2.8 The t 2 IT versus duty cycle of the buck converter in the discontinuous mode of operation. t 2 is smaller. Using L'Hopital's rule in Equation (2.38), it can be shown that as the inductor value reduces to zero, the average output voltage V. A ap- proaches the input voltage V s . The switching waveforms for a discontinuous mode of operation are shown in Figure 2.9. Discontinuous mode of operation islrequently used at low power levels, especially where large output load ranges are possible. It is common practice to design the switching converter to operate either in the continuous or the discontinuous mode, avoiding the change from one mode of operation into the other during normal operation. This is to avoid changes in the switching converter model that may lead to serious regulation or stability problems. If the load of a buck converter is suddenly removed, the output voltage of an open- loop buck converter will rise to the same level as the input voltage. In a closed- loop buck converter, the output voltage will fall to zero with a time constant dependent on the values of the output capacitance and any leakage resistance inherent in the circuit. The advantages oflthe buck converter are its ability to easily control output voltages and currents during turn-on and turn-off and 30 Power-Switching Converters o U 1"s r^ -> t \A vt *>*, «. = <«. j£! -^-i (a) (b) Figure 2.9 Buck converter waveforms for (a) Z, > A: and (b) L < L c . under fault conditions. The boost converter, however, does not possess such advantageous properties. Example 2.1 . The buck converter shown in Figure 2. 1 has an input voltage of 10 V. The switching frequency is 1 kHz. The load requires an average voltage of 5 V with a maximum ripple voltage of 20 mV. The maximum ripple current of the output inductor is 0.2 A. Determine: (a) the duty cycle, (b) the output inductance, (c) the output capacitance, and (d) the output capacitance if the switching frequency is increased to 10 kHz. Solution. The given parameters for the buck converter are: V s = 1 V,/ s = 1 kHz, V a = 5 V, AK a =-20mV, and M L = 0.2 A. (a) From Equation (2.10), '-$-*-** Basic Switching Converter Topologies 3* (b) From Equation (2.14), DVAl-D) 0-5(lO)(05) _ nm „„_ 17SmH _ f s M 1000(0.2) (c) From Equation (2.20), V S D(\ - D) _ 10(0.5)(0.5) _ } ^ n Sf?LbV a 8(1000) 2 0.0125(0.02) (d) The duty cycle does not change since the output voltage remains at 5 V. The output inductance is 0.5(10)(0.5) 25H 10000(0.2) Thus, the output capacitance is C = 10 (°- 5 ><°- 5 > = 125uF. 8(10000) 2 0.00125(0.02) This example illustrates that increasing the switching frequency by an order of magnitude decreases the values of both the output inductor and capacitor by an order of magnitude. Hence, increasing the switching fre- quency of the buck converter, assuming that increased switching losses do not degrade its performance, decreases its size, weight, and cost. 2.3 SYNCHRONOUS RECTIFIER The current technology in computer microprocessors and peripherals requires power supply voltages of 1.2 V at high currents. An important limitation in efficiency is the voltage drop across the diode, V d . When the output voltage of a buck converter is calculated, considering V d yields: F a = DK s -(l-D)K d . < 2 - 41 ) It is obvious that the larger the voltage drop across the diode is, the smaller is the resulting output voltage. The ability of the MOSFET channel to conduct current in both directions makes it possible to replace the Schottky diode by a synchronous rectifier, which is gated when the diode should conduct. The gate signal to this device is complementary to that of the main switch M x . Figure 2.10 shows an example of a buck converter with a synchronous rectifier M 2 . 32 Power-Switching Converters V R ^= Figure 2.10 Synchronous rectifier. Sometimes, the MOSFET may not be fast enough, and a Schottky diode is connected in parallel to assist during the turn on. Once M 2 is completely on, the voltage drop across its channel resistance may be much smaller than the forward voltage drop of the diode and it will take on all the current. The synchronous rectification enables the current through the inductor to reverse its direction; thus, the synchronous buck converter of Figure 2.10 works only in the continuous conduction mode. 2.4 BOOST CONVERTER The boost converter is capable of providing an output voltage, which is greater than the input voltage. It is also known as a ringing choke or a step- up converter. A boost converter using a power MOSFET as the switching transistor is shown in Figure 2.11. Its switching waveforms ane-shown in Figure 2.12. The operation of the boost converter can also be divided into two modes, depending on the switching actions of its switching transistor. Similar to the buck converter, W 'Dfw(0 l a ' ' 'o(0 v (t) Figure 2.1 1 Circuit schematic of a boost converter. Basic Switching Converter Topologies 33 DT T+DT Figure 2.12 Waveforms for the boost converter. the boost converter can either be operating in the continuous or discontinu- ous mode. 2.4.1 Continuous Mode Model (0<t< to„) Mode 1 begins when the switching transistor Q s is switched on at t = and it terminates at t = t on (i.e., 0<fS t on ). The equivalent circuit for mode 1 is shown in Figure 2.13. 34 Power-Switching Converters WO A fc 'a Vc(l)4 C WO LOAD V o (0. V a Figure 2.13 Mode 1 equivalent circuit for the boost converter (0 < t £ t on ). The diode D fw is reverse biased since the voltage drop across the switching transistor Q s is smaller than the output voltage. The inductor current i L (t) ramps up linearly from I\ to I 2 in time t on : *on 'on The duration of this interval t on can be expressed as (2.42) *on — " LAI (2.43) The energy stored in the inductor is E ^ A/ > 2 = 2Z^'o" (2.44) The output current during this interval is supplied entirely from the output capacitor C, which is chosen large enough to supply the load current during the on-time, f on , with a minimum specified droop in output current. Mode 2 (t^ < t< T) Mode 2 begins when the switching transistor Q s is switched off at / = / on . The equivalent circuit for this mode is shown in Figure 2.14. Since the current in the inductor cannot change instantaneously, the voltage in the inductor reverses its polarity in an attempt to maintain a constant current. The current, which was flowing through the switching transistor Q s , would now flow through L, C, diode Z> fw , and the load. The inductor current falls Basic Switching Converter Topologies 35 V M.V. Figure 2.14 Mode 2 equivalent circuit for the boost converter (/ on < t < T). until the switching transistor Q s is turned on again in the next cycle. The inductor delivers its stored energy to the capacitor C and charges it up via D rw to a higher voltage than the input voltage, V s . This energy supplies the current and replenishes the charge drained away from the capacitor C when it alone was supplying the load current during the on-time. The voltage across the inductor is (V s - K a ) and its current falls linearly from 7 2 to 7, in time f ff: V s -V a h-h 'off (2.45) or V S = L A/ 'off The duration of the interval t oft can then be expressed as LAI 'off — it - 77 ■ (2.46) (2.47) Since the change in the peak-to-peak current M is the same during ' on and / fr for steady-state operation, it can be shown from Equations (2.43) and (2.47) that A/ V s t on (K a -F s )f olT (2.48) L L Substituting '„„ = Z>rand t o{T = (1 - U)rinto Equation (2.47), we have V S DT = (V a - F s )(l - D)T = K a (l - D)T - K,(l - D)T. (2.49) 36 Power-Switching Converters Simplifying the above equation, V S DT = V a (\ - D)T -V S T+ V S DT (2.50) or K 5 = V a (l - D). (2.51) The average output voltage V a for a boost converter is V, 1 -£>' (2.52) Thus, the average output voltage V a is inversely proportional to (l-D). It is obvious that the duty cycle D cannot be equal to 1 because there would not be any energy transfer to the output. Assuming a lossless boost converter, then K s / s =K a / a =^£^. (2-53) The average input current I s can be expressed as 7 S = /a . (2.54) s (l-D) Note that the average output current J a is reduced by the factor of (1— D) from the average input current since the output power can only be at best equal to the input power. The switching period T is the sum of t on and t ofr : 1 _ LA7 LAI LAIV a 'Is ~ fon + ' ofr ~~vT + v a -v~ v s (v a - v s y T = -=t on + t o!T = - 7 ^ + — 7r = -rrrr, ;tt- ( 2 - 55 ) The peak-to-peak inductor current ripple AI is A1 = V S (K-V S )T ^ (K/(l-D))-Vs (256) LV a - s f s LV a Simphfying the above equation, we have A/=-^. (2-57) Thus, the magnitude of the peak-to-peak inductor current A7 is inver- sely proportional to the switching frequency f s and the inductance L. Basic Switching Converter Topologies 37 Comparatively speaking, A7 is larger in magnitude for the boost converter than the peak-to-peak current ripple in the buck converter, as shown in Figure 2.15. For a constant VJf s L, the peak-to-peak inductor current ripple in the buck converter is smaller than the peak-to-peak inductor current ripple in the boost converter by a factor of (1— D). When the switching transistor Q s is switched on, the capacitor-supplies the load current for the entire on-time. Thus, the average capacitor current, 7 C , is equal to the average output current 7 a during this interval. During the off-time interval, the output capacitor is charged. The capacitor charging current decreases linearly from an initial value of 72 — 7 a to a final value of 7, - 7 a as shown in Figure 2.12. For steady-state operation, the average capacitor charging current during the off-time interval must be equal to the average capacitor discharging current during the on-time interval. The capacitor ripple voltage can be found by recognizing that the average capacitor current during the on-time is equal to the average output current 7,. Thus, Av c = v c Ve(0) = iJ7 a d, = ^. (2.58) A/ Boost converter (KD) Buck converter KD (1-0) Figure 2.1 5 A comparison of the peak-to-peak inductor ripple current versus the duty cycle for the buck and boost converters at a constant K = VJf s L. 3 g Power-Switching Converters From Equation (2.50) v V > _ V > T - V ' T - (2-59) a \-D T-DT T-t on or T-t on = (2.60) The on-time, t on , can also be expressed as , T V * T K ~ Vs (2-61) Substituting Equation (2.61) into Equation (2.58), / a (K a -K s ) /.(K.-K,) (262) l-D /s Simplifying the above equation, . / a «n - n + dk.)/(i - j>)) _ / a i? (263) AVc_ (Ks/a-WsC /,c The peak-to-peak output ripple voltage, Av„, is equal to the capacitor peak- to-peak ripple voltage, Av c . It is evident that Av can be reduced by either increasing the switching frequency or the capacitance of the output capaci- tor. The inductor is used for energy storage, and it does not act as a part of the output filter. Therefore, the peak-to-peak output ripple voltage of the boost converter is generally larger than that of the buck converter. 2.4.2 Discontinuous Mode If the current flowing through the inductor has fallen to zero before the next turn-on of the switching transistor S , the boost converter is said to be operating in the discontinuous mode. The critical inductance, L c , can be derived by assuming that the input power of the boost converter is equal to the output power: Basic Switching Converter Topologies 3 ^ The average inductor current is // = A/ V*D (2.65) 2/sLe" Since the average input current, / s , is also equal to the average inductor current, J L , then V, V S D Vl '' 2/ s L c R ' The critical inductance, L Q , is (2.66) RDd-Df ( 2. 6 7) U ~ 2/ s ■ The boost converter will be operating in the discontinuous mode if the load resistance, R, is greater than its critical resistance, R c , given by R,= Z>(1 - Df (2.68) where R nom is a design parameter equal to 2/ s L[2]. Figure 2.16 shows the mode 2 equivalent circuits of the boost converter operating in the discontinuous mode. The voltage conversion ratio of the boost converter for the discontinuous mode of operation can be derived by imposing a constant volt-second requirement on its inductor. The average voltages across the inductor are V s and (K a -K s ) during the DT and D 2 T intervals as shown in Figure 2.17, respectively. Thus VsD-(V a -V s )D 2 =0, (2.69) where D 2 is defined as (t 2 — t on )/T. The average input current, I s , is equal to the average inductor current, I L , in the boost converter, where / =Ih. = IjR (2-70) L 2 2Lf: 40 Power-Switching Converters 1 St- ± C LOAD V o (0. V a {a)t on <t^t z V (Q, V a Figure 2.16 Discontinuous mode 2 equivalent circuits for the boost converter. V L (0 l ton 1 1— h T (a) Figure 2.17 Waveforms for (a) voltage across and (b) current flowing through the inductor for a boost converter in the discontinuous mode of operation. Basic Switching Converter Topologies 41 The average output current, 7 a , is related to the average inductor current, I L , by a factor D 2 , viz., h =Y± = I L D 2 . (2-72) Substituting Equations (2.70) and (2.72) into Eguation (2.69) yields a quad- ratic equation: Vl -V s V a V ? DL * = 0. (2.73) The open-loop voltage conversion ratio, VJV S , in the discontinuous mode of operation can be found by solving the quadratic equation: K s 2 Figure 2.18 shows the open-loop voltage conversion ratio versus duty cycle of the boost converter operating in both the continuous and discontinuous modes. As shown, the voltage conversion characteristics of the two modes of operation differ from each other only in the rate of increase of the average output voltage. In the discontinuous mode of operation, the voltage conver- sion ratio increases at a much faster rate compared to the voltage conversion ratio in the continuous mode of operation. Thus, the discontinuous mode of operation of a boost converter yields a larger average output voltage at a smaller duty cycle compared to the continuous mode of operation. The discontinuous-mode switching waveforms of a boost converter are shown in Figure 2.19. The input current of the boost converter is continuous. At the initial turn-on of the boost converter, an inrush current with an amplitude of several times the steady-state input current is flowing through the switching transistor. The switching transistor must be able to handle this initial switching stress. It is also important to limit the inrush current so as not to saturate the input inductor. Otherwise, a higher inrush current limited only by the source impedances and parasitic resistances will flow. The output current is always pulsating in both the continuous^nd discontinuous modes of operation. The output voltage is very sensitive to changes in duty cycle; therefore, the design of the feedback circuitry is critical. The effects of component parasitic resistances become quite noticeable when the average output voltage V a is greater than three times the input voltage V s . The boost converter must always have a load connected to its output; otherwise, the 42 Power-Switching Converters V a IV s 10 Discontinuous mode L/Le=0A Discontinuous mode L/Lc=0.5 Continuous mode LI Ld=1.0 0.2 0.4 0.6 0.8 Figure 2.18 Open-loop voltage conversion ratio versus duty cycle of the boost converter operating in the continuous and discontinuous modes. output voltage will continue to rise until a component (usually the output capacitor) fails. If the output of the boost converter is shorted, simply reducing the duty cycle of the switching transistor will not limit the amount of current drawn from the input supply. This is because the switching transistor is not in series with the output. An additional switching transistor in series with the input supply must be added if an overload protection is desired. 2.5 BUCK-BOOST CONVERTER The buck-boost converter is a special cascade combination of a buck con- verter and a boost converter which provides an output voltage that may be less than or greater than the input voltage, with a polarity opposite to that of the input voltage. As such, it is also known as an inverting converter. The Basic Switching Converter Topologies 43 v O S W i i Va i Vs i .. w». 1/ a v s j » /Lp A : .TV / 3r 1 's / N: ./ \ / VM t i Vs > 7 i !/ r / (V a -V s ) tp 'o t ! i/ *- K — w 27 s Figure 2.19 Waveforms for the discontinuous-mode boost converter. basic circuit for a buck-boost converter is shown in Figure 2.20. Its switch- ing waveforms are shown in Figure 2.21 . The operation of this converter can also be divided into two modes, depending on the switching actions of its switching transistor. Depending on the continuity of the current flowing through the inductor, the operation of the buck-boost converter can also be classified as the continuous or discontinuous mode. 44 Power-Switching Converters ^s-= — m "i VbWf C MO Figure 2.20 Circuit schematic of a buck-boost converter. LOAD t i fc(0 'a ' ' WO VoW-Va or t r+or Figure 2.21 Buck-boost converter waveforms. Basic Switching Converter Topologies 45 2.5.1 Continuous Mode Model (0<t<t on ) Mode 1 begins when the switching transistor, Q s , is turned on at t = 0. Its equivalent circuit is shown in Figure 2.22. The freewheeling diode, D fw is reverse-biased since the voltage across the inductor is near the input voltage, V s , assuming that the output voltage, v„(f), is of negative polarity. The inductor current rises linearly from I\ to 7 2 in the time / on : fon 'on The duration of mode 1, t on , can be expressed as (2.75) *on — ' LM (2.76) and the energy stored in the inductor is 2 *-K^)-2^ 2 t 2 . s on (2.77) Mode 2 (ton <t < T) Mode 2 begins when the switching transistor, Q s , is switched off at t on . Its equivalent circuit is shown in Figure 2.23. The polarity of the voltage across the inductor reverses in an attempt to keep its current from changing. Thus, at the instant of turning off, the current that was flowing through the inductor would now flow through L, C, D fw and the load. This current ; C LOAD A V (f) Figure 2.22 Mode 1 equivalent circuit of the buck-boost converter (0 < t r& f on ). 46 Power-Switching Converters 'lm -W- /l(0 -<6 'Dfw ^ C LOAD / c n <c(0 t ik «0 v o (0-^ Figure 2.23 Mode 2 equivalent circuit for the buck-boost converter (/ on <tsT). flowing upward through the output capacitor charges the top end of the capacitor to a negative voltage as previously assumed. The energy stored in inductor L is transferred to the load and the inductor current falls until the switching transistor, Q s , is switched on again in the next cycle. Assuming the inductor current falls linearly from I 2 to l x in time t otT : V a = -L- 'off The duration of this interval, t o{f , can then be expressed as 'off = LM (2.78) (2.79) Since the peak-to-peak inductor ripple currents present during the ' on and t ofr intervals are the same for steady-state operation, it can be shown from Equations (2.76) and (2.79) that A/ = V s t V a t ofT (2.80) L L Rearranging the above equation, V s t on = -V a t ofI . < 2 - 81 ) Substituting r on = £>rand t off = (l-I>)rinto the above equation, V S DT = - V a (l - D)T. < 2 - 82 ) Basic Switching Converter Topologies Simplifying, we get _ VzV-D) (2.83) Vs ~ D ■ The average output voltage, V a , is then KD (2.84) \-D' As can be seen, K a has an opposite polarity to the input voltage K ? . The numerator D is the output conversion factor of a buck converter while the denominator (1-X>) is the output conversion factor for a boost converter. Assuming a lossless buck-boost converter, the input power, (F s 7 S ), is equal to the output power (V a I a ): K/ _ K/ - J a(-^) (2.85) s s — a a — 1 — D The average input current, 7 S , can be expressed as 7 /aZ? (2-86) The switching period, T, is the sum of f on and t o{ f. t_, J., AIL_ML_ ML{V a -Vs) (287) J -'on + 'ofT- ^ ^ KsFa The peak-to-peak inductor ripple current, A/, is then .\i - V * V * T _ KK ( 288 > ai ~Z,(K a -K s ) / s I.(F a -K s )- Simplifying the above equation, we obtain V s (-V s D/(l-Dy) _VsD ( 2.89) A/ - / S L(( - K S D/(1 - Z>)) - F s ) / S L • The peak-to-peak inductor ripple current is, therefore, similar to that of the boost converter. When the switching transistor is switched on, the output capacitor supplies the load current for the entire on-time interval. The average discharging current of the capacitor is equal to 7 a . During the off- time interval, the output capacitor is charged by the stored energy m the inductor. The capacitor charging current decreases linearly from J 2 - h to 48 Power-Switching Converters /, - 7 a during this interval. For steady-state operation, the average capacitor charging current during the off-time interval must be equal to the average capacitor discharging current during the on-time interval. The peak-to-peak ripple capacitor voltage, Av c , can be found by integrating the average cap- acitor discharging current during the on-time interval: 'on 'on Av c = lJ/ c dr = ij/ a df = ^. (2-90) o o f on can be expressed in terms of the input voltage, switching frequency, and average output voltage. From Equation (2.84), with t on = DT Vsitou/T) ^ V s (t on /T) (291) 1 - (t on /T) (t on /T) - 1 ' Multiplying both sides of the above equation by its denominator gives (^_l)K a =K s ^ (2-92) or or ^K a -^K = F a (293) The on-time, t on , can be expressed as VJT V a on V*-V s (K a ^F s )/ s ' Substituting Equation (2.95) into Equation (2.90), we have (2-95) Av hVa (2-96) c ~(K a -K s )/ s C- Substituting Equation (2.85) into Equation (2.96), the peak-to-peak capaci- tor ripple voltage is Basic Switching Converter Topologies 49 A 4( - VsD/V ~ D)) _ hD (297) aVc ~ « - V s D/{\ - D)) - V t )f,C fiC ■ The above result can also be found by recognizing that t oa = D/f s . As can be seen, the expression for the output ripple voltage, Avo, is similar to that for the boost converter and its magnitude can be decreased by either increasing the switching frequency / s or increasing the output capacitor value. Again, the input inductor is used for energy storage and it does not act as part of the output filter. 2.5.2 Discontinuous Mode If the current flowing through the inductor has fallen to zero before the next turn-on of the switching transistor, the buck-boost converter is said to be operating in the discontinuous mode. The boundary between the con- tinuous and discontinuous modes in an open-loop configuration is deter- mined by the critical inductance, L c . The critical inductance can be derived by assuming an ideal buck-boost converter with the input power equal to its output power: K./.=2£. (2-98) The average inductor current is Jl p _ V*D (2.99) L 2 2f s L c - The average input current I s is related to the average inductor current I L by 'on h = I L D. (2 101) Substituting Equation (2.99) into Equation (2.101) and then into Equation (2.98), we get: Yl°L = YL (2.102) 2/sZ.c R ' 50 Power-Switching Converters The critical inductance, L c , is R&V} R(l-Df i-c — " (2.103) JC 1UVI 2/ s The open-loop conversion ratio VJV S can be found from Equation (2.102): V} 2f s L (2.104) or 2f s L (1 - D) V L (1.105) Figure 2.24 shows the open-loop voltage conversion ratio versus duty cycle of the buck-boost converter for the two modes of operation. As shown, the iv a /vy 10 Discontinuous mode L/L c = 0A Discontinuous mode LI 1^ = 0.5 Continuous mode LIL c =\.0 Figure 2.24 Open-loop voltage conversion ratio versus duty cycle of the buck- boost converter operating in the continuous and discontinuous modes. Basic Switching Converter Topologies 51 voltage conversion ratio increases more rapidly for smaller L/L c values. Thus, the discontinuous mode of operation of a buck-boost converter yields a larger average output voltage K a compared to the continuous mode of operation for a similar duty cycle. The output voltage of the buck-boost converter has the opposite polarity with respect to the input voltage. The input current in the buck- boost converter is pulsating. As in the boost converter, a high inrush current is flowing during initial turn-on of the switching transistor. The switching transistor, therefore, must be capable of handling this initial switching stress. Comparisons of the voltage conversion ratio VJV S for the three types of switching converters are shown in Figure 2.25. As shown previously, a linear relationship between the input and output voltages are a characteristic of the buck switching converter. The rapid changing output voltage, when operating at above 50% duty cycle in the boost and the buck-boost switch- ing converters, presents some challenging stability problems in the designing of these switching converters. Example 2.2. The buck-boost converter shown in Figure 2.20 has an input voltage of 12 V and a load resistance of 24 ft. The switching frequency is 10 kHz. The values of the inductor and output capacitor are lmH and 100 |xF, respectively. If the output voltage is required to be twice that of the input, determine (a) the duty cycle, (b) the peak-to-peak output ripple voltage, (c) the magnitude of the average input current, (d) the magnitude of the average inductor current, and (e) the peak inductor current. l(V a /V s )l 0.5 Figure 2.25 Comparisons of the voltage conversion ratios of buck, boost, and buck-boost switching converters. 52 Power-Switching Converters Solution. (a) From Equation (2.84), the voltage conversion ratio for the buck- boost converter is V a D = -2. Therefore, the duty cycle, D, is 2/3 or 66.7%. (b) From Ohm's law, the average output current is i -2jl-?!-ia 7a ~lf-24- 1A - From Equation (2.97), the peak-to-peak output ripple voltage is AK a =^ = ^a_- = 0.667V. a f s C 10000(100 x io- 6 ) (c) From Equation (2.86), the magnitude of the average input current is , _ h*> 2 / 3 _ 2A ys_ T^D~l-(2/3) (d) From Equations (2.86) and (2.100), the magnitude of the average inductor current is / h = l -3A L ~ (1 - D) 1 - (2/3) (e) From Equation (2.89), the peak-to-peak inductor ripple current is n£ = 12(2/3) f s L 10000(0.001) The peak inductor current is /,,pea k = /,+f = 3+^ = 3.4A. 2.6 CUK CONVERTER [4] The Cuk converter can be considered as a series combination of a boost converter followed by a buck converter with the particular feature that the Basic Switching Converter Topologies 53 output boost capacitor is an energy source for the buck section of the system and that both converters share the same switching elements [5] as shown in Figure 2.26. It provides an output voltage which is less than, or greater than, the input voltage with an opposite polarity to its input voltage. It is a derivative of the buck-boost converter in that the energy transfer from the input to the output is achieved by a capacitor rather than by an inductor as in the buck-boost converter. Its switching waveforms are shown in Figure 2.27. Notice that the current flowing through the output capacitor, i'co(')> has been drawn in the negative direction according to the passive sign convention; therefore the waveforms show a change in polarity. The oper- ation of the Cuk converter can be divided into two modes, depending on the switching actions of its switching transistor. The continuous mode of oper- ation of the Cuk converter is discussed below. Model (0<f<f on ) Mode 1 begins when the switching transistor, Q s , is switched on at t = 0. Its equivalent circuit is shown in Figure 2.28. The current flowing through the input inductor, L„ rises. At the same time, the voltage across the energy- transfer capacitor, C„ reverse biases diode D {vl and turns it off. C, discharges its energy to the circuit formed by C„ C , L , and the load. If the current of the input inductor Z. ; rises linearly from I Lil to /^ in-time t on : 'on 'on The duration of this interval, ' on , is (2.106) 'on — Li Ml, (2.107) C, l c ,(t) U> 'loW ayti a: Vco(t)t C o LOAD : J M C o(t) M 'o(0 _ V (t), V a Figure 2.26 Circuit schematic of a Cuk converter. 54 Power-Switching Converters vc o (0 DT T Figure 2.27 Cfik converter switching waveforms. Basic Switching Converter Topologies 55 ■c,(0 Q ^W Lo V o (0. V a Figure 2.28 Mode 1 equivalent circuit for the Cuk converter. Due to the discharge of C„ the current flowing through the output inductor, L„, rises linearly from I Loi to I La2 in time r on , v Q -v a L (I U2 -I Ul ) The duration of t on can, therefore, be expressed as L M U *on — K C t - V a (2.108) (2.109) Mode2({ on <f< 7) Mode 2 begins when the switching transistor, Q s , is switched off at t = t m . The voltage across the input inductor reverses its polarity in order to maintain its current uninterrupted. The diode D fw is forward- biased since the anode is at a higher potential than its cathode. The converter's equiva- lent circuit is shown in Figure 2.29. The energy-transfer capacitor, C„ is charged by the input source V s and the stored energy in the input inductor Li. The load current i (f) is now supplied by the energy stored in the output inductor, L m and the output capacitor, C G . The current flowing through the input inductor, L-„ falls linearly from 1^ to 1^ in time f fr: Vs-Vc^Li 'off The duration for the f ofr interval is 'off UMl, K s - V, (2.110) (2.111) c, ■'■" 56 Power-Switching Converters v [t>. V* a >o Figure 2.29 Mode 2 equivalent circuit for the Cuk converter. where V Ct is the average voltage across C t . At the same time, the current flowing through the output inductor, i io (0, falls linearly from I L<st to I Lol in time / ofr . Therefore, K a = 'off The duration for the t ofT interval can also be^xpressed as toif = 77 • (2.112) (2.113) The peak-to-peak ripple current in the input inductor L„ A I L ., can be found from Equations (2.107) and (2.111): V s t on -{V s - V c ,)t ofT U (2.114) Substituting r on = DT and f fT = (1 - D)T into the above equation and solving for V Ct gives Vc,= 1 -D (2.115) The energy-transfer capacitor stores its energy in the form of an electric field. The electrostatic energy stored in the energy-transfer capacitor is 1 1 Vl 2 ct 2 \\ -Df (2.116) Basic Switching Converter Topologies 57 The peak-to-peak ripple current in the output inductor, A//^, can be found from Equations (2.108) and (2.1 12): A/ _ ( v ct-V a )t on _ V a t o{{ (2.117) L L'o Substituting /on = £>randr ofT = (1 -£>)rinto the above equation, we obtain K rt = -£. (2-118) Equating Equations (2.115) and (2.118) Y± (2.119) \-D D The average output voltage V a is V ~ DV% (2.120) This is similar to the average output voltage of the buck-boost converter. Assuming a lossless Cuk converter, the input power is equal to its output power, and VI -VI - ~ DVs I (2-121) The average input current, / s , is \-D (2.122) This is, again, similar to the average input current of the buck-boost converter. The switching period, T, is the sum of t on and f ofr from Equations (2.107) and (2.111): T- l -t i . bMu ■ ^ A/ A (2.123) Js~ ° n ° V* K-Vc,' Simplifying = LjV^Iu (2.124) v s {Vc,-v s y w 5§ Power-Switching Converters The peak-to-peak ripple current in the input inductor, M L . can be deter- mined from the above equation: K s (Kc,-K 5 ) (2125) U fsUVc, Simplifying A/ ti = V * D (2.126) fsL, ' Thus, the peak-to-peak ripple current in the input inductor is inversely proportional to the switching frequency and its inductance value. The switching period, T, can also be found from Equations (2.109) and (2.113): T- 1 -, -l, J^Ih- - ^° A/l « _ ^^'^ Q127) -£ - 'on + tea - y^ + Va Fa Ka(Kct + Ka) - The peak-to-peak ripple current in the output inductor is K a (Kc,+ K a ) (2128) ^ / s i„K Cl Js*-o Js-L-o Thus, the peak-to-peak ripple current in the output inductor, A/ io , is also inversely proportional to its switching frequency and its inductance value, L . When the switching transistor, Q s , is switched on, the energy-transfer capacitor, C„ discharges its stored energy to L„, C , and the load circuit. The discharging current increases from / iol to I Lo2 . The average discharging current, I Ct , in C, is equal' to the average output current, I a . During the off-time, the energy-transfer capacitor is charged by the energy stored in the input inductor and the input source. The charging current decreases from J La to -//..,. Therefore, the average charging current, /q, is the same as the average input current, J s . The charging and discharging current-time prod- ucts for the energy-transfer capacitor, for steady-state operation, must be equal. The peak-to-peak ripple voltage of the energy-transfer capacitor, Av Cl , is Basic Switching Converter Topologies -*9 /off *oir Since t „ = (1 - £>)rand r = l// s , then , olT = (L^). (2.131) The peak-to-peak capacitor ripple voltage is Av Cl =^^. (2-132) Thus, the peak-to-peak ripple voltage across the energy-transfer capacitor, Av Ct , is directly proportional to its average input current, / s , and inversely proportional to the product of its switching frequency and the capacitance value. Assuming that the peak-to-peak load ripple current, Az" , is negligible, then A/ i _ > = Ai'co- The average charging current of the output capacitor C c , which flows for time 772, is 7 C o = (A/ io /4). Therefore, ^-iT^-iT^-^-Sfe (2i33> or n(l-Z>) DK (2.134) aVc ° SCoI-o/^ 8C0W? ' The peak-to-peak output ripple voltage, Av , is equal to the peak-to- peak output capacitor ripple voltage, Ave, since the output capacitor is connected directly across the load. The most effective way to reduce the output ripple voltage is to increase the switching frequency, since the output ripple voltage is inversely proportional to the square of the switching frequency. The input and output currents of the Cuk converter are continuous, which reduces EMI problems. The output ripple voltage and ripple current of the Cuk converter are much smaller than those of the buck-boost con- verter. A substantial weight and size reduction of the Cuk converter over the buck-boost converter is the result of a smaller output filter inductor, L OJ and a smaller energy-transfer capacitor C t , because the capacitive energy storage in a Cuk converter is more efficient than the inductive energy storage in a £Q Power-Switching Converters conventional buck-boost converter. The switching transistor and the free- wheeling diode in the Cuk converter have to carry the currents flowing through both the input and output inductors. At first sight, it seems that the Cuk converter has higher DC conduction losses when compared to the conventional buck-boost converter. However, both types of switching con- verters have been shown to have the same DC conduction losses in the ideal case when both the parasitic resistances in the input and output inductors are neglected [6]. In fact, the Cuk converter has been shown to have an overall higher efficiency when compared to the conventional buck-boost converter with the same component values and output requirements. Fur- thermore, the use of coupled inductors in the Cuk converter has been shown to reduce both the output current ripple as well as the output switching ripple [7]. Example 23. The Cuk converter shown in Figure 2.26 has an input voltage of 48 V. The switching frequency is 64 kHz. The magnitude of the average output voltage is 36 V across a 9-fl load resistor. The maximum ripple voltage across the energy-transfer capacitor is 0.5 V. If U = 10 mH, L = 1 mH, and Co = 100 nF, determine (a) the duty cycle, (b) the value of the energy-transfer capacitor, C„ and (c) the peak-to-peak ripple current in L,. Solution. (a) From Equation (2.120), the duty cycle is D _ _VJX 1 _ = __C36/48)_ = {1 + {VJV S )) (1+ (36/48)) (b) From Ohm's law, the average output current is a R 9 From Equation (2.122), the average input current is DI a 0.429(4) _ 3A /s ~~ (1 - D) (1 - 0.429) The value of the energy-transfer capacitor can be found from Equation (2.132): c /sd-D) _ 3(1- 0-429 ) _„ |F C, ~ /sAvc, 64000(0.5) Basic Switching Converter Topologies (c) From Equation (2.114), the peak-to-peak ripple current in U is A/ , _ Y*ZL = 48(0-429/64000) = u ~ U 10 x 10- 3 2.7 CONVERTER REALIZATION WITH NON1DEAL COMPONENTS In practical applications, components do not always behave as predicted. Unexpected parasitics and other effects may result in a capacitance that is a tenth of what was expected, or even worse, the capacitor may be acting like an inductor or the inductor acting like a capacitor. So far, the basic configurations of DC-DC switching converters have been analyzed considering ideal components. This section introduces a non- ideal model for capacitors and inductors and analyzes the impact that the nonidealities, including the semiconductor losses, have on the behavior of a switching converter. A buck converter is used as an example. 2.7.1 Inductor Model Figure 2.30 illustrates the equivalent circuit model for a real inductor with parasitic elements. Most inductors can be represented with an acceptable degree of accuracy by one of the circuits shown in Figure 2.30. Circuit A typically represents an inductor that uses a magnetic core material, such as ferrite or powdered iron. Circuit B represents most nonmagnetic core in- ductors, commonly referred to as air cores. Most inductors are used well below their self-resonant frequency (SRF) and the basic three-element inductor models will be very accurate under these conditions. The SRF of the inductor occurs when the inductive reactance (XL) is equal to the capacitive reactance (XC) of the inductor. The impedance of the inductor is at its maximum and would be infinite if there were no core losses or if the resistance of the inductor were zero. Above the SRF, the XC exceeds XL and the inductor behaves like a capacitor. As the frequency increases above the SRF, the inductor will go through other resonant phases, caused by secondary parasitic elements. Modeling this behavior requires a more complex equivalent circuit. For this reason, the typical useful range for the three-element inductor models is the SRF of the inductor plus about 25% [8]. The parasitic capacitor is usually very small. In switching applications it charges fast to the voltage applied to the inductor terminals contributing 62 Power-Switching Converters Figure 2.30 Inductor model. with a current spike; after that no further current circulates through it. Therefore, an RL model is normally used to model power converters. 2.7.2 Semiconductor Losses The switch, implemented with a BJT or a MOSFET, can be represented in the on state by a resistance (*„„)- A good model for the forward biased diode is a voltage source (F d ) in series with the dynamic resistance of the diode (.R d ). Other parasitics like capacitors and inductors are not consid- ered here. Figure 2.31 represents a buck converter that has been modeled v«- PWM -=- V d dpC <RL Figure 2.31 Equivalent circuit of a buck converter including losses. Basic Switching Converter Topologies 63 including the losses of the inductor and the semiconductors. During T on , the inductor voltage is VL„ = (Vs ~ V a ) - h(Ron + *s). < 2135 > During r o) r, the inductor voltage is v Lo(I = -Vi -V a - h{R& + R s ). ( 2136 > For the steady-state operation, the time-voltage product in the inductor must be null; thus Z>v Lon = (l-DK o(r . (2J37) Then D{(V S - V a ) - h(R m + « s )} = (1 - D){ - V & - K, - 7 a (/?d + i?s)}- (2-138) Approximating 7 a = VJR^ and assuming that R m = R d , the expression for the duty cycle can be derived as: Vq + K a (l + (IR „ + Rs)/Rl» (2 139) V. + V d It is clear that the losses demand a larger than the ideal duty cycle for fixed V a and V s . Note that if V & = R on = R s = 0, then the duty cycle adopts the ideal value. The expression for the average output voltage yields v 2>n-(l-D)Ka ( 2.140) 3 {l+((Ror,+Rs)/RLli)' Therefore, for a fixed D and K s , the losses reduce the output voltage. 2.7.3 Capacitor Model The simple RLC model of Figure 2.32 is often considered a good representa- tion of the capacitor in varying frequency applications. The resistive element is known as the effective series resistance (ESR), while the inductive element is the effective series inductance (ESL). However, things are never as simple as they seem. For example, the resistive element changes with frequency and elec- trolytic capacitors have a steep capacitance roll-off at higher frequencies [9]. The ceramic capacitor model is distinguished by a frequency- dependent resistive element that seems to result in a minimum ESR at or 64 . Power-Switching Converters -AA/V r-ry^r^ 1|_ Figure 2.32 Capacitor model. near the SRF of the capacitor. At the SRF the capacitive reactance and the inductive reactance cancel each other; thus, the capacitor gets reduced to its ESR. Though the capacitance may decay by 1% per decade of frequency, this is insignificant in modeling the performance and is usually disregarded. The tantalum capacitor shows a strong dependency of the capacitance with frequency, which can decay 20% or more per decade. This has been explained by different RC-ladders to define the performance. Consider now that the ideal capacitor of the output filter of the buck converter of Figure 2.1 is replaced by its RLC model. A capacitor with a large ESL would produce spikes on the capacitor voltage due to the dijdt. Since the ESL is not usually evident when the right capacitor is chosen, only the effect of the ESR will be analyzed. In the steady state, the average current through the capacitor is zero, with the current ripple through the inductor (AT) becoming the effective current through the capacitor. The M will produce a voltage drop across the ESR that will add to the output ripple voltage. The magnitude of this extra ripple voltage can be cal- culated as: Avcesr = ESRA7. (2.141) PROBLEMS 2. 1 . A buck converter has an input voltage of 12 V. The switching frequency is 10 kHz. The load is a resistor of 6 CI. The average load current is 1 A. If the ripple current of the output inductor is limited to 0.1 A and the ripple voltage of the output capacitor is 20 mV. Determine (a) the duty cycle, (b) the filter capacitance, and (c) the output inductance. 2.2. A boost converter has an input voltage of 12 V. The average output voltage is 15 V with a- ripple of lOOmV. It has a resistive load of 3 £1. If the inductor, L, is 1 mH and the output capacitor is 220 n-F. Determine (a) the required switching frequency and (b) the peak-to-peak ripple current in the inductor. Sketch the waveforms for the currents flowing through the inductor and capacitor. Basic Switching Converter Topologies 65 2.3. A buck-boost converter has an input voltage of 9 V and an inductor of lOmH. The magnitude of the average output voltage is 12 V at a switching frequency of 1 kHz. Determine (a) the duty cycle and (b) the magnitude of the ripple inductor current in this converter. 2.4. Derive the critical inductance, L c , in terms of the load resistance, R, duty cycle, D, and switching frequency,/;, that wifrmake the inductor current, in a practical buck converter, discontinuous. Assume that the voltage drop across the switching device is V A and the average inductor current during the on-time is equal to half the peak inductor current. 2.5. A boost converter has a switching frequency of 1 kHz with a duty cycle of 50%. Its maximum ripple current is 4 A and the initial current is 1 A. Determine (a) the average input current, and (b) the average output current. Plot the inductor and output capacitor current waveforms using the passive sign convention. Determine the average charging and discharging currents for the output capacitor. Explain your results. 2.6. The component specifications for a Cuk converter are: L a = 150 p-H, C = 220 |xF, and L, = 200 p-H and C t = 200 m-F. The input voltage is 12 V. It is operating at a switching frequency of 25 kHz with a duty cycle of 25%. The average load current is 3 A. Determine (a) peak-to-peak ripple current in the inductor L } , (b) peak-to-peak ripple current in the inductor L , and (c) the average input current, I s . Plot the current flowing through the energy-transfer capacitor, / Ct (0. f° r a complete switching cycle. Determine the average charging and discharging cur- rents for the energy-transfer capacitor. 2.7. The duty cycle for the two switches, S, and S 2 , of a switching converter shown in Figure 2.33 is 40% with a switching frequency of 10 kHz. Determine (a) the output voltage, V a , and its polarity, and (b) the peak- to-peak ripple current in the input inductor, A/£...-Sketch the current waveform flowing through the inductor £j. 2.8. A buck-boost converter has an input voltage of 9 V, an inductor of 10 mH, an output resistant of 12 ft, and an output capacitance of 200 pF. The magnitude of the average output voltage is 12 V with a 10 mH :12V -W— tis. 1 kJT?,. rir 10 uF 10 mH S E>2 100 pF ±Cz 100 Figure 2.33 Circuit schematic of the switching converter for Problem 2.7. 66 Power-Switching Converters switching frequency of 1 kHz. Determine (a) the duty cycle, (b) the magnitude of the average input current, (c) the peak input current, (d) the peak inductor current, and (e) the capacitor charging current-time product. 2.9. Calculate the efficiency of the buck converter of Figure 2.31 . Find the requirements for high efficiency. 2 10. Find the maximum output voltage that can be obtained with the buck converter of Figure 2.31, when K S =10V, K d =0.7V, i?„ n = i?d = 0.2 XI, ,R S = 1 .2 ft, and R L = 3 ft. 2.1 1 . Consider the ideal buck converter of Figure 2.1. Using PSpice, analyze the effect of an output capacitor with ESR = 10mft, XESL(Q = 0.1 XC(/ S ). Compare your results with the waveforms obtained using ideal components. 2.12. Draw the equivalent circuit for a boost converter including the losses in the transistor, the diode and the inductor; then calculate the duty cycle. 2 13. (a) Calculate the efficiency of a buck converter with K, = 5V, K a =1.2V, F d = 0.3V, and R L = 0.l ft. (b) Repeat (a) replacing the diode with a synchronous rectifier with R on = 3mil. 2.14. (a) Calculate the critical load resistance for the buck converter of Example 2.1. (b) The addition of a synchronous switch, M 2 , in parallel with the diode converts the circuit into a synchronous buck converter. Draw the steady-state waveforms for a load resistance 20% larger than the critical resistance. 2.15. Show that the charging and discharging intervals of the output cap- acitor of a buck converter are both equal to half the switching period. REFERENCES 1 . J. W. Nilsson. Electric Circuits, 3rd ed., Addison-Wesley, Boston, 1990, chap. 5. 2. S. Cuk and R. D. Middlebrook. Advances in Switched-Mode Power Conversion, Vol. 1, TESLAco, Pasadena, 1982, 109 pp. 3. D. M. Mitchell. DC-DC Switching Regulator Analysis, McGraw-Hill, New York, 1988, 13 pp. 4. S. Cuk and R. D. Middlebrook. DC-to-DC Switching Converter, U.S. Patent 4,184,197, January 15, 1980. 5. A. S. Kislovski, R. Redl, and N. O. Sokal. Dynamic Analysis of Switching-Mode DC/DC Converters, Van Nostrand Reinhold, New York, 1991, 177 pp. Basic Switching Converter Topologies °' 6. S. Cuk and R. D. Middlebrook. Advances in Switched-Mode Power Conversion,Vo\. 2, TESLAco, Pasadena, 1982, 31 1 pp. 7. S. Cuk and R. D. Middlebrook, Coupled-inductor and other extensions of a new optimum topology switching dc-to-dc converter, IEEE Industry Applications Society Annual Meeting, Los Angeles, 1977. 8. Vishay Dale Engineering Note, Circuit Simulation of Surface Mount Inductors and Impedance Beads, Document Number 34098, Revision August 27, 2002. 9. J. Prymak. SPICE Models of Capacitors, Vol. 4, No. 5, Kemet Tech. Topics, Kemet Electronics Corp., September 1994. Resonant Converters 3.1 INTRODUCTION The major thrusts in switching converter design are to achieve a higher power packing density and higher conversion efficiency. To increase the power packing density, the switching frequency of the switching converter is often increased to reduce the size and weight of its reactive components. However, the conventional or hard-switching switching converter, employ- ing pulse-width modulation to control the dynamic transfer of electrical energy from the input to the output, suffers an excessive switching loss as its switching frequency approaches 1 MHz. The higher switching losses of the power transistor require a larger heat sink capacity that offsets the net magnetic size reduction when operating at a higher switching frequency. At high switching frequencies, capacitive turn-on losses in power MOSFETs become the predominant switching losses. A power MOSFET with a C ds of 100 pF, switching at 500V, will have a turn-on loss of 0.5C ds f s V ds , or 12.5 W, when operating at 1 MHz. However, the turn-on loss increases to 69 IT 7 Power-Switching Converters 62.5 W when this device operates at a switching frequency of 5 MHz. Resonant converters offer an attractive solution to the above dilemma. There are many topological variations of the resonant converter. Only two of the common resonant converter topologies, the quasi-resonant converter and the load-resonant converter, will be discussed in this chapter. The quasi-resonant converter employs an LC tank circuit to shape the current or voltage waveform of the switching transistor, resulting in a zero-current or zero-voltage condition during device turn-off or turn- on. Zero-current-switching (ZCS) quasi-resonant switches are employed to reduce the turn-off switching losses, while zero-voltage-switching (ZVS) quasi-resonant switches are used to mitigate the turn-on switching losses. In general, ZVS is preferable to ZCS at high switching frequencies. The load-resonant converter can be classified as either a voltage-source series- resonant converter or a current-source parallel-resonant converter. The voltage-source series-resonant converter can be further subdivided into either a series-loaded or parallel-loaded resonant converter. In the series- loaded resonant converter, the load is connected in series with the resonant circuit and the output voltage is obtained from the resonant current. As such, the output voltage is sensitive to load variations. However, the series-loaded resonant converter is inherently overload protected. In the parallel-loaded resonant converter, the load is connected in parallel with the resonant capacitor and the output voltage is obtained from the voltage across this capacitor. Because of this, the output voltage of the parallel-loaded resonant converter is not sensitive to load variations. How- ever, it requires protection against overloading since the output energy is derived directly from the resonant capacitor. One of the major advantages of resonant converters is the absorption of the switching transistor capacitance and other parasitic components into the converter topologies. However, the switching transistors in the resonant converters generally have to carry a higher peak current or voltage for the same output power than their counterparts in conventional switching con- verters. Since resonant converters regulate their output by changing their switching frequencies or by frequency modulation, electromagnetic inter- ference may be unpredictable. The choice of using resonant converters over conventional switching converters should be based on the fact that the reduction in switching losses is greater than the increase in semiconductor device conduction losses associated with the higher peak current or voltage in the resonant topologies. A review of the fundamental concept of parallel and series resonant circuits is done to help with the analysis of some of the simple resonant converter topologies. Resonant Converters '' 3.2 PARALLEL RESONANT CIRCUIT — A REVIEW Consider a current source 7 s O>) connected in parallel with a resistor R, a capacitor C, and an inductor L, as shown in Figure 3.1. As the frequency of the current source changes, the voltage across terminals a and b is given by 7 5 (3.1) v {fo>) (l/R)+j<oC + (yjwL) / m Z0° yJ(\/R 2 ) + («C - (l/wL^Zten- 1 [R(<*C - (1/wL))] The resonant frequency in this circuit is defined as the frequency at which the impedance seen by the current source is purely resistive. This frequency makes the corresponding admittance purely conductive, since Y=Z . The resonant frequency, <a n , is then Q) n C or o)„L ILC At the resonant frequency, the voltage across terminals a and b is V (to = «„) = K mmx = I m R. The capacitor current, 7 c (o> ), during resonance is V a [c I c (w = o»„) = — =jto„CI m R =jI m R^j — (3.2a) (3.2b) (3-3) (3.4) l s U<o) jcoL -L- _L V {ja>) jeaC -T- Figure 3.1 A parallel-resonant circuit. 7 2 Power-Switching Converters while the inductor current, 7i(w n ), is 7 , V I m R _ j£ (3 5) The phasor diagram depicting the currents and voltages at the resonant frequency is shown in Figure 3.2. It can be seen that the capacitive current is of the same magnitude but opposite in sign to the inductive current at resonance. Thus, electrical energy is exchanged between the inductor and the capacitor. 3.3 SERIES RESONANT CIRCUIT — A REVIEW Consider a voltage source K s (» connected in series with a resistor R, an inductor L, and a capacitor C, as shown in Figure 3.3. As the frequency of the voltage source changes, the current flowing in the circuit is given by / = R+j{a,L-(\/{oCJ) V m /0° (36) yjR* + (toL - (l/wQr/tan- 1 I ^ J -A,fljf='t(<»=<°n) Figure 3.2 Phasor diagram showing the inductor and capacitor currents at the resonant frequency. 73 Resonant Converters Ft I P> L V\Ar > rw~w\ V S U<») 1 jaC Figure 3.3 A series-resonant circuit. Again, the resonant frequency in this circuit is defined as the frequency at which the impedance seen by the voltage source is purely resistive. Thus, the resonant frequency, <o n , is also given by a, =— — (3- 7 > At the resonant frequency, the current flowing in the circuit is simply 7, \ 7 ^ m (3.8) The voltage across the inductor, V L (<o ), is V L (o> = o>„) = UvnL)!^ = J ^ V \ (3 ' 9) and the voltage across the capacitor, V£(a> ), is j>. . /max 7^m /^ (3.10) The phasor diagram depicting the voltages and currents of the series reson- ant circuit is shown in Figure 3.4. It can be seen that the voltage across the inductor is equal in amplitude, but opposite in phase, to the voltage across the capacitor. Hence, there is a constant exchange of electrical energy between the capacitor and inductor at resonance. 3.4 CLASSIFICATION OF QUASI-RESONANT SWITCHES The quasi-resonant switch is basically a conventional semiconductor power switching device with an LC tank circuit incorporated into a circuit to shape 74 Power-Switching Converters Figure 3.4 Phasor diagram showing the capacitor and inductor voltages at the resonant frequency. either the voltage across the device or current flowing through it from rectangular pulses into a sinusoidal waveform. The two types of quasi- resonant switches are the current-mode quasi-resonant switch and the volt- age-mode quasi-resonant switch. For the current-mode quasi-resonant switch, the inductor of the resonant tank circuit is connected m series with the switching transistor to shape the current flowing through it. There are two current-mode quasi-resonant switch configurations: the L-type and the M-type, as shown in Figure 3.5 [1]. In both cases, the resonant inductor, L r , is connected in series with the switching transistor, Q s , while the resonant capacitor, C T , is connected in parallel with the switching transistor Q s and the resonant inductor. The resonant inductor and capacitor constitute a series-resonant tank circuit whose resonance occurs during the major portion of the on-time of the switching transistor. The quasi-resonant switch is said to operate in a half- wave mode since the resonant current is not allowed to flow back to the source. If an antiparallel -diode, D u is connected across the switching tran- sistor then the quasi-resonant switch is configured to operate m a full-wave mode and the resonant current can flow bi-directionally to both the load and the source. At turn-on, the switching transistor, Q s , is first driven into saturation before the current flowing through it gradually rises in a quasi-sinusoidal fashion The switching transistor is commutated naturally as the current flowing through it tends to oscillate to a negative value. The effect of the resonant switch on the reduction of switching stress and switching loss is Resonant Converters 75 Til "- Os ■ & ■ — • & O ■ L T C r L-type, half-wave M-type, half wave 4> — i — % * p r -f^T\~V~\ a *> =F C r L-type, full-wave Figure 3.5 Current-mode quasi-resonant switches. M-type, full wave evident from the load-line trajectories shown in Figure 3.6. Path A shows a typical load-line trajectory for inductive switching of a switching transistor with conventional forced turn-ofT. It traverses through a high-stress region where the switching transistor is subjected to both high voltage and high current simultaneously, whereas the load-line trajectory for inductive switch- ing with a current-mode resonant switch is along either the voltage axis or the current axis, as shown by path B in Figure 3.6. Consequently, the switching stresses and losses in the current-mode quasi-resonant switch are greatly reduced. The voltage-mode quasi-resonant switch is implemented by connecting a resonant capacitor, C r , in parallel with the switching transistor, Q s . The strategy in the voltage-mode quasi-resonant switch is to shape the voltage waveform across the switching transistor during its off-time such that a zero- voltage condition is created before the device is allowed to switch on. Voltage-mode quasi-resonant switches are primarily used to reduce capaci- tive turn-on loss in power MOSFETs at very high switching frequencies. Nonzero-voltage turn-on in the power MOSFET switching transistor gen- erates substantial noise that interferes with the controller, and reduces its switching speed due to the switching Miller effect. There are also two voltage-mode quasi-resonant switch configurations: the L-type and the M-type as shown in Figure 3.7 [2]. The voltage-mode quasi-resonant switch is said to operate in a half-wave mode when the voltage across the resonant 76 Power-Switching Converters ON OFF Figure 3.6 Load-line trajectories of a switching transistor: path A, forced switch- ing; path B, resonant switching. C, -U- i 1 — W ' ' © — &- o s Lr L-type, half-wave Hr— T1IT" Os /-, Lr =F C r L-type, full-wave Figure 3.7 Voltage-mode quasi-resonant switches M-type, half-wave t ® M-type, full-wave 77 Resonant Converters capacitor is not allowed to swing to its negative cycle. This is accomplished by a clamping diode, £>,, connected across the resonant capacitor. However, if the diode, D u is connected in series with the switching transistor, then the voltage-mode quasi-resonant switch is said to operate in a full-wave mode since the voltage across the resonant capacitor is allowed to swing freely to negative values. . All the basic switching converter topologies can be converted into quasi-resonant converters simply by replacing the switching transistor with either the current-mode or voltage-mode quasi-resonant switch. They are called quasi-resonant converters because there are resonant and nonreso- nant intervals in the switching waveforms [1,2]. The quasi-resonant switch- ing converter utilizes a voltage-controlled oscillator in its control circuit to change its switching frequency, as shown in Figure 3.8, to maintain a constant output voltage. 3.5 ZERO-CURRENT-SWITCHING QUASI-RESONANT BUCK CONVERTER A ZCS quasi-resonant converter can be easily implemented by replacing the conventional switching transistor with a current-mode quasi-resonant switch. A half-wave ZCS quasi-resonant buck converter with a L-type switch is shown in Figure 3.9(a) and a full-wave ZCS quasi-resonant buck converter with a L-type switch is shown in Figure 3.9(b). The analysis of this ZCS Quasi-resonant converter Voltage-controlled oscillator Error Amplifier ~ Figure 3.8 Control scheme for a quasi-resonant converter. 78 Power-Switching Converters C r=F & D h» T^^fl (a) (b) Figure 3.9 Zero-current-switching (ZCS) quasi-resonant buck converter with: (a) a half-wave, L-type switch and (b) a full-wave, L-type switch. resonant buck converter can be simplified considerably by making the following assumptions [1]. The output inductance, L , is assumed to be much larger than the resonant inductance, L T . The corner frequency of the output filter L - C ,/„ is much lower than the switching frequency. Thus, the output filter L„ - C and J? L can be treated as a constant current sink of /oTThe switching devices are ideal semiconductor switches with no forward drops in their on-state and no leakage currents in their off-state. There are also no time delays at both turn-on and tum-off. The resonant inductor and capacitor are ideal circuit elements with no lossy or parasitic elements. The operation of the ZCS quasi-resonant buck converter can be div- ided into four modes. Suppose that before the switching transistor is switched on, the freewheeling diode, Aw, carries the steady-state output current of /„, and the resonant capacitor voltage, v Cr (f-0), is clamped at zero volt by the freewheeling diode. Also, there is no current flowing through the resonant inductor, i.e., /'^(O) = 0. Mode 1 (0 < t < ft) Mode 1 begins at time t = when the switching transistor, Q s , is switched on. The freewheeling diode, Z> fw , carries the steady-state output current initially, since the resonant capacitor is clamped at zero volt. Hence, both Resonant Converters 79 Aw NO 'o Figure 3.10 Mode 1 equivalent circuit of the ZCS quasi-resonant buck converter. the switching transistor and the freewheeling diode are switched on during mode 1. The mode 1 equivalent circuit is shown in Figure 3.10. The current flowing through the resonant inductor, i L ,U), increases linearly from zero to the steady-state output current of J . The voltage across the resonant in- ductor is related to the rate of rise of its current. At the end of mode 1, the voltage across the resonant inductor, v^i), is given by K s = ^. (3.H) The duration of mode 1, T\, is T,=hk (3.12) Thus, mode 1 is characterized by inductor charging and the storage of electrical energy, in magnetic form, in the resonant inductor. Mode 2 (f, <t<t 2 ) Mode 2 begins when the current flowing through the resonant inductor, i Lr (i), reaches the steady-state output current, /„. The freewheeling diode, Df W , is reverse biased since the resonant capacitor is charged by the differ- ence between the current flowing through the resonant inductor, i Li (i), and the steady-state output current, J a (i.e., i L £t) - J ). The voltage across the resonant capacitor increases in a quasi-sinusoidal fashion. Figure 3.1 1 shows the equivalent circuit for mode 2. The rate of increase of the resonant current is di L , = (Ps-vc r (P) ( 3 13 ) dt L t w 80 Power-Switching Converters Figure 3.11 Mode 2 equivalent circuit of the ZCS quasi-resonant buck converter. The rate of increase of the resonant capacitor voltage is , v c , (fc.(0 ~ 7 q) d -d7 = Q (3-14) The initial resonant capacitor voltage is zero (i.e., v c ,{ti) - v Cf (0) - 0), while the initial resonant inductor current, f^(0), is 7„. The first-order differentia Equations (3.13) and (3.14) can be solved using the two known initial conditions. The expression for the resonant inductor current, i L (fi, is fe,(0 -I + -^r sin w «'' (3-15) where Z„ = -JlJCr is the characteristic impedance and <w„ = 1/ y/L z C t is the resonant frequency of the resonant tank. The expression for the resonant capacitor voltage, v c ,(0> is V Cr (0 = I'sO - COSto„/). (3.16) The current flowing through the resonant inductor is sinusoidal. However, the voltage across the resonant capacitor increases according to a versine function. Thus, mode 2 is also known as the resonant stage. In the half-wave quasi-resonant buck converter, the switching transistor, &. will be naturally commutated at time t a when the resonant inductor current, i Lr (t), reduces to zero as shown in Figure 3.12. In a full-wave quasi-resonant buck converter the resonant inductor current will continue to oscillate and feed energy back to the voltage source, V s , through the antiparallel diode £>,. The current flowing through diode Z>, oscillates to zero again at time f b as shown in Figure 3.13. , _ . . The duration of this resonant mode, T 2 =t 2 - t u can be found by setting i Lr (T£ = 0, Resonant Converters 81 y> vctf Figure 3.12 Waveforms for the half-wave ZCS quasi-resonant buck converter. i Lr (T 2 ) = = h + -^ sin (fti„7- 2 ). Rearranging the above equation, sin(w„r 2 ) = - : V s ' and the duration of mode 2, T 2 , is T 2 = sin-'(-/ Z n /K s )_ a (3-17) (3.18) (3.19) w n For the half-wave mode, a takes on values between -n and 3tt/2. The resonant mode ends at / a when the resonant inductor current reduces to zero. For the full-wave mode, a adopts values between 3-rr/2 and 2tt. 82 Power-Switching Converters %W 2V fi Figure 3.13 Waveforms for the full-wave ZCS quasi-resonant buck converter. The resonant mode terminates at t b after the resonant inductor current feeds energy back to the input voltage source. The resonant capacitor still holds some charge even after the current in the resonant inductor is reduced to zero. As such, the freewheeling diode is kept reverse biased at the end of the resonant mode. The resonant capacitor voltage, v Cr (0> at t = t 2 is v c ,(f2)= ^s(l -cos a). (3.20) The switching transistor is switched off after f a for the half-wave mode. For the full-wave mode, the switching transistor is switched off between f a and f b . Thus, a zero current condition is created for the switching transistor to switch off in order to reduce turn-off switching losses. The steady-state output current, I , must be less than VJZ„ for the switching transistor to switch off during zero current. Resonant Converters 83 Mode3(f 2 <f<fe) Mode 3 begins after the switching transistor switches off at t 2 . The equiva- lent circuit is shown in Figure 3.14. The resonant capacitor, C r , begins to discharge through the output loop and v c ,(0 decreases linearly to zero at time r 3 . Thus, C r d^=-/„. (3.21) The initial resonant capacitor voltage is given by Equation (3.20). At the end of this mode, the voltage across the resonant capacitor, v Cr (/ 3 ), is zero. Using the boundary conditions, Equation (3.21) can be solved for the duration of mode 3, Tj, T 3 = h -t 2 = C / C ^- VC - {t2) = c /' (1 " C °"' ) . (3-22) — h *o The drain-to-source voltage of the switching transistor increases during mode 3. At the end of mode 3 (i.e., at t 3 ), the drain-to-source voltage of the switching transistor is equal to the input voltage, V s , as the switching transistor is completely switched off. Mode4(f 3 <#<T s ) Mode 4 begins when the voltage across the resonant capacitor reduces to zero at time / = f 3 . The freewheeling diode, D fw , switches on and the output current now flows through D fw . The equivalent circuit is shown in Figure 3.15. The duration of mode 4, T 4 , is T 4 = T S -T 3 -T 2 -Ti, (3.23) Figure 3.14 Mode 3 equivalent circuit of the ZCS quasi-resonant buck converter. 84 Power-Switching Converters Figure 3.15 Mode 4 equivalent circuit of the ZCS quasi-resonant buck converter. where T s is the switching period. By controlling the freewheeling time interval, T 4 , the output voltage, V a , can be regulated. The voltage conversion ratio of the full-wave ZCS quasi-resonant buck converter can be found by imposing the constant volt-second relationship on the output inductor, L m since the average voltage across the output inductor is zero under steady-state conditions. Since the resonant capacitor voltage waveform is approximately K s (l - cos io n t) during the interval between t 3 and t u its average value is approximately equal to the input voltage, V s . The resonant period is approximately T n = h - h- During this time interval, the average voltage across the output inductor is (V s - K a ). The voltage across the output inductor during the remaining switching period, i.e., T s - T„, is - V a . From the constant volt-second relationship, (K s - V a )T n - K a (r s - T H ) = 0. (3.24) Rearranging this equation, the voltage conversion ratio, V a /V s , for a full- wave ZCS quasi-resonant buck converter is T s f n (3.25) Thus, the output voltage of a ZCS quasi-resonant buck converter is regu- lated by changing the switching frequency. It is obvious that the switching frequency, / s , must be less than the resonant frequency, /„. In a half-wave ZCS quasi-resonant buck converter, the output voltage is very sensitive to load variations as shown in Figure 3.16 [1]. This is because the only means for the half-wave quasi-resonant buck converter to regulate the output voltage is by varying the switching frequency since it takes a longer time to discharge the tank energy to the load in a light load situation. The voltage conversion ratio of the full-wave ZCS quasi-resonant buck converter is insensitive to load variations. This is because the excess tank Resonant Converters VJV S 85 r=10 15=2 J fjfn Figure 3.1 6 Voltage conversion ratio for the half-wave ZCS quasi-resonant buck converter. (From K.H. Liu, R. Oruganti, and F.C. Lee. Resonant Switches— Topol- ogies and Characteristics, IEEE Power Electronics Specialists Conference liHO, Record: 106, 1985. With permission.) energy in the full-wave ZCS quasi-resonant buck converter is allowed to feed back to the input source during a small output load current requirement. When the required output current is large, the time interval to charge the resonant inductor is longer, and consequently, the resonant inductor is charged to a higher value according to the requirement of the load as shown in Figure 3.17. Since most of the stored magnetic energy in the resonant inductor is used to satisfy the output current requirement, very little excess tank energy is fed back to the input source. Consequently, the magnitude of the resonant inductor current is higher in the first half-cycle during the resonant mode, and is lower during the second half-cycle when the excess energy is fed back to the input source as shown in Figure 3.17(a). Conversely, when the required output current is small, the magnitude of the current flowing through the resonant inductor is small during the resonant mode and is larger during the second half-cycle as shown in Figure 3.17(b). This is because a larger amount Power-Switching Converters (b) Figure 3.17 Resonant inductor current and resonant capacitor voltage for (a) heavy load and (b) light load. (From K.H. Liu, R. Oniganti, and F.C. Lee. Resonant Switches — Topologies and Characteristics, IEEE Power Electronics Specialists Conference 1985, Record: 106, 1985. With permission.) of stored energy is fed back to the input source. Thus, the full-wave ZCS quasi-resonant buck converter is able to regulate its output voltage against load variations without a large change in the switching frequency. Example 3.1. The zero : current-switching quasi-resonant buck converter shown in Figure 3.9(b) has an input voltage of 12 V. The values of the resonant inductor, L T , and resonant capacitor, C r , are 2p,H and 79 nF, respectively. The average output voltage is 9 V across a 9-fl resistor. The output inductor and output capacitor are lOmH and 100 n-F, respectively. Determine (a) the switching frequency,./;, (b) the duration that the resonant Resonant Converters &? inductor is charged, (c) the peak current in the resonant inductor, and (d) the peak voltage across the resonant capacitor. Solution. (a) The resonant frequency is f„=- l ! ! -HVfV-H7 J lit y/LC 2tt yj2 x 10- 6 (79 x 10-») From Equation (3.25), the switching frequency, / s , is /, = y-fn = ^400 kHz = 300 kHz. (b) The average output current is / -2--2-1A /o " R ~ 9 _ ! A " From Equation (3.12), the resonant inductor is charged for j^o = 2x 10-0(1) 1 V s 12 (c) From Equation (3.15), the peak current in the resonant inductor is V 12 /, -/„+ — -!+ , - =3 3S5A. (d) From Equation (3.16), the expression for the voltage across the resonant capacitor is Vc, = V s \ 1 - cos J_J = 12[1 - cos(2.516 x 10 6 f)] The peak voltage across the resonant capacitor is V Cijim = 12(1 + 1) = 24 V. 3.6 ZERO-CURRENT-SWITCHING QUASI-RESONANT BOOST CONVERTER The circuit schematic of a full-wave, ZCS quasi-resonant boost converter is shown in Figure 3.18. The analysis of this converter can be simplified by T 88 Power-Switching Converters i C a Figure 3.18 Circuit schematic of a full-wave ZCS quasi-resonant boost con- verter. adopting the same assumptions made in Section 3.5. Furthermore, the input of the boost converter is treated as a constant-current source, / s , supplying power to a constant-voltage load, K a . The operation of the ZCS quasi-resonant boost converter can also be divided into four modes. Suppose before the switching transistor Q s , is switched on, the freewheeling diode is conducting, and consequently, the resonant capacitor is charged to the output voltage, V a . Model (0< t<U) Mode 1 begins when the switching transistor, Q s , is switched on at t = The equivalent circuit is shown in Figure 3.19. The current flowing through the resonant inductor, i Lt (t), increases linearly from zero to the steady-state input current / s . The voltage across the resonant inductor is related to the rate of rise of its current. At the end of mode 1, the voltage across the resonant inductor, v Lt (t), is given by Figure 3.19 Mode 1 equivalent circuit of the ZCS quasi-resonant boost con- verter. Resonant Converters V - L — 'a — j -t ,r, - J 1 The duration of mode 1, T\, is Ms 59 (3.26) (3.27) Thus, mode 1 is characterized by the storage of electrical energy in the resonant inductor in magnetic form. Mode 2 (U <t<t 2 ) Mode 2 begins when the current flowing through the resonant inductor reaches the input current, J s . The freewheeling diode is reverse biased as the resonant capacitor discharges its stored energy into the resonant in- ductor. The equivalent circuit is shown in Figure 3.20. The voltage across the resonant capacitor, v Cr (/), decreases sinusoidally according to Q — ^ — = h — '£,(')- The rate of increase of the resonant inductor .current, (di Li {t)ldi), is di L ,(0 v c ,(/) d? L t (3.28) (3.29) The above first-order differential equations can be solved using the two known initial conditions: i ir (r,) = i ir (0) = / s and vc t (/,) = v Ct (0)= V a . The expression for the resonant inductor current, 4±;(t), is iL,(t) = h+-^- sin (w„0 (3.30) Figure 3.20 Mode 2 equivalent circuit of the ZCSquasi-resonant boost converter. 90 Power-Switching Converters where Z n = y /LjC I is the circuit characteristic impedance and to„ = 1/v/i^Cr is the resonant frequency. The expression for the resonant capacitor voltage, v c ,(A is vc r (0= V a cos(w„t). (3.31) Thus, both the current flowing through the resonant inductor and the voltage across the resonant capacitor are sinusoidal. Hence, electrical energy is exchanged between the resonant inductor and capacitor. Mode 2 is also known as the resonanl^ode. The resonant inductor current continues to swing to its negative cycle when it feeds energy back to the input source as shown in Figure 3.21. At the beginning of this mode, the resonant capacitor discharges its energy to the resonant inductor. However, as the resonant inductor current decreases below the steady-state input current, / s , the resonant capacitor voltage increases toward the output voltage, V a . The duration of this resonant mode, T 2 = t 2 -h, can be found by setting iX r (72) = 0: Figure 3.21 Waveforms for the full-wave ZCS quasi-resonant boost converter. Resonant Converters iL,{T 2 ) = = / s + -^ sin (w„T 2 ). The duration for mode 2, T 2 , is T 2 = sin (-(Z„/ S /F a ))_ a 91 (3.32) (3.33) where a takes on values between 1.5tt and 2-tr. The resonant mode termin- ates at r 2 = t b after the resonant inductor has completely fed its stored energy back to the input source. After t a , the switching transistor, Q s , can now be switched off. Thus, a zero-current condition is created for the switching transistor to switch off. The input current, I s , should be smaller than VJZ n for the switching transistor to switch off during zero current. Mode3(f 2 <f< f 3 ) Mode 3 begins after the resonant inductor current decreases to zero from its negative peak at time t 2 . The switching transistor, Q s , switches off and its drain-to-source voltage continues to rise during this interval. The equivalent circuit is shown in Figure 3.22. The resonant capacitor continues to charge towards the output voltage, V a , by the input current, / s . The rate of increase of the capacitor voltage is ,v Cr (0 / s d_ dT = Q- The initial resonant capacitor voltage is vcv('2)= F a cos(a). (3.34) (3.35) Figure 3.22 Mode 3 equivalent circuit of the ZCS quasi-resonant boost con- verter. 92 The duration of mode 3, T 3 , is _ C r K a (l-cos«) r 3 = - • Power-Switching Converters (3.36) Mode 4 (f 3 < t < T s ) Mode 4 begins when the resonant capacitor voltage reaches V a at r 3 . The freewheeling diode, £> fw , is forward biased and switched on. The equivalent circuit is shown in Figure 3.23. The duration of mode 4 is r 4 T, - T 2 - T 3 , (3.37) where T s is the switching period. The voltage conversion ratio of the full-wave ZCS quasi-resonant boost converter can be found by imposing the constant volt-second relation- ship on the input inductor, L„ since the average voltage across it is zero for steady-state operation. The average voltage across the input inductor during the time interval between /, and t 3 (i.e., the resonant period T„) is V s since the average V c is zero. During the remaining time interval (i.e., T s - T„), the average voltage across the input inductor is (K s — V a ). Thus, V i T n + (T s -T n )(V s -V 3 ) = 0. (3.38) The voltage conversion ratio for the full-wave ZCS quasi-resonant boost converter is 1 V s (!-(/,//»))' (3.39) Figure 3.23 Mode 4 equivalent circuit of the ZCS quasi-resonant boost con- verter. Resonant Converters 93 Note that this voltage conversion ratio is similar to that of the conventional boost switching converter if the ratio of the switching frequency to the resonant frequency is replaced by its duty cycle, D. The voltage conversion ratio versus fjf„ relationship for a full-wave ZCS quasi-resonant boost converter is shown in Figure 3.24. It should be noted that the switching frequency, / s , must be smaller than the resonant frequency. In a half-wave ZCS quasi-resonant boost converter, the output voltage is very sensitive to load variations. Thus, the only means to regulate its output voltage is to change the switching frequency. On the other hand, the full-wave ZCS quasi- resonant boost converter is able to regulate its output voltage against load variation without a large change in switching frequency. Example 3.2. The zero-current-switching quasi-resonant boost converter shown in Figure 3.18 has an input voltage of 12 V. The values of the resonant inductor, L T , and resonant capacitor, C r , are 2jiH arid 79 nF, respectively. The output voltage is 15 V across a 10-11 resistor. The output inductor and output capacitor are lOmH and 100 p.F, respectively. Determine (a) the switching frequency, f s , (b) the duration that the resonant inductor is charged, (c) the peak current in the resonant inductor, and (d) the peak voltage across the resonant capacitor. VJV S 5 r fjfn 0.6 0.8 02 0.4 Figure 3.24 Voltage conversion ratio versus fjf„ for a full-wave ZCS quasi- resonant boost converter. g 4 Power-Switching Converters Solution. (a) From Equation (3.39), the switching frequency, / s , is /s = (l -£)/„= (l -^)400kHz = 80kHz. (b) The average output .current is /o -"^-io- 15A - Assuming a lossless converter, the input current, / s , is 2Vo = i5(^) = 1875A V s 12 From Equation (3.27), the duration that the resonant inductor is charged is „ L T I S 2xl0-'(1.875) = 025 ^ "~ K. " 15 (c) From Equation (3.30), the peak current in the resonant inductor is t j i v " i :7.t i . 15 - A °* A 7z -" max _ Ys + Z„ ~ 7(2 x 10- 6 /79 x 10~ y ) (d) From Equation (3.31), the peak voltage across the resonant cap- acitor is Kc r , m „ = V. = 15V. 3.7 ZERO-VOLTAGE-SWITCHING QUASI-RESONANT BUCK CONVERTER The circuit schematic of a full-wave ZVS quasi-resonant buck converter is shown in Figure 3.25. The analysis of this converter can be simplified by using the same assumptions made for the ZCS quasi-resonant buck converter. The operation of the ZVS quasi-resonant buck converter can be divided into four modes. Suppose that before the switching transistor, Q s , is switched off, the resonant inductor, L T , carries the load current, I„. The resonant capacitor, C r , is clamped at zero volt and the freewheeling diode, £> fw , is switched off. Resonant Converters 95 Figure 3.25 Circuit schematic of a full-wave ZVS quasi-resonant buck con- verter. Model (0<f<f 1 ) Mode 1 begins when the switching transistor is switched off at time / = 0. The equivalent circuit is shown in Figure 3.26. The resonant capacitor begins its charging process as soon as the switching transistor is switched off. At the end of mode 1, the current flowing through the resonant capacitor is I - C — The duration of mode 1, T x , is T t c t v s (3.40) (3.41) Thus, mode 1 is characterized by the capacitor charging and the storage of electrical energy in electrostaticTorm in the resonant capacitor. It should be noted that both the switching transistor and the freewheeling diode remain off during mode 1. 6' <*5 Diw © Figure 3.26 Mode 1 equivalent circuit of the full-wave ZVS quasi-resonant buck converter. 96 Power-Switching Converters Mode2(*,<f<f 2 ) Mode 2 begins when the voltage across the resonant capacitor reaches the input supply voltage, V s , at time t x . The freewheeling diode, Aw, is switched on and the current flowing in the resonant inductor decreases in a sinusoidal fashion. Figure 3.27 shows the equivalent circuit for mode 2. The rate of decrease of the resonant inductor current is Ait, _ v vc,(0 ~dT s C r • The rate of increase of the resonant capacitor voltage is dvc = iir(0 d* (3.42) (3-43) The initial resonant inductor current, i^h), is I , while the initial resonant capacitor voltage, v Cr (fi), is V s . The above first-order differential equations can be solved using the two known initial conditions. The expression for the resonant inductor current, i£ r (f)> is »£,(*) = Jo cos to„t t 3 - 44 ) and the resonant capacitor voltage, v Cl (0> is vc r (0 = V s + Z„I sin u>„t, where Z„ = y/TJei is the circuit characteristic impedance and u>„ = \/Vt~C r is the resonant frequency. Mode 2 is also known as th& resonant mode. The voltage across the resonant capacitor continues to swing to its negative cycle as it feeds energy back to the input source as shown in Figure 3.28. The current flowing through the resonant inductor decreases to its minimum value as the voltage across the resonant capacitor (3.45) Figure 3.27 Mode 2 equivalent circuit of the full-wave ZVS quasi-resonant buck converter. Resonant Converters 97 Figure 3.28 Waveforms of the full-wave ZVS quasi-resonant buck converter. is again at V s . After this, the current in the resonant inductor increases toward J . The duration of this resonant mode, T 2 =t 2 -t x , can be found by setting v c , (T 2 ) = 0: vc,(T 2 ) = V s + Z„I sin (o>„r 2 ) = 0. Thus, the duration of mode 2, T 2 , is T 2 = sin"' ( - (K s /Z„/ )) _ a (3.46) (3-47) where a takes on values between l.5ir and 2tt. The resonant mode termin- ates at t 2 , after the resonant capacitor has completely fed its stored energy back to the input source. The switching transistor should be switched on during the negative part of the resonant capacitor voltage. Otherwise, the resonant capacitor will begin to recharge and the switching transistor will lose the opportunity to switch on under zero-voltage condition. It should be noted that the steady-state load current, I oy must be greater than (VJZ ) for the switching transistor to switch on at zero voltage. 98 Power-Switching Converters Mode3(f 2 < t<t 3 ) Mode 3 begins after the resonant capacitor voltage decreases to zero from its negative peak at time t 2 . The equivalent circuit is shown in Figure 3.29. The resonant inductor current continues to increase toward the steady-state output current, /„. The rate of increase of the resonant inductor current is .^ = n (3.48) dr L r ' The current flowing through the resonant inductor at the beginning of this mode is U,(r3) = /oCOS(cr). < 3 - 49 > The duration of mode 3, T 3 , is r3= ^ ( l_ CO sa). (3- 5 °) Mode4(f 3 < t<T s ) Mode 4 begins when the current in the resonant inductor reaches the steady- state output current, / 0) at time t 3 . The freewheeling diode is switched off at time r 3 . The equivalent circuit is shown in Figure 3.30. The duration of this mode is t a = r s - r, - t 2 - r 3 , (3.51) where T s is the switching period. The voltage conversion ratio of the full-wave ZVS quasi-resonant buck converter can be solved by imposing the constant volt-second relationship on the output inductor, L . The average voltage across the output inductor 6* Qs -o o- t-r ©/o Figure 3.29 Mode 3 equivalent circuit of the full-wave ZVS quasi-resonant buck converter. Resonant Converters ^9 Figure 3.30 Mode 4 equivalent circuit of the full-wave ZVS quasi-resonant buck converter. during the time interval between t x and t 3 , or T„ = t 3 - t t is — V a . During the remaining time interval (i.e., T s - T„), the average voltage across the output inductor is approximately ( V s — K a ). Thus -V a T„ + (V s - K a )(r 5 - T n ) = 0. (3.52) The voltage conversion ratio of the full-wave ZVS quasi-resonant buck converter is V S V fn) (3.53) A plot of the voltage conversion ratio versus/s// n is shown in Figure 3.31. As can be seen, it is very insensitive to any load variations. Note that the voltage conversion ratio of the ZVS resonant buck converter is quite different from that of the ZCS quasi-resonant buck converter and the conventional buck converter. Since the resonant mode occurs during the off-time of the switch- ing transistor, it is expected that the voltage conversion ratio is related to this period. As in the previous two ZCS quasi-resonant converters, the switching frequency of the ZVS quasi-resonant converter must be less than its resonant frequency. The voltage conversion ratio of the half-wave ZVS quasi- resonant buck converter is also very sensitive to load variations. Thus, the half-wave ZVS quasi-resonant buck converter requires a larger change in switching frequency to regulate its output voltage compared to the full-wave, ZVS, quasi-resonant buck converter. Example 33. The ZVS quasi-resonant buck converter shown in Figure 3.25 has an input voltage of 12 V and a resistive load of 2ft. The values of the resonant inductor, L T , and resonant capacitor, C r , are 2 p,H and 79 nF, respectively. The switching frequency is 200 kHz. The output inductor and output capacitor are lOmH and IOOjjlF, respectively. Determine (a) the average output voltage, V a , (b) the duration that the resonant capacitor is Power-Switching Converters Figure 3.31 Voltage conversion ratio versus fjf„ for the full-wave ZVS quasi- resonant buck converter. charged, (c) the peak voltage across the resonant capacitor, and (d) the expression for the resonant inductor current. Solution. (a) From Equation (3.53), the average output voltage is (b) The average output current is /o ~ R-2~ 3A - From Equation (3.41), the duration that the resonant capacitor is charged is C^ = 79 x 10-9(12) = 0316 ' /o 3 (c) From Equation (3.45), the peak voltage across the resonant cap- acitor is V a [Li ,„ 6 / 2 x 10- 6 F Cr ,max=K s + Z n / =K s+ ^^=12 + - ) / wlrl ^ = 27.1V. Resonant Converters 101 (d) From Equation (3.44), the expression for the resonant inductor current is k, = /ocos(o)„0 = 3cosf-/=L=) = 3 cos (2.51 6 x 10 6 )/ A. 3.8 ZERO-VOLTAGE-SWITCHING QUASI-RESONANT BOOST CONVERTER The circuit schematic of a full-wave ZVS quasi-resonant boost converter is shown in Figure 3.32. The same assumptions made for the ZCS quasi- resonant boost converter are valid here. Suppose that before the switching transistor, Q s , is switched off, it carries the input current, l s . Also, the freewheeling diode, Z> fw , is switched off. Model (0< t<U) Mode 1 begins when the switching transistor, Q s , is switched off at t = 0. The resonant capacitor, C r , is charged up and its voltage increases according to C r d— = /,. The duration of mode 1, T u is T X = C T ^. (3.54) (3.55) Thus, mode 1 is characterized byJhe charging of the resonant capacitor and the storage of energy in electrostatic form. Both the switching transistor and the freewheeling diode are switched off during mode 1 as shown by the equivalent circuit shown in Figure 3.33. Figure 3.32 Circuit schematic of- a full-wave ZVS quasi-resonant boost con- verter. 102 Power-Switching Converters ©< _rW"V"» o o- Os ic, 6 Figure 3.33 Mode ] equivalent circuit of the full-wave ZVS quasi-resonant boost converter. Mode 2{U<t< t 2 ) Mode 2 commences when the voltage across the resonant capacitor reaches the steady-state output voltage, V a . The freewheeling diode, £> rw , is forward- biased and switched on. Current starts to flow through the resonant in- ductor. The equivalent circuit is shown in Figure 3.34. The rate of increase of the resonant inductor current, i ir (r), is d iL,_ vc,(i)-V a df Lr (3.56) The voltage across the resonant capacitor continues to increase beyond the steady-state output voltage, V a , according to Q^ = / s -UO. (3.57) The expressions for the resonant inductor current, i Lt (t), and resonant cap- acitor voltage, v c (i), can be found by using the initial conditions ii^rO = Figure 3.34 Mode 2 equivalent circuit of the full-wave ZVS quasi-resonant boost converter. Resonant Converters and v Cr (f i) = V*- The resonant inductor current, i Lr (t), is i Li (i) = / s (l - cos &>„0, while the resonant capacitor voltage, v c (i), is vcr(') = v a + / S Z„ sin « n r, 703 (3.58) (3.59) where Z„ and «„ are the circuit characteristic impedance and resonant frequency, respectively, as defined previously. Mode 2 is also known as the resonant mode. The resonant capacitor voltage continues to swing to the negative cycle as it feeds energy back to the input source as shown in Figure 3.35. The duration of the resonant mode, T 2 = t 2 -t t , can be found by setting vc r (T 2 ) = 0: vc r (T 2 ) =V a + I % Z n sin (o>„r 2 ) = 0. The duration of mode 2, T 2 , is sin-'(-(K a // s Z n )) a (3.60) (3.61) *■ t Figure 3.35 Waveforms of the full-wave ZCS quasi-resonant boost converter. W" 104 Power-Switching Converters where a takes on values of 1 .5-n- and 2ir. The resonant mode terminates after all the stored energy in the resonant capacitor has been fed back to the input source. The switching transistor, Q s , should be switched on during the negative resonant capacitor voltage cycle. Otherwise, the resonant capacitor will begin to recharge and the switching transistor will miss the opportunity to switch on at the zero-voltage condition. It should be noted that the input current, / s , must be greater than VJZ n for the switching transistor to switch on at zero voltage. Mode3(f 2 < t<t 3 ) Mode 3 begins after the resonant capacitor voltage decreases to zero frcan its negative peak at time t 2 . The equivalent circuit is shown in Figure 3.36. Both the switching transistor, Q s and the freewheeling diode, X> fw , are switched on during this mode. The resonant inductor current continues to decrease according to Z, r d£=-K, The initial resonant inductor current is iL,(t2) = W -cos a]. The duration of mode 3, T 3 = t 3 — t 2 , is L T I s [i —cos a] (3.62) (3.63) (3.64) Figure 3.36 Mode 3 equivalent circuit of the full-wave ZVS quasi-resonant boost converter. Resonant Converters 105 Mode4(f 3 < #< T s ) Mode 4 begins when the resonant inductor current decreases to zero at time r 3 . The freewheeling diode, Aw, is now reverse biased and switched off at time t 3 . The equivalent circuit is shown in Figure 3.37. The duration of this mode is T % -Ti-T 2 - 7a, (3.65) where T s is the switching period. The voltage conversion ratio of the full-wave ZVS quasi-resonant boost converter can be found by imposing the constant volt-second relation- ship on the input inductor, L v The average voltage across the input inductor during the time interval between t x and r 3 (i.e., T„ = t 3 — f i) is {V s — K a ). During the remaining time interval (i.e., T s - 7*„), the average voltage across the input inductor is V s . Thus, (V, - V a )T n + V S (T S - T n ) = 0. (3.66) The voltage conversion ratio of the full-wave ZVS quasi-resonant boost converter is (3.67) A plot of the voltage conversion ratio versus fjf n of a full-wave ZVS quasi- resonant boost converter is shown in Figure 3.38. As shown, the voltage conversion ratio is inversely proportional to \hzfjf„ ratio. A lower switching frequency in the ZVS quasi-resonant boost converter yields a higher aver- age output voltage. Note that the voltage conversion ratio of the ZVS quasi-resonant boost converter is quite different from that of the ZCS Figure 3.37 Mode 4 equivalent circuit of the full-wavaZVS quasi-resonant boost converter. 106 Power-Switching Converters VJV S l I L j. _i^r~-=- — l f S /fn 0.2 0.4 0.6 0.8 Figure 3.38 Voltage conversion ratio versus fjf„ for the full-wave ZVS quasi- resonant boost converter. quasi-resonant boost converter, as well as the conventional boost converter. As in all other quasi-resonant converters, the switching frequency of the ZVS quasi-resonant boost converter must be less than its resonant frequency, /„. The voltage conversion ratio of the half-wave ZVS quasi-resonant boost converter is very sensitive to load variations for the same reasons previously mentioned. Example 3.4. The ZVS quasi-resonant boost converter shown in Figure 3.32 has an input voltage of 12V. The output voltage is 24V across a resistive load of 6 ft. The values of the resonant inductor, L T , and resonant capacitor, C r , are 2 w.H and 79 nF, respectively. Determine (a) the switching frequency,/ s , (b) the duration that the resonant capacitor is charged, (c) the peak resonant inductor current, and (d) the peak voltage across the resonant capacitor. Solution. (a) The resonant frequency,/,, is 400kHz. From Equation (3.67), the switching frequency, f s , is f s = Y±f n = — 400 kHz = 200 kHz. Js V* 24 Resonant Converters *®' (b) From Ohm's law, the average output current is Assuming a lossless converter, the average input current is 2V, = 24^ =8A V s 12 From Equation (3.55), the resonant capacitor is charged for V „ 24 T, = C,-^ = (79 x 10- 9 )— = 237ns. (c) From Equation (3.58), the peak current in the resonant inductor is /^max = /stl -("!)] = 8(2) = 16A- (d) From Equation (3.59), the peak voltage across the resonant cap- acitor is Vc., m = V a + I S Z„ = 24 + 8^g = 64.25 V. 3.9 SERIES-LOADED RESONANT CONVERTER [3] The circuit schematic of a half-bridge series-loaded resonant converter is shown in Figure 3.39. As the name implies, both, the resonant inductor, L r , and the resonant capacitor, C r , are connected in series with the output load via a full-wave rectification circuit. The series-loaded resonant converter topology has an important advantage over the parallel-loaded resonant converter in high-voltage applications since it does not require an output V R /2 4=5 V-/2 ±Ci jHM° 1 /». r& c, -HH d, in '■ B D, SO; %a Figufe 3.39 Circuit schematic of a half-bridge series-loaded resonant converter. 705 Power-Switching Converters inductor. For a very large output filter capacitor, the rectification circuit and the load can be represented as a constant output voltage source of V . In the steady-state symmetrical operation, the switching transistors, Q\ and Q 2 , conduct for less than each half cycle of a switching period. Similarly, the two antiparallel diodes, D x and D 2 , conduct during apportion of each half cycle of a switching period. Thus, it is sufficient to analyze only one-half cycle of the operation in this resonant converter. The input voltage, V s , is divided equally between the two symmetrical input capacitors that serve as the input sources during each half of the switching cycle. As such, the one-half equivalent circuit, neglecting all parasitic resistances, can be represented as shown in Figure 3.40. This is essentially an undamped series-resonant circuit. In the steady- state, the operation of the half-bridge series-loaded resonant converter can be classified as either the discontinuous mode or the continuous mode. There are two continuous modes of operation, depending on the switching frequency. 3.9.1 Discontinuous Mode (0 < f< 0.5f„) In the discontinuous mode of operation, the energy in the resonant inductor is consumed before the second switching transistor is switched on m the second-half of a switching cycle. There are six stages of operation in one switching cycle. Suppose before the beginning of a switching cycle, the voltage across the resonant capacitor, v Cr (0), is charged to (K„ - 0.5 K s ) and the current flowing through the resonant inductor, i L , (0), is zero. Stage 1 (0 < / < *0 begins when the switching transistor g, is switched on at tune t = 0. The current in the resonant inductor begins to increase sinusoidally as the resonant capacitor voltage increases from itSFinitial value of (V - 0.5 K s ) toward a positive value. It should be noted that V < 0.5 V s . The equivalent circuit for stage 1 is shown in Figure 3.41(a). WO Vs/2 — II— VcM « B 6 ±v a < i c Figure 3.40 Equivalent circuit for the half-bridge series-loaded resonant con- verter. Resonant Converters O n A L. C. 109 (b)stage2(f 1 <f=st ! ) (c)stage4(^</sg (d)stage5(f 4 <fs t 5 ) Figure 3.41 Discontinuous-mode equivalent circuits for the half-bridge series- loaded resonant converter. The rate of rise of the resonant inductor current is related to the voltage across its terminals according to dfr.(Q ((P./2) - K - v Q (P) At Lr while the rate of rise of the resonant capacitor voltage is . v Cr (0 MO dr a (3.68) (3.69) Thus, the series-loaded resonant converter acts as a step-down converter without an output transformer. The current flowing through the resonant inductor, iz. r (0. ' s W0 = Z^ sin („„,), (3-70) and the voltage across the resonant capacitor, v Cr (t), is v Cr (0 = Y± - V - (K, - 2K )cos {w„t), (3-71) where <o„ = 1/VZ^Q is the resonant frequency and Z„ = y/L r /C T is the characteristic impedance. Stage 1 ends at time f, when the current flowing j JO Power-Switching Converters through the resonant inductor decreases to zero and the voltage across the resonant capacitor reaches its peak value of (3K s /2) - 3K . Hence, the switching transistor commutates naturally and switches off at both zero current and zero voltage. Stage 2 (f i < / :£ t 2 ) begins when the antiparallel diode, D u is forward- biased at U as the direction of the resonant inductor current reverses. The voltage across the resonant capacitor decreases as it discharges its stored energy to the upper input source via the antiparallel diode, />,. The equiva- lent circuit is shown in Figure 3.41(b). The polarity of the voltage across terminals B and C (i.e., v BC ) is reversed since the current now flows through the rectifiers D 4 and D 5 . Stage 2 ends when the current in the resonant inductor decreases to zero again and the voltage across the resonant capaci- tor reaches a value of 0.5 V s - V . Thus, the antiparallel diode, D,, switches on and off at zero current. During stage 3 (t 2 < t < tj), all the switching devices remain off. The resonant capacitor voltage remains at 0.5 V s - V since there is no discharge path. This completes the first half-cycle of operation. Stage 4 (f 3 < t < U) begins when the lower switching transistor, Q 2 , switches on at time t 3 . The polarity of the source voltage reverses since it is connected through the lower switching transistor, Q 2 . Both the resonant inductor current and the resonant capacitor voltage begin to decrease to- ward their negative peaks. The equivalent circuit during stage 4 is shown in Figure 3.41(c). Stage 4 ends when the current in the resonant inductor reaches zero from its negative value. The switching transistor, Q 2 , commu- tates naturally. At the same time, the antiparallel diode, D 2 , switches on as it is forward-biased, thus feeding the stored energy in the resonant tank back to the lower input source during stage 5(( 4 <»s * s ). v BC reverses its polarity as the output current flows through the rectifiers D 3 and D 6 . Stage 6(; 5 <is T) is characterized by zero current in the resonant inductor and a constant voltage of V„ - 0.5 V s across the resonant capacitor. This completes the switching cycle. The switching waveforms for the half-bridge series-loaded resonant converter are shown in Figure 3.42. Since the switching transistors switch off at both zero current and zero voltage in the discontinuous mode of operation, it is feasible to use conventional silicon-controlled rectifiers without the need for commutation circuits in high-power, low-frequency applications. 3.9.2 Continuous Mode (f s > /„ or Above-Resonant Mode) There are six stages of operation in the above-resonant continuous mode of operation. Figure 3.43 shows the first three stages during the first-half cycle of operation. Suppose before the beginning of a switching cycle, the voltage across the resonant capacitor is at some negative value, while the resonant Resonant Converters 111 stage: Figure 3.42 Switching waveforms for the discontinuous-mode half-bridge series- loaded resonant converter. inductor current is at some positive value. Stage 1 (0 < t =£ t ,) begins when the switching transistor, Q u switches on at ( = ft The rate of rise of the resonant inductor current is related to the voltage across its terminals according to JlAO _ ((F 5 /2)-K o -v Cr (0) d_ dT~ L r ' while the rate of rise of the resonant capacitor voltage is dv Cr (0 = iuiO dt C T ' The above two equations can be solved using the initial conditions i Lt (0) (for iz., (0) > 0) and v Cr (0) (for v c , (0) < 0). The resonant inductor current, i Lr (t), is (3.72) (3.73) M0 ((F 5 /2)-F o -v Cr (0)) sin (tj„t) + ii. r (Q) cos (to„t), (3.74) 112 O, A L, C, -o o ^Y^ 11_ =k Vs/2 U0 (a) stage 1 (0<»sf,) Power-Switching Converters . D 2 a l, c. 'JO 5kz v B ^ vya 1 I- (b)stage2((, <(sy I D, C, ;t Vs/2 UO ^- V„ X (c)stage3(t,<f^y Figure 3.43 Continuous-mode (f 5 > f n ) equivalent circuits for the half-bridge series-loaded resonant converter. and the voltage across the resonant capacitor, v Ct (t), is Cr(0 = (-y - v °) -(^2~ V °- Vc - (0) ) cos(ft, " r) vcA + i L ,(0) z n sin (&>„/)• (3.75) It is noted that the peak of the resonant inductor current occurs when the resonant capacitor voltage is equal to (0.5 V s — V ). Stage 2 (*i < / £ t 2 ) begins when the switching transistor g, is forced to switch off at time f,. Since the resonant inductor current cannot be interrupted, the antiparallel diode, D 2 , starts to conduct as it is forward-biased and the resonant inductor current continues to flow through the path along Z> 3 , the output V a , D 6 , the bottom input source 0.5 V 2 , and D 2 . The resonant capacitor voltage con- tinues to increase according to v Ct (r) = - ( y + V j + Hj + V + v c ,{t0) cos («„0 + ijL,{ti)Z„ sin (w„t\ (3.76) and the resonant inductor current decreases according to . l{{) = _ ((n/2) + K o + v Cr (r,)) sin((i)n0 + f£r(fl)cos(Wn0 . (3.77) Resonant Converters 113 Stage : Figure 3.44 Switching waveforms for the above-resonant continuous-mode half- bridge series-loaded resonant converter. Stage 2 ends when the resonant inductor current decreases to zero at time t 2 . The resonant capacitor voltage is now at its positive peak value. Stage 3 (t 2 < t £ r 3 ) begins when the resonant inductor current decreases to zero at time t 2 . The antiparallel diode, Z>,, is forward-biased and feeds energy back to the upper voltage source. Stage 3 ends when the switching transistor, Q 2 , switches on at time t 3 . This completes the first half-cycle of operation. The switching waveforms of this continuous mode of operation are shown in Figure-3.44. The combined conduction interval for the positive resonant inductor current is less than 180° of the resonant frequency, thus resulting in f s >f n or T S <T„. 3.9.3 Continuous Mode (0.5f„ <f<f„ or Below-Resonant Mode) The below-resonant continuous mode has four stages of operation in one switching cycle. Suppose before the start of a switching cycle, the inductor current is positive while the voltage across the resonant capacitor is negative. The switching waveforms and equivalent circuits are shown in Figure 3.45 and Figure 3.46, respectively. Stage 1 (0 < t < r,) begins when the switching transistor, Q x , switches on at t = 0. The resonant inductor current increases and reaches its peak amplitude when the resonant capacitor voltage reaches (0.5 V s - V„). The switching transistor remains conducting until it is natur- ally commutated when the resonant inductor current reduces to zero. Stage 2 (f, <-t < t 2 ) begins as the antiparallel diode, D x , conducts. The resonant 114 Power-Switching Converters *■ t Stage : Figure 3.45 Switching waveforms for the below-resonant continuous-mode half- bridge series-loaded resonant converter. Qi A L, _o o r-v>-> C, Z±Z Vg/2 ili.fi 1 ] -o o <~*-v^ c Hl- C 'L r (0 .1 I 1 (a) -o— — o rw~v C, 1 Vg/2 >l,(0 C X I I (b) 2 A L, _o o rv-v-v U» -±r Vsf2 1 5, (c) (d) Figure 3.46 Equivalent circuits for the below-resonant continuous-mode half- bridge series-loaded resonant converter. inductor current reverses its direction as it feeds energy back to the upper input source. At the same time, v BC reverses its polarity as the output current flows through D A and D 5 . Stage 3 (t 2 < / ^ h) commences as the switching transistor, Q 2 , switches on at time t 2 and remains conducting until it is Resonant Converters 115 Ufn Figure 3.47 Steady-state output characteristics of a half-bridge series-loaded resonant converter: (A) discontinuous mode, (B) below-resonant continuous mode, and (C) above-resonant continuous mode. naturally commutated at time f 3 . Stage 4(( 3 <l£J) begins as the resonant inductor current continues to flow through Z> 2 . The next cycle starts when the switching transistor, Q u switches on again. Figure 3.47 shows the steady-state normalized output current I ' versus fjf„ characteristics of the series-loaded resonant converter. As shown, the discontinuous mode requires a larger change in switching frequency to main- tain a constant output voltage, V ', as the load current changes. As such, the discontinuous mode of operation is to be avoided for a large load swing. The output voltage remains fairly constant in the two continuous modes of operation. In the above-resonant mode, the switching frequency must de- crease to increase the output voltage or current, while the switching frequency in the below-resonant mode must be increased to increase the output voltage or current. However, the continuous mode is the preferred mode of operation since it requires a smaller frequency range to regulate the output voltage. Example 3.5. The series-loaded resonant converter shown in Figure 3.39 has the following parameters for its components: C r =0.1 u.F, L r = 100 u.H, C f =1000n-F, and C o = 2000n,F. The input source, V s , is 24 V and the output voltage, V , is 5 V. The switching frequency is 20 kHz. Identify the mode of operation for this series-loaded resonant converter. Determine 116 Power-Switching Converters (a) the peak amplitude of the resonant inductor current and (b) the peak value of the resonant capacitor voltage. Solution. The resonant frequency,/,, is /» = 1 liry/LfCy 50.3 kHz. Since f s = 20 kHz is less than /„/2 = 25.15kHz, the series-loaded resonant converter is operating in the discontinuous mode of operation. (a) From Equation (3.70), the peak amplitude of the resonant inductor current is ■'J-rtpcnk) 2V 24-10 VOOO/O.l) 0.443 A. (b) From Equation (3.71), the peak amplitude of the resonant capaci- tor voltage is v c„, F -(n-2K )(-l) = ^-3K = 21V. -rfpeak) <y 3.10 PARALLEL-LOADED RESONANT CONVERTER [4] In the parallel-loaded resonant converter, the load is connected directly across the resonant capacitor, C r , via a full-wave rectification circuit as shown in Figure 3.48. This converter is capable of providing an output voltage that is higher or lower in amplitude than its input voltage without the use of a transformer. Parallel-loaded resonant converters are mainly used for low-voltage, high-current applications since the output inductor reduces + + Vs/2 : Vs --c,_n — w A, D <vyr> — » £D 3 i B ID 5 L* C -.C ^ + Vs/2 = r ^ t} OZ 2 1 1 Vo Figure 3.48 Circuit schematic of a half-bridge parallel-loaded resonant con- verter. Resonant Converters 117 the ripple current in the output capacitor. For a sufficiently large output inductor, the output of the parallel-loaded resonant converter can be repre- sented as a constant current sink of magnitude I . The equivalent circuit of the parallel-loaded resonant converter is shown in Figure 3.49. In the steady- state, these converters can operate in either the discontinuous or continuous modes of operation. 3.10.1 Discontinuous Mode (0 < f -c0-5f„) Suppose before the beginning of a switching cycle, the resonant inductor current is zero and the output current, I , is freewheeling through the four rectifiers. The resonant capacitor is clamped at zero volt by the freewheeling action. The switching waveforms for the below-resonant discontinuous mode of operation are shown in Figure 3.50. Stage 1 (0 < t £ *i) begins when the switching transistor, Q u switches on at time t = 0. The equivalent circuit is shown in Figure 3.51(a). The rate of increase of the resonant inductor current is At The resonant inductor current increases linearly according to The duration of stage 1 is 2L r /„ 'l = rr ■ (3.78) (3.79) (3.80) Figure 3.49 Equivalent circuit for the half-bridge parallel-loaded resonant con- verter. 118 Power-Switching Converters 1 >t stage Figure 3.50 Switching waveforms for the discontinuous-mode half-bridge paral- lel-loaded resonant converter. Stage 2 (t x < t < t 2 ) begins when the resonant inductor current reaches the magnitude of the output current, /„, at time f,. The output current, 1 , is now supplied entirely by the input source. The resonant capacitor is charged by the difference between the resonant inductor current and the output current (i.e., i L (0 - I ). As the resonant capacitor voltage increases, rectifiers D 4 and£>s are reverse-biased. Rectifier D 3 and D 6 remain conducting and the equivalent circuit is shown in Figure 3.51(b). The rate of rise of the voltage across the resonant capacitor is dvc r (0 _ '/•,(') ~ 7 ° dt C t (3.81) The resonant inductor current begins to increase in a sinusoidal fashion. The rate of increase of the resonant inductor current, i^t), is JlXO ((K,/2) - v Cr (0) dt L r . (3.82) The resonant capacitor voltage, v c , (0, and the resonant inductor current i L (0, can be found using the initial conditions of 1^(0) = I and v Cr (0) — to yield Resonant Converters *'" //,(') = Jo + ^ sin [*>„(' - /,)], (3-83) and v Cr (0 = y [1 - cos w " ( ' _ ,,)] ' (3 ' 84) where Z a = y/{L t /Cj). It can be seen from the above equation that the resonant capacitor voltage approximates a haversine function with a peak value of V s . The resonant inductor current reaches its peak value when the resonant capacitor voltage reaches 0.5 V s . On the other hand, the resonant capacitor voltage attains its peak as the resonant inductor current decreases to I from its peak. The switching transistor, Q u remains conducting until its current decreases to zero at a time t 2 , given by [Tr + sin-'(2/ Z /K s )] (3g5) Thus, the switching transistors switch off naturally in the discontinuous mode of operation. Stage 3 (r 2 < / =£ t 3 ) begins when the anti-parallel diode, D u switches on at time t 2 as the current in the resonant inductor decreases to zero. The equivalent circuit is shown in Figure 3.51(c). The tank energy is fed back to the source through the antiparallel diode, D x . Stage 3 ends when the reson- ant inductor current decreases to zero from its negative peak at a time t 3 , given by '3 = 'i + [27r-sin-'(2/ Z /F s )] (3g6) o>„ Stage 4 (* 3 < / < t 4 ) commences at time r 3 . The resonant capacitor voltage during this time interval is "c, where :,(0 = £ I [ - /Jdr = v Cr (r 3 ) - ^> . (3-87) vc,('3) = y l-cos^-sin-'^)]. (3-88) 120 Power-Switching Converters The resonant capacitor continues to discharge its stored energy to the output shown by the equivalent circuit in Figure 3.51(d) until time u, given by as /4 = '3 + (3.89) Stage 5 (/ 4 < / ^ * 5 ) commences when the voltage across the resonant capacitor decreases to zero. The output circuit is now freewheeling through the rectifiers to maintain a constant output current, /„. This completes the first half-cycle of operation. The above half-cycle operation is repeated as the switching transistor, Q 2 , switches on at time r* except that the direction of the resonant inductor current and the polarity of the resonant capacitor voltage are reversed. The average output voltage is determined by rectifying and averaging the resonant capacitor voltage: Vo _ *£ 2^ _ COSWn( ,- ,)] d , + j;; [ Vc ,, 3) -Mf_^ _ 2 \(VJ2){<o„T, - sin(a> n r 3 )) | „ ^ _I£t\ (c)stage3(f 2 <fsf 3 ) (d)stage4(f 3 </s (,) Figure 3.51 Discontinuous-mode equivalent circuits for the half-bridge parallel- j loaded resonant converter. 121 Resonant Converters where T 3 = r 3 - h = and T 4 = t4-t 3 = [2TT-sin ' (2/qZ /K s )] (3.91) CtVcOi) (3.92) /o Thus, the output voltage in the discontinuous mode of operation can be regulated by controlling the off-time of the switching transistor while keep- ing its on-time fixed. 3.10.2 Continuous Mode (f s > f z or Above-Resonant Mode) There are six stages of operation in a switching cycle for the above-resonant continuous mode. In this mode of operation, the turn-on losses in the switching transistors are mitigated since they are switched on at zero reson- ant inductor current. The switching waveforms and equivalent circuits are shown in Figure 3.52 and Figure 3.53, respectively. Suppose before the switching transistor is switched on, there is no current flowing through the resonant inductor, while the resonant capacitor voltage is at some negative value. Stage 1 (0 < t < /,) commences when the switching transistor, Q,, switches onatf = 0. Since the resonant capacitor voltage is negative, both the resonant inductor current and the steady-state output current, J , flow into the resonant capacitor. The voltage across the resonant capacitor increases from its negative value. Stage 2 (fi < t =s h) begins when the resonant capacitor voltage reaches zero. However, the resonant inductor current continues to increase. The output current now flows through rectifiers D 3 and D 6 as the resonant capacitor voltage becomes positive. The resonant capacitor is now charged by the difference in the resonant inductor current and the steady-state output current (i.e., i Lr (t) - /„). Stage 3 (t 2 < t < h) begins when the switching transistor is forced to switch off at time t 2 . Since the resonant inductor current cannot be inter- rupted, the antiparallel diode, D 2 , starts to conduct. The resonant inductor current decreases from its peak value. However, the resonant capacitor voltage continues to increase as it is charged by the difference in the resonant inductor current and the output current (i.e., i Lr {i) - /„)- The resonant capacitor voltage is at its peak value when the resonant inductor current is equal to the steady-state output current. The resonant capacitor then begins to discharge in order to maintain a constant output current, 7„. Stage 3 ends 122 Power-Switching Converters stage TJZ Figure 3.52 Switching waveforms for the above-resonant continuous-mode half- bridge parallel-loaded resonant converter. Q, A L, / tr (0 Di- -Vs/2 v Ci (t) B Q, A L, /l r (0 I C D* (a) stage 1 (0<fs t,) (b) stage 2 ft < fs fe) D 2 A L, '^(0 VMO + 1 T - l pi_ —4 * C (c)stage3(fe<tsy Figure 3.53 Equivalent circuits for the above-resonant continuous-mode half- bridge parallel-loaded resonant converter. Resonant Converters 123 when the resonant inductor current decreases to zero at time t 3 . This com- pletes the first half-cycle of operation. The next half-cycle repeats the same way as the first half-cycle except that the direction of the resonant inductor current and the polarity of the resonant capacitor voltage are reversed. 3.1 0.3 Continuous Mode (0.5f„ <^f s < f„ or Below-Resonant Mode) There are six stages of operation in one switching cycle, as shown in Figure 3.54. The equivalent circuits for the first three stages are shown in Figure 3.55. Suppose before the start of a switching cycle, the resonant inductor current attains a positive value while the resonant capacitor voltage is negative. Stage 1 (0 < t == t{) begins when the switching transistor, Q u switches on at time t = 0. The resonant capacitor voltage increases from its negative value as it is charged by both the resonant inductor current and the output current, I a , until it reaches zero at time t t . Stage 2 (fi < t ■£■ t 2 ) begins when the resonant capacitor voltage reaches zero at time t x . The steady-state output current now flows through rectifiers D 3 and D&, as the voltage across the resonant capacitor becomes positive. The resonant cap- acitor is charged by the difference in the resonant inductor current and the Stage : Figure 3.54 Switching waveforms for the below-resonant continuous-mode half- bridge parallel-loaded resonant converter; 124 Power-Switching Converters (a) stage 1 (0<fs/i) (b)stage2(f 1 <f^f 2 ) =: ±Vg/2 D«— Vctilc, fa h (c)stage3(^<t^y Figure 3.55 Equivalent circuits for the below-resonant continuous-mode half- bridge parallel-loaded resonant converter. steady-state output current. The switching transistor, Q u remains conduct- ing until it is switched off naturally when the resonant inductor current reaches zero at time t 2 . Stage 3 {t 2 < t ^ t 3 ) begins when the antiparallel diode, £>,, starts to conduct and feeds the stored energy m the resonant tank back to the input source. Stage 3 ends when the switching transistor, Q 2 , is switched on at r 3 . This completes the first half-cycle of operation. The next half-cycle repeats the same way as the first half-cycle except that the direc- tion of the resonant inductor current and the polarity of the resonant capacitor voltage are reversed. Figure 3.56 shows the voltage conversion ratio, VJ0.5 V s versus fjf„ characteristics of a half-bridge parallel-loaded resonant converter. The output voltage of the parallel-loaded resonant converter operating in the below- resonant discontinuous mode is always less than the input voltage of 0.5 V % On the other hand, the output voltage can be higher than the input voltage of 0.5 V s for both the above-resonant and below-resonant continuous mode of operation. However, the above-resonant continuous mode is preferred since it can maintain a constant output current as the output voltage changes with a smaller change in frequency as compared to the other two modes of operation. Example 3.6. The parallel-loaded resonant converter shown in Figure 3.48 has the following parameters for its components: L r = 50 n-H, C T = 1 \lF, C = 500 n.F, L Q = 1 mH, and C f = 1000 u-F. The input source, V s , is a Resonant Converters 125 -a-'A Discontinuous mode Below-resonant continuous mode Above-resonant continuous mode Figure 3.56 Voltage conversion ratio (2 VJ V s ) versus fjf„ of a typical half-bridge parallel-loaded resonant converter. 12-V automotive battery and the steady-state output current, I , is 1 A. The switching frequency is 10 kHz and the resonant capacitor voltage is clamped at zero volt before the beginning of a switching cycle. Identify the mode of operation for this converter. Determine (a) the peak value of the resonant inductor current and (b) the duration that the switching transistor is switched on. Solution. The resonant frequency,^, is given by /- = 1 1tT->JL T C r : = 22.5 kHz. Since/, is less than 0.5 /„, the parallel-loaded resonant converter is operating in the discontinuous mode of operation. (a) The peak value of the resonant inductor current can be found from Equation (3.83). The resonant inductor current reaches its peak value when t = (t/2) 2vf H 11.1 u-s. 126 Power-Switching Converters (b) From Equation (3.85), the duration that the switching transistor is switched on is 2L, [ir + sin' 1 (2I Z /V S )] z VI PROBLEMS -w„ i = 43.43 jiS. 3.1. The ZCS quasi-resonant buck converter shown in Figure 3.9 has an input voltage of 48 V and a resistive load of 12 ft. The values of the resonant inductor and resonant capacitor are 4 jiH and 1 47 nF, respect- ively. The switching frequency is 100 kHz. The output inductor and output capacitor are lOmH and 100 jiF, respectively. Determine (a) the average output voltage, V a , (b) the duration of the resonant mode, and (c) the minimum load resistance for this quasi-resonant converter. 3.2. Draw a circuit schematic of a full-wave ZCS quasi-resonant buck converter with an M-type switch. Sketch the waveforms for the current flowing through the resonant inductor and voltage across the resonant capacitor over two switching periods given the following parameters: L T = 2\xH, C r = 79nF,/ s =200kHz,L o =10mH,and C o =100m-F. 3.3. The ZCS quasi-resonant boost converter shown in Figure 3.18 has an input voltage of 24 V and a resistive load of 40 ft. The values of the resonant inductor and resonant capacitor are 10|aH and 470 nF, re- spectively. The switching frequency is 25 kHz. The output inductor and output capacitor are 10 mH and 100 p.F, respectively. Determine (a) the average output voltage, V a , (b) the duration of the resonant mode, (c) the time when the resonant inductor current is at its negative peak, and (d) the minimum loadresistance for this quasi-resonant converter. "M- « Figure 3.57 Circuit schematic for Problem 3.4. Resonant Converters 127 3.4. Identify the topology of the quasi-resonant converter shown in Figure 3.57. Sketch the equivalent circuits for the four modes of operation in one switching period. 3.5. The ZVS quasi-resonant buck converter shown in Figure 3.25 has an input voltage of 24 V and a load resistance of 3 ft. The values of the resonant inductor and resonant capacitor are 2 u.H and 47 nF, respect- ively. The average output voltage, K a , is 12 V. The output inductor and output capacitor are lOmH and 100 u.F, respectively. Determine (a) the switching frequency, (b) the duration of the resonant mode, (c) the time that the current flowing through the resonant inductor crosses zero during the resonant mode, and (d) the maximum load resistance for this quasi-resonant converter. 3.6. Draw a circuit schematic for a full-wave ZVS quasi-resonant boost con- verter with a L-type switch with the following parameters: L t = 10 u,H, C r = 470nF,/ s = 25kHz,Z, o = 10mH,andC„= 100 nF. Sketch the wave- forms for the current flowing through the resonant inductor and voltage across the resonant capacitor over two switching periods. 3.7. Identify the topology of the resonant converter shown in Figure 3.58. State whether it is a full-wave or half-wave and L- or M-type switch. irr 1 Q v s Figure 3.58 Circuit schematic for Problem 3.7. Figure 3.59 Circuit schematic for Problem 3.8. 128 Power-Switching Converters 3.8. Identify the topology of the resonant converter shown in Figure 3.59. State whether it is a full-wave or half-wave and L- or M-type switch. 3.9. The series-loaded resonant converter shown in Figure 3.39 has the following parameters for its components: C r =0.1 fi.F, L T = 100 u.H, C f =2000fiF, and C o = 200|xF. The input source, V s , is 36 V and the output voltage is 12 V. The switching frequency is 20 kHz. Identify the mode of operation for this series-loaded resonant converter. Deter- mine (a) the peak amplitude of the resonant inductor current, (b) the duration of the negative resonant inductor current (i.e., t 2 — t{), and (c) the duration of the positive-cycle of operation, t 3 . 3.10. The parallel-loaded resonant converter shown in Figure 3.48 has the following parameters for its components: L r =100jiH, C r = 0.1|i.F, C f =2500pF, I =lmH, and C o = 470uF. The input source, V s , is 24 V. The switching frequency is 20 kHz. Identify the mode of oper- ation for this converter. Determine (a) the maximum steady-state load current, / , (b) expressions for the resonant inductor current when the upper switching transistor is switched on, and (c) the duration of the upper switching transistor switched on. 3.11. In the quasi-resonant ZCS buck converter, the output steady-state current, I , must be less than VJZ„ for the switching transistor to switch off during zero current. Explain its physical significance. REFERENCES 1. K. H. Liu, R. Oruganti, and F. C. Lee. Resonant switches — topologies and characteristics, IEEE Power Electronics Specialists Conference 1985, Record: 106, 1985. 2. K. H. Liu and F. C. Lee. Zero-voltage switching technique in dc/dc converters, IEEE Power Electronics Specialists Conference 1986, Record: 58, 1986. 3. N. Mohan, T. M. Undeland, and W. P. Robbins. Power Electronics: Converters, Applications, and Design, John Wiley & Sons, New York, 1989, p 164. 4. Y. G. Kang and A. K: Upadhyay. Analysis and design of a half-bridge parallel resonant converter, IEEE Power Electronics Specialists Confer- ence 1987, Record: 231, 1987. 1 1 % -i Transformerized Switching Converters 4.1 INTRODUCTION One of the most important drawbacks of the switching converter topologies, discussed in Chapters 2 and 3, is that their inputs and outputs are not isolated from each other. Isolation between the common or ground of the input supply and the output load is often desired to isolate the common returns from different parts of the electronic system to eliminate ground loops between circuitries. In switching power supplies, there is always a need to have multiple outputs with the same or different voltages for different load requirements. The switching converter topologies discussed so far can only provide a single regulated output. Transformers are commonly used to provide isolation between the inputs and outputs of alternating-current systems. In switching converters, transformers can also be used to isolate the output load from the input power supply. Transformers also provide the necessary voltage scaling, thus enabling a higher output voltage in all the topologies considered. The use of transformers thus offers the advantage of having multiple outputs at 129 130 Power-Switching Converters different voltage levels. The transformerized switching converters to be discussed in this chapter are the forward converter, push-pull switching converter, half-bridge switching converter, full-bridge switching converter, flyback converter, and resonant switching converter. Forward converters are used for medium power applications from 100 to 500 W. Push-pull-switch- ing converters are mainly used for high-power applications to a few thou- sand watts. Half-bridge and full bridge switching converters are mainly used for off-line applications. Flyback converters are often used for high-voltage applications for output power from about 5 to 200 W. The choice of a switching converter for a specific application often requires many other considerations such as economic feasibility, electromagnetic interference generation, and size and weight of the switching converter. 4.2 FORWARD CONVERTER The forward converter is the most commonly used switching converter for medium power applications below 500 W. A circuit schematic of the forward converter with a slave output is shown in Figure 4.1. The forward converter resembles the buck converter in that the switching transistor in the basic buck-switching converter is replaced by the transformer, the switching tran- sistor, and the rectifier combination. As shown, the center-tapped trans- former consists of two primary and two secondary windings. It should be noted that the dotted ends represent the transformer windings that are in phase with each other. This implies that the terminal voltages at the dotted ends increase or decrease simultaneously. The output with a negative feed- ©* Figure 4.1 Circuit schematic of the forward converter. Transformerized Switching Converters *** back loop is called the master output while the nonfeedback output is called the slave output. In general, the dynamic behavior of the slave output depends on the load and closed-loop characteristic of the master output circuitry. However, the regulation of the slave output voltage can be im- proved significantly with the use of a magnetic amplifier postregulator in the slave output circuitry. By using a magnetic core as a switch, it is possible to regulate the slave output efficiently with very few parts, over a wide power range, at a reasonable cost [1]. The operation of the forward converter in the continuous mode can be divided into two modes. Model (0<f<*i) Mode 1 begins when the switching transistor, Q u is switched on at t ^ 0. Since the dotted end of the primary winding, Np, is connected to the positive input supply voltage, V„ all the dotted ends of the transformer windings are positive with respect to the undotted ends. The current in the primary winding rises linearly from I\ to I 2 in time t on according to: h-h (4.1) Ki=Z., neglecting the saturated collector-emitter voltage of the switching transistor. The duration of mode 1 is The currents in the secondary windings rise synchronously with-the main primary winding, their magnitude being scaled by the inverse tums=ratio of the transformer (i.e., Np/N s ). The current in the secondary master winding increases from /,(iVp/JV sm ) to / 2 (7Vp/iV sm ) in time t on . The voltage at the dotted end of the secondary master winding is V\ N *m (4.3) N p ' where N sm is the number of turns in the secondary master winding. Similarly, the voltage at the dotted end of the slave secondary winding is V * = Vi N p iVss (4.4) Thus, different output voltages can be accomplished using different number of turns for the master and slave windings. In principle, the forward 732 Power-Switching Converters converter can accommodate multiple secondary slaves according to load requirements. Since the polarity of the dotted end of the secondaries is positive with respect to the undotted ends, the rectifiers, D x and 2> 2 , are forward-biased. The freewheeling diodes, D Tv ,i and £> rw2 , are reverse-biased. Thus, the input energy is "forward-transferred" to the output inductors during the on-time of the switching transistor and, hence, this switching converter topology is called the forward converter. Mode 2 (!„„ < t< T s ) Mode 2 begins when the switching transistor, £>,, switches off at r on . Since the current flowing through the main primary winding is now interrupted, the voltage across the primary winding reverses its polarity to oppose this . change. As such, the voltages at all the dotted ends of the transformer windings are now negative with respect to their undotted ends. The clamp diode, D c , connected between the dotted end of the reset winding, N T , and the input common, prevents this voltage from falling below its turn-on voltage of about 1 V. Hence, the rectifiers, X>i and D 2 , are reverse-biased. At the same time, the freewheeling diodes, £> fw i and Z> fw2 , are forward-biased and allow the output inductors to discharge their stored energies to satisfy the load requirements. Neglecting the leakage inductance of the transformer, the voltage across the primary winding is v P (/)=-^. (4-5) Neglecting the voltage drop across the clamp diode, the voltage across the reset winding is simply the input supply voltage, V v The off-state collector voltage of the switching transistor is then If the number of turns in the reset winding, N T , is equal to the number of the primary winding, N p , then the voltages across the primary and reset wind- ings are equal to the input supply voltage, V % . The voltage at the collector of the switching transistor. is then twice the input supply voltage, i.e., 2V„ The off-state collector voltage is smaller if the number of turns in the reset winding is "larger than the primary winding as shown in Equation (4.6). However, the peak primary current for a given output power is greater than the case when N T is equal to N p . The voltage spike observed at the collector of the switching transistor shown in Figure 4.2, immediately after it Transformerized Switching Converters 133 V hB ,4 Vd(0t V, - /dO fec(0 l_l^ -> t * i -* t ^ ^ . . > D1 (0 ,v sm -». f Vsm(0 . v,5l *• t ,¥ sm. t» T Figure 4.2 Switching waveforms of the forward converter for NJN V . j34 Power-Switching Converters is switched off, is due to the stray inductance in the collector circuit and leakage inductance in the transformer. This is because the falling current of the switching transistor induces a positive-going spike at the collector according to where L ik is the sum of the stray and leakage inductances in the collector circuit. The clamp diode, D c , conducts immediately after the switching tran- sistor is switched off at t on . Thus, the trapped energy in the primary winding is fed back to the input source. It remains conducting for a time t T to satisfy the volt-second product given by "GH = t v- ( 4 - 8a ) 'on * J or t -t ^- ( 4 - 8b ) This is because the magnetic core in the transformer must be completely reset before the beginning of the next switching cycle. In magnetic terms, the core must be restored to its original position on the hysteresis loop or the core will be saturated. Thus, the on-state volt-second products must be equal to the off-state volt-second products, as shown in the cross-hatched areas of Ai and A 2 , respectively, of Figure 4.2. The clamp diode, D c , switches off after satisfying the volt-second requirement of the magnetic core. The col- lector voltage of the switching transistor is now equal to the input supply voltage, V h for N T equals N p . It is essential to choose a switching period greater than the sum of t oa and t T to ensure that the magnetic core is reset before the start of the next switching cycle. If the transformer is completely reset before the next switching cycle, the maximum value of (r/T) is (1 - £>)- Therefore, the maximum duty cycle, D ma% , with a given turns ratio, Nr/N p , is Cr/n™ = (1 " ^ = D m {N T /N p ) (4-9a) or D \ (4.9b) Transformerized Switching Converters *35 The maximum duty cycle is 50% if the number of turns of the reset winding, tf n is equal to the number of turns of the primary winding, N p . The maximum duty cycle will be larger than 50% if the number of turns of the reset winding is smaller than the number of turns of the primary winding. The voltage conversion ratio of the forward converter can be derived by imposing the constant volt-second relationship on the output inductor, L om , of the master secondary output. The average voltages across the output inductor are ( V, (iV^/JVp) - K am ) and - V am during the on-time and off-time, respectively. V am is the average output voltage of the secondary master output. Thus, ( v *ir- Kam )'» n + ( - v ™ )ton = °- (410) The voltage conversion ratio is (4.11) <%> It can be seen that the voltage conversion ratio of the forward converter is similar to that of the conventional buck converter. The turns ratio, N sm /N p , is to account for the voltage scaling of the transformer in the forward converter. Following a similar analysis as in the buck converter, the peak-to-peak ripple current in the output inductor is .. DVi{N m /N v )il-'D) (4 . 12) JsJ-'om The output ripple voltage of the forward converter is A Vom = Vi ^ Dil - D \ < 413 > As can be seen, both the peak-to-peak inductor ripple current and output ripple voltage of the forward converter are similar to those of the conven- tional buck converter, except that they are scaled by the transformer turns ratio, (NsJNp). The forward converter has a low output ripple voltage. However, it nas a poor transient response and its efficiency's low due to poor transformer utilization. Thus, the size and weight of the transformer is a major factor in choosing the forward converter for a specific application. 73(5 Power-Switching Converters Example 4.1. The forward converter shown in Figure 4.1 has an input supply voltage of 60 V and an average output voltage of 5 V at the secondary master output. The switching frequency is 1 kHz with a maximum output inductor ripple current of 0. 1 A. The number of turns in the primary winding is 60 and the turns ratio, NJNp, is equal to one. Determine (a) the smallest number of turns in the secondary master winding Nsm, and (b) the output filter inductance L om . Solution. (a) From Equation (4.9b), the maximum duty cycle Z> max is - 1 _ 1 _ n s Dma *-l + (N r /N p )-l + \-™- From Equation (4.1 1), Therefore, the smallest number of turns in the secondary winding is (/\L m > = N„ 1 — 1 — ^— = 60 ( — ) — r = 10 turns. VVsm/mra J ^\60j D max \60j 0.5 (b) From Equation (4.12), DV^N m /N v ){\-D) 0-5(60)(10/60)(l-0.5) ^ 0025H ^ mH jLom_ / s A/ om 1000(0.1) 4.3 PUSH-PULL CONVERTER The push-pull converter is derived from two forward converters working in antiphase. As such, the push-pull converter topology has the advantage over the forward converter in that the voltage across the transformer and, hence, the peak collector voltage of the switching transistor is limited to twice the input voltage. This is due to the symmetrical center-tapped transformer with equal number of turns in the primary windings. Since the power supplied to the load is never stored in the transformer, more power can be handled at a greater efficiency and with a better regulation than the forward converter. The basic circuit schematic of a push-pull converter is shown in Figure 4.3. The switching transistors, Qi and Qi-> alternately conduct each half cycle at a Transformerized Switching Converters 137 V <W I'amO Pulse-width modulator & Base driver Error Amplifiej Figure 4.3 Circuit schematic of the push-pull converter. duty cycle determined by the input supply voltage, V„ transformer turn ratio, and the desired output voltage. Thus, the maximum duty cycle attainable is slightly less than 50% to account for the turn-off times of the switching transistors. Otherwise, "shoot through" will occur in the two switching tran- sistors, resulting in irreversible damage to them. This "shoot through" phe- nomenon can be avoided by defining a dead time, t d , between the turn-on of Q 2 and the turn-off of Q, switching transistors. The dead time t d should, at least, be equal to turn-off times of the switching transistors. When the switching transistor, Q u is switched on during the first half of the switching period, all the undotted ends of the transformer windings are now positive as the input supply voltage is applied across the primary winding, N pl . Its collector current, f c i(0, increases linearly from h to h m time r on as shown in Figure 4.4. The collector of the switching transistor, Q 2 , is now at twice the input supply voltage since both the primary windings have the same number of turns. The voltage at the anode of the rectifier D t is a rectangular waveform of the input supply voltage, V„ except it is scaled by the turns-ratio of the transformer: Vl . V ."2. (4.14) where N p < N pl < N p2 . The rectifier D x is now forward-biased. Thus, the output inductor, L om , is charged during this time interval. The current flowing through the rectifier D x , i Dl (t), is a scaled version of the collector current, i cl (t): (4-15) 138 PWM(Q,) * ^ce(0 'd(0 f W) t 'c2(D Vi(0 'D,(0 ^/1 Power-Switching Converters h 2i Hi -2V, Hi r^o 2V, -V, Ng. N, N„ £-'* Figure 4.4 Waveforms of the push-pull converter. -* f -*• J rt rt . -» / Transformerized Switching Converters 139 The switching transistor, Q u is switched off at t < / on . It should be noted that t on must be less than half the switching period to accommodate the turn- off time of the switching transistor. As the switching transistor, Q u is switched off, a voltage spike appears at its collector due to the induced voltage caused by the falling collector current and the stray and leakage inductances in the collector circuit. The collector voltage momentarily drops to the input supply voltage after the trapped energy is dissipated. The collector voltages of the two switching transistors are now at the input supply voltage since both are switched off. As the collector current m Q x drops abruptly to zero at f on , a ledge current continues to flow through the rectifiers before the other switching transistor, Q 2 , is switched on as shown m Figure 4.5. This ledge current is due to the voltage reversal of the output inductor, L om , as the switching transistor, Q u is switched off. The negative voltage at the cathodes of both rectifiers causes them to be forward-biased. Each rectifier is now carrying half the total current in the inductor. Hence, the rectifiers in the push-pull converter perform the func- tion of freewheeling as in a conventional buck converter. The voltage conversion ratio of the push-pull switching converter can be derived by imposing the constant volt-second relationship on the output PWM(qj)(Q v 2 {t) — . *■ .. „ L wo Figure 4.5 Output waveforms of the push-pull converter. 240 Power-Switching Converters inductor, L om . Neglecting the on-state voltages of the switching transistor and the rectifier, the average voltage across the output inductor, when either one of the switching transistors is switched on, is ( V\ (NjJN p ) - K am ). During the freewheeling of the rectifiers, the average voltage across the output inductor is — V am . Thus (Vi^- V am y ton - V am {T - 2/ on ) = 0. (4.1&) The factor of 2 for f on is to account for the fact that the output inductor is charged twice in one switching cycle. The voltage conversion ratio is *-— K®^) (4,7) or v~ = lW-v~dj=-vj%?- (418) "p when the on-state voltages of the switching transistors and rectifiers are taken into consideration- The most common failure mode in the push-pull converter with bipolar switching transistors is caused by a flux imbalance in the transformer. This occurs when the volt-second products across the two primary windings are not equal to each other. When this occurs, the mag- netic core will not return to its original starting point in its hysteresis loop after a switching cycle. After a number of switching cycles, the magnetic core will saturate. Once in saturation, the magnetic core will not be able to support the applied input voltage. Thus, the bipolar switching transistors are subjected to high current and high voltage situations and may eventually be destroyed due to thermal run-away. This failure mode is less severe in the push-pull converter with power MOSFET switching transistors. This is due to the negative temperature coefficient of the drain current in power MOSFETs. As the device temperature increases in a power MOSFET due to a flux imbalance problem, its drain current tends to decrease. Thus, thermal runaway caused by flux imbalance in the transformer is mitigated in the push-pull converter with the use of power MOSFETs. 4.4 HALF-BRIDGE SWITCHING CONVERTER The half-bridge topology is primarily used in off-line switching converters since their switching transistors are not subjected to twice the input supply Transformerized Switching Converters 141 voltage as in the forward and push-pull switching converters. Figure 4.6 shows the circuit schematic of a half-bridge switching converter. As shown, the undotted end of the transformer is connected to the common terminal of the two identical filter capacitors, C n and C c , via a DC blocking capacitor, C b . The DC blocking capacitor can be omitted in some applications. A drop in primary voltage will result due to the charging of this capacitor by the current flowing in the transformer. The input supply voltage, V K is divided between the two filter capacitors. Thus, the common terminal of the filter capacitors has an average voltage of V-J2. The purpose of the DC blocking capacitor, Cb, is to avoid the flux imbalance problem caused when the voltage at the common terminal is not exactly half the input supply voltage. The dotted end of the transformer is connected to the common terminal of the switching transistors configured in a totem-pole configuration. The switching transistors, Q\ and Q 2 , alternately conduct each half cycle of a switching cycle. Thus, the two switching transistors alternately connect the dotted end of the transformer to V x or ground, while the undotted end of the transformer is maintained at V-J2. When the switching transistor, Q x , is switched on, the voltage at the dotted end of the primary winding is now Kj. The voltage across the primary winding is VJ2, since the undotted end is maintained at VJ2. Thus, the polarity of the voltages at all the dotted ends of the secondary windings is positive. The collector of Q 2 is at K ; as long as Qi remains conducting. The rectifier, Z> 2 , conducts and the output in- ductor, L , is charged during this time interval. When Q\ is switched off at t :£ / on , the dotted end of the transformer is now grounded by the switching transistor, Q 2 . The undotted ends of the transformer windings are now Pf> " a (0 Figure 4.6 Circuit schematic of a half-bridge converter. 7* J42 Power-Switching Converters positive with respect to the dotted ends. Rectifier D, is now forward-biased and the output inductor is charged. It is obvious that the voltage across the primary winding is always maintained at half the input supply voltage. During the interval between the on-time of the two switching transistors, the two rectifiers, 2>, and D 2 , are freewheeling as the energy stored in the output inductor, L , is transferred to the output capacitor and the load as the ledge current. Figure 4.7 shows the switching waveforms of the halt- bridge switching converter. The voltage conversion ratio of the half-bridge switching converter can be derived by imposing the constant volt-second relationship on the output inductor. The average voltages across the output inductor are [(F ; /2) (JV s /W p ) - V a ] and -K a during t on and / ofr , respectively. Thus (jn;- v v t v *t "■ (4.19) PWMtQOft) . 'd(0 * '1 ■ n~ I_n3_ >t 7 w _r£XJ • > W) "l -^_sL_ . ■ — * -*■ i m Figure 4.7 Waveforms for the half-bridge converter. Transformerized Switching Converters The factor of 2 for r on is to account for the fact the output inductor is charged twice in one switching cycle. The voltage conversion ratio is #>© (4.20a) or when the on-state voltages of the switching transistors and rectifiers are taken into consideration. The half-bridge switching converter requires a more complex control circuitry. An isolated driver is required for the switching transistor, Q\, since its emitter is not directly connected to ground. The filter capacitors are usually bulky and costly since they have to handle the full primary current. The full-wave output of the half-bridge switching converter results in the use of smaller output inductor and capacitor when compared to the forward converter. The other important feature of the half-bridge switching con- verter is that the leakage inductance spikes are clamped to the input supply bus. Thus, any energy stored in the leakage inductance is conducted back to the input bus instead of having to be dissipated in some resistive elements. 4.5 FULL-BRIDGE SWITCHING CONVERTER The full-bridge converter topology is primarily used in off-line switching converters since-their switching transistors are only subjected to the magni- tude of the input supply voltage V,. Figure 4.8 shows the circuit schematic of a full-bridge converter. As shown, the switching transistors are configured m a full- or half-bridge topology. The switching transistor pairs of Q x - Qa and q 2 _ g, are switched on alternately during each half cycle of a switching period. When the transistor pair, g, - Qa, is switched on, the dotted end of the primary winding is connected to the input supply voltage, V u while the undotted end of the primary winding is connected to near ground potential. Thus, all the dotted ends of the secondary windings are now positive with respect to their undotted ends. The output rectifier, D 2 , conducts and delivers the energy to the output inductor. The voltage at the secondary winding is a scaled version of the primary winding voltage. When the transistor pair, Q 2 - Qs, is switched on, the undotted end of the primary winding is now-at V„ while the dotted end is at near ground potential. The output rectifier, D u conducts and delivers energy to charge the output 144 Power-Switching Converters PWNKQ,) v, PWM(Qj) J ^ W s 'o^to *tJ At " T R^. Ya vM SO, 3% yo 3H v„ pwM(o 2 )n pwM(o 4 >n •w Figure 4.8 Circuit schematic of a full-bridge converter. inductor. The rectifiers, D, and D* are freewheeling when both the switch- ing transistor pairs are switched off. Figure 4.9 shows the switching wave- forms of the full-bridge converter. The voltage conversion ratio of the full-bridge converter can be derived by imposing the constant volt-second relationship on the output inductor. The average voltages across the output inductor are [ViWNp) - V a ] and - K a during t on and t o(T , respectively. Thus 0£-k.)*=- K.^L=0. The voltage conversion ratio is Vi~ \nJ\tJ' or V: *-*®* (4.21) (4.22a) (4.22b) The output power of the full-bridge converter is double that of the half- bridge converter because the full input supply voltage, rather than half, is applied to the primary winding. The full-bridge converter has good trans- former utilization. However, it requires a more complex driver circuitry that is capable of driving high-side and low-side switching transistors. The flux imbalance is also a potential problem in the full-bridgexonverter. Transformerized Switching Converters pWM(Q„Cy(<) t 145 W>.'c4<0. /, - ft* VdM. U0» V. rn ** -■ — w Figure 4.9 Waveforms for the full-bridge converter. 4.6 FLYBACK CONVERTER The flyback converter is widely used for high voltage as well as offline power supplies applications. It is essentially a constant-output-powef switching converter. An output inductor is not required for the flyback converter. As such, it is attractive for multiple output application with a better output voltage tracking than most other switching converter topologies. The sav- ings in cost and size, due to the absence of the output inductor, is a significant advantage over other switching converter topologies. Figure 4.10 shows the circuit schematic of a flyback converter. When the switching transistor, Q s , is switched on at r < 0, the dotted ends of the windings are negative with respect to the undotted ends. As such, the output rectifier, D u is reverse-biased. During this time interval, the output load current is maintained by the output capacitor, C . It should be noted that a 146 Power-Switching Converters / P (0 Pulse-width modulator and driver Figure 4.1 Circuit schematic of a flyback. freewheeling diode is not required for the flyback converter. Neglecting the on-state collector-to-emitter voltage drop of the switching transistor, Q s , the current in the primary winding increases linearly at a rate determined by d/ dr V (4.23) where L p is the magnetizing inductance of the primary winding. The peak primary current, / p , ma x> is given by •*p, max — r ' (4.24) where t on is the on-time of the switching transistor. It can be seen that the maximum input current, J p , ma x does not depend on load variation. Thus, the flyback converter delivers a constant power. The switching transistor is switched off at / ^ t on . Since the current flowing in the primary winding cannot change instantaneously, the voltage across the primary winding reverses its polarity. As such, the dotted ends of the windings are now positive with respect to the undotted ends. The output rectifier, D u is now forward-biased and current flows from the secondary winding. The current in the secondary winding decreases linearly at a rate determined by dz s At (4.25) 147 Transformerized Switching Converters where L s is the magnetizing inductance of the secondary winding and V s is the voltage across the master secondary winding. The peak secondary cur- rent, /s.max, is related to the peak primary current and is given by 's,max ~ Uj 7 *' (4.26) If the current in the secondary winding has decreased to zero before the switching transistor switches on again as shown in Figure 4.11, the flyback converter is said to be operating in the discontinuous mode of operation. Thus, the flyback converter first stores the energy in the trans- VM pi'/ At - V, | - I ._ -+■ t T v s O 1 V,^L w p > - -v a _ Figure 4.1 1 Waveforms for the diseentimious-mode flyback converter. or , _ /sfV\/ (4.29b) since (N p /N S ) Z ={L P /L s ). The average load current, J a , can be found by integrating the current in the secondary winding over a switching period, T: i --j CA ( 4 - 30 > From Equation (4.30), t 2 can be found: V a N n 2L n^VpZLs (4.31) where R is the load resistance. j^g Power-Switching Converters j| former during the on-time, and subsequently, transfers this energy to the load during the off-time of the switching transistor. The input power, P„ is defined as _ -MJ P ,max) 2 (4.27a) 2r From Equation (4.24), the input power can also be expressed as _ (Ki/ on ) 2 (4.27b) ' 2TL P " Since the flyback converter is a constant-power switching converter, its output voltage is maintained by keeping the product V, t on constant. The efficiency of this converter is defined as _ Pout _ (l/27"V snlax _ L^ Ms, max \ (4.28) V ~ Pi -(l/2T)L p Il mm L p \I p , ma *J " The relationship between the primary and secondary winding currents can be found from Equation (4.28) as: 'h.r (4.29a) Js,max — v^y j M>, Transformerized Switching Converters 149 The flyback converter is said to be operating in the continuous mode of operation if the switching transistor is switched on while energy is dumped into the load. The switching waveforms of a continuous mode flyback converter are shown in Figure 4.12. When the switching transistor is switched on at I < 0, the current in the primary winding increases linearly from a minimum value of I p , m m according to: to a maximum value of / p in time / Ki = L. / P „ ■*p,min (4.32) IM ->- f yo Vs(0 J t 1/Ns N P s, oil - Figure 4.12 Waveforms for the continuous-mode flyback converter. 750 Power-Switching Converters When the switching transistor is switched off at / ss / on , current appears in the secondary winding and decreases linearly from a maximum value of / sjnax to a minimum value of / s mjn in time t otr according to: J s,max v j -*s,niax A, min {4 Ji") 'off where L s is the inductance in the secondary winding. Since the switching transistor is switched on again before the second- ary current drops to zero, it is transferred back to the primary through the current, I p ^j„. The secondary current is related to the primary current through the inverse turns-ratio of the transformer / j — Np (i - I - ) (4.34) •"s, max 's,min — ~jj~ \ J p,ma% *p,mmj- v ' The average output current, 7 a , is • A, max ~r Js,min t ff (4 3^\ a _ 2 T ' The average output voltage, V a , of the flyback converter operating in the continuous mode is V -y.(^l\ D (4.36) The off-state collector voltage of the switching transistor is Vc =V i + ^V a . (4-37) The discontinuous mode flyback converter is suited for those applications, which require a constant output current, while the continuous mode flyback converter is suited for applications that require a constant output voltage. The discontinuous mode flyback converter responds more rapidly and with a lower transient output voltage spike to sudden changes in load current or input voltage when compared to the continuous mode flyback converter. However, the peak currents in the discontinuous mode are larger than those in the continuous mode. As such, the discontinuous mode flyback converter requires a flyback transformer with a larger current rating and output capacitor with a larger ripple current rating than those required in the continuous mode flyback converter. The design of the flyback transformer WP"' 5. Transformerized Switching Converters 151 [3-5] is also critical due to poor transformer utilization. The input supply is isolated from the load so that faults, which occur on the secondary, are not directly reflected to the primary. The flyback converter also has a high output ripple voltage due to the absence of the output inductor. Three flyback converter designs are evaluated in Chapter 10. Example 4.2. The continuous-mode flyback converter shown in Figure 4.10 has an input voltage of 50 V and an average output voltage of 100 V. The magnetizing inductance of the primary winding, Lp, is 1 mH. The turns ratio, (N s /N p ), is 4. For a switching frequency, f s , of 1 kHz, determine (a) the duty cycle and (b) the magnetizing inductance of the secondary winding. Solution. (a) From Equation (4.36), o^d) = w WJ = \io) w ~ °" Therefore, the required duty cycle is P = 5|= 0.333. (b) The magnetizing inductance in the secondary winding, L s , is L s = *v(?f\ = (1 mH)(4) 2 = 16mH. 4.7 ZERO-CURRENT-SWITCHING QUASI-RESONANT HALF-BRIDGE CONVERTER [2] The circuit schematic of a ZCS, half-wave, quasi-resonant half-bridge con- verter with secondary-side resonance is shown in Figure 4.13. As shown, it is similar to the conventional half-bridge converter except for the resonant capacitor, C r , connected across the freewheeling diode, Z> fw . The secondary- side resonant ZCS quasi-resonant converter makes use of the leakage in- ductance, L T , of the transformer as the resonant inductor. The operation of this converter can be divided into four modes. All components, except the transformer, are assumed to be ideal. The output inductor, L , is much larger than the leakage inductance of the transformer, L T . Thus, the output inductor, output capacitor, and the load, can be modeled as a constant 152 Power-Switching Converters Co±f\ Figure 4.13 Circuit schematic of a ZCS, half-wave, quasi-resonant half-bridge converter. current sink of /„. Suppose before the switching transistor, Q„ is switched on, the freewheeling diode, Aw, carries the steady-state output current, J , and the voltage across the resonant capacitor, K c , (/ =£ 0), is clamped at zero volt by the freewheeling diode. Model (0< f<fi) Mode 1 begins when the switching transistor, Q u switches on at t = 0. The current in the upper secondary winding of the transformer, i Lt {t), increases linearly from zero to the steady-state output current of I . Its equivalent circuit is shown in Figure 4.14. The voltage across the upper secondary winding is related to the rate ot rise of its current. At the end of mode 1, the voltage across the upper secondary winding, v S)UpP er (' i)» is given by Vs,upper' (ri) = VjN s 2N n u 7V (4.38) M& L, 2W„ c, I OL ® Figure 4.14 Mode 1 equivalent circuit for the ZCS, half wave, quasi-resonant half-bridge converter. 153 Transformerized Switching Converters where N s and N p are the numbers of turns in the secondary and primary windings, respectively. The duration of mode 1, T\, is T\ 2LrI N p ViN s (4.39) Thus, mode 1 is characterized by charging of the leakage inductance of the transformer and the storage of electrical energy in magnetic form in the resonant inductor. Mode2(fi<f^fe) Mode 2 begins when the current flowing through the upper secondary winding reaches the steady-state output current of /„. Its equivalent circuit is shown in Figure 4.15. . The voltage across the resonant capacitor, v c ,(0> increases, as it is charged by the difference between the input current, u,(0, and output steady-state current, I a (i.e., i Lf {t) - /„). The freewheeling diode, Aw, is reverse-biased as the voltage across the resonant capacitor increases accord- ing to dt C t (4.40) The current in the upper secondary winding, //,(/), continues to increase in a sinusoidal fashion according to L ' dt 2N P QK) (4.41) The above two first-order differential equations can be solved using the following initial conditions: vc,(/i) = 0, /L r (r,) = /o- (4 " 42) Figure 4.15 Mode 2 equivalent circuit for the ZCS, half wave, quasi-resonant half-bridge converter. j 5 . Power-Switching Converters The expression for the resonant inductor current, 1^(0, is mo=/.+2^»o*o (443) and the expression for the resonant capacitor voltage, v Cf (0, »s v Q (0=-^U-cos( Wn 0], < 444 ) where Z„ = y/LJC, is the characteristic impedance and w n = l/y/LrC T is the resonant frequency. Zero-current switching requires that 7 - v i N * (4-45) "~2N P I ~ Mode 2 ends when the current in the resonant inductor, i Lt (t), reaches zero. At this time, the switching transistor, Q u should be switched off to take advantage of the ZCS condition. The duration of mode 2 can be found by setting Equation (4.43) to zero and solving for T 2 = t 2 - t x : Ur 2 )=/o + ^|;sin(a, n r 2 ) = 0. (4-46) Thus, _ sin' 1 \-{2IoZ„N p /ViN t )) _ a_ (4 . 47) where a takes on values between it and 3ir/2. Mode3(f 2 <f<f 3 ) Mode 3 begins when the current flowing through the resonant inductor, iY(r) decreases to zero. Its equivalent circuit is shown in Figure 4.16. Since the unidirectional switching transistor, Q u prevents current reversal through the resonant inductor, the resonant capacitor begins to discharge its stored energy to the output. The freewheeling diode, £> rw , is still reverse-biased by the voltage across the resonant capacitor. The voltage across the resonant capacitor decreases linearly according to dvr V-.Ns ., . ht (4 48) C '-df=2^ (1 - COSa) -Q- ( } Transformerized Switching Converters 155 Figure 4.16 Mode 3 equivalent circuit for the ZCS, half wave, quasi-resonant half-bridge converter. Mode 3 ends when the voltage across the resonant capacitor becomes zero. The duration of mode 3, T 3 , is *-^*«— * (4.49) Mode4(f 3 <f<7y2) Mode 4 begins when the voltage across the resonant capacitor decreases to zero at time t = t 3 . The freewheeling diode, Z> fw , starts to conduct and the output current is freewheeling through it. Its equivalent circuit is shown in Figure 4.17. The duration of mode 4 is r 4 = r, - T 2 - T 3 , (4.50) where T s is the switching period. Figure 4.18(a) and (b) shows the switching waveforms of the ZCS, quasi-resonant half-bridge converter. The voltage conversion ratio of this converter can be derived by imposing the constantjrolt-second relationship on the output inductor, L . The average voltages across the output inductor are ((V;NJ2Np) - V a ) and -V a during the resonant period T n and ((TJ2) - T„) intervals, respectively. Thus, m-^-^i-^- (4.51) Figure 4.17 Mode 4 equivalent circuit for the ZCS, half wave, quasi-resonant half-bridge converter. Power-Switching Converters Figure 4.18 Switching waveforms for the ZCS, half-wave, quasi-resonant, half- bridge converter [2]. Transformerized Switching Converters 157 The voltage conversion ratio for maximum load (i.e., /„ Z„ — ( V { N S /2N P ) ) is Vi UpJU)' (4.52) *\ V'P/ Vn/ Figure 4.19 shows the straight-line characteristics of the voltage conversion ratios for several x values [2], where x = 2/ Z„JVp/Ki7V s . Example 4.3. The ZCS, half-wave, quasi-resonant half-bridge resonant converter shown in Figure 4.13 has an input voltage, V h of 50 V and a steady-state output current, /„, of 5 A. The capacitance for the resonant capacitor is lOu-F. The turn-ratio of the transformer is 2, with a leakage inductance, L r , of 10|iH. Determine (a) the peak amplitude of the resonant inductor current, (b) the peak value of the resonant capacitor voltage, and (c) the duration of the resonant mode. Solution. (a) From Equation (4.43), the peak value of the resonant inductor current is ViN s II, = h + 2V a N s IV s N ( 2N P Z„ = 55A. Figure 4.19 Voltage conversion versus fjf„ of the ZCS, quasi-resonant half- bridge converter for several normalized output current values [2]. , eg Power-Switching Converters (b) From Equation (4.44), the peak resonant capacitor voltage is c ' 2N p 2 (c) For a half-wave mode, a takes on values between tr and 3W2. Thus, sin' 1 ( - 0.1) = ir + 0.1 = 3.1416 + 0.1^3.2416. From Equation (4.47), the duration of the resonant mode is T 2 = sin"' (~ 27 ^ P ) V^Cr = 32.4 ^s. PROBLEMS 4 1 The forward converter shown in Figure 4.1 has an input voltage of 50 V and a switching frequency of 1 kHz. The average output voltage is 25 V with a maximum duty cycle of 0.6. The number of turns of the primary winding is 100. Determine (a) the number of turns of the reset winding, (b) the number of turns of the secondary winding, and (c) the duration, t T when the secondary current is flowing. 4 2 The discontinuous-mode flyback converter shown in Figure 4. 1 has an input voltage of 50 V. The magnetizing inductance of the primary winding is 500 |xH with a turns ratio, NJN P , of 4. The switching frequency is 1 kHz with a duty cycle of 20%. Determine (a) the peak value of the primary current, (b) the duration of the secondary current t r , and (c) the average output voltage. 4 3 The ZCS half-wave, quasi-resonant half-bridge resonant converter shown in Figure 4.13 has an input voltage of 40 V and a steady-state output current of 5 A. The capacitance for the resonant capacitor is 1 p.F. The turn-ratio for the transformer is 2, with a leakage inductance of 10|xH. Determine (a) the peak amplitude of the resonant inductor current, (b) the duration of the resonant mode, and (c) the switching frequency required for the maximum load. 4 4 Derive the expressions for the duty cycle, output voltage, and average input current for a flyback converter operating in the discontinuous mode. Transformerized Switching Converters *->" REFERENCES 1. T. Roullier and C. Lam. Magnetic amplifier post regulator simulation provides load and temperature effects, PCIM, July 1993, pp 26-34. 2. M.M. Jovanovic, D.C. Hopkins, and F.C. Lee. Design aspects for high- frequency off-line quasi-resonant converters, High-Frequency Power Conversion Proceedings, April 1987, pp 83-97. 3. Power Integrations, Inc., TOPSwitch Flyback Transformer Construc- tion Guide Application note AN- 18, July 1996. 4. L. Dinwoodie. Designing a 50-Watt Flyback Converter, Texas Instru- ments, January 2002. 5. Texas Instruments, Inductor and Flyback Transformer Design, Mag- netics Design Handbook — MAG100A, section 5, 2001. Control Schemes of Switching Converters 5.1 INTRODUCTION The figure-of-merits in switching converters are the load and line regula- tions. Load regulation is defined as the change in the output voltage corre- sponding to a 1-mA change in the load current while line regulation is defined as the change in the output voltage corresponding to a 1-V change in the input voltage. The load and line regulations of the switching con- verters depend largely on their control schemes. By varying the on time of the switching transistor in a switching converter, the output voltage can be maintained at a constant during load variations and supply-voltage vari- ations. Pulse-width modulation (PWM) is the most common control scheme for switching converters. The abundance of commercially available PWM integrated-circuit controllers has contributed to making the switching con- verters ajjppular choice in many system applications. On the other hand, the resonant switching converters require a variable-frequency controller or frequency modulator to achieve the desired energy conversion. The imple- mentation of the variable-frequency controller is more involved than the 161 /52 Power-Switching Converters pulse-width-modulated-controller. This chapter presents the most common control techniques for DC-DC switching converters and a description of some commercial controller circuits. 5.2 PULSE-WIDTH MODULATION The technique of modulating the duration of the ON or OFF pulses, or both, that are applied to the switching transistor is called pulse-width modulation (PWM). The purpose of the PWM is to vary the duty cycle d according to d=t oa f s = /on . (5.1) 'on + ^ofT Thus, modulating either t on or t off or both can vary d. There are two schemes of PWM: the fixed-frequency PWM and the variable-frequency PWM. The variable-frequency PWM can be achieved by: (a) keeping f on fixed and varying / o(T , (b) keeping t oIT fixed and varying t on , and (c) changing both r on and t „ as shown in Figure 5.1(a)-(c), respectively. The major problem associated with the variable-frequency PWM is the unpredictable electro- magnetic interference (EMI) due to the varying switching frequencies. The fixed-frequency PWM is achieved by changing both the t on and f ofr durations while maintaining a constant switching period, as shown in Figure 5.2. This PWM scheme is the most popular due to its ease of implementation by commercially available integrated-circuit controllers and because its EMI can be filtered without difficulty. There are two PWM modes of operation depending on the control signals required. The voltage-mode PWM derives its control signal from the output voltage of the switching converter, whereas the current-mode or current-injected PWM utilizes both the output voltage information as well as the information from the inductor current in the switching converter to determine the desired duty cycle applied to the switching transistor. 5.2.1 Voltage-Mode PWM Scheme The schematic of a fixed-frequency voltage-mode PWM controller is shown in Figure 5.3(a). The error amplifier compares the sampled output voltage V sp with a fixed reference voltage K ref and generates an error voltage V c given by: Control Schemes of Switching Converters PWM signal 163 PWM signal toll ton ?1 ''oft ton (a) PWM signal ton PWM signal * ton T, tott , ' (b) PWM signal PWM signal < (o« « ' -■ — <on T ''oil , °" Z (c) Figure 5.1 Variable-frequency PWM schemes: (a) fixed t on , variable t otr ; (b) variable / on> fixed t o!T ; and (c) variable / on , variable / rr- This error voltage is then fed to the noninverting input of a comparator that compares the error voltage with a sawtooth signal at its inverting input. The charging and discharging of a capacitor C c via a switching transistor Q st driven by a fixed-rate clock pulse generates this positive-going sawtooth signal. The frequency of this fixed-rate clock pulse determines the switching frequency of the converter. To achieve a linear positive-going slope, it is assumed that the time constant R C C C is much larger than the switching period. The clock pulse should be short, but sufficient to discharge the capacitor C c through the switching transistor Q st . Due to the large gain of the comparator, its output will swing close to its positive supply rail when- ever the noninverting signal is higher than the inverting signal. The output of 164 Power-Switching Converters H PWN j 1 signal «— tott — * t, on T pwh H signal < ''off > > Figure 5.2 Fixed-frequency PWM scheme. the comparator is a PWM signal shown in Figure 5.3(b). The output is high whenever the error voltage is higher than the sawtooth signal. This PWM signal is then fed to a gate-drive circuitry that drives the switching transistor g s of the buck converter. The duty cycle is determined by the time between the reset of the sawtooth generator as the switching transistor Q sl switches on, and the intersection of the error voltage with the positive-going sawtooth signal. Consequently, the instantaneous duty cycle d can be approximated by: d = -Z; (5.3) where V p is the maximum amplitude of the sawtooth signal. A lower-than- desired output voltage produces a higher error voltage. This produces a longer on pulse, which, in turn, switches the switching transistor Q st for a longer duration and results in an increased output voltage. The feedback network, Z t and Z 2 , of the error amplifier helps to stabilize and shape the frequency response of the switching converter (see Chapter 6). The average output voltage, K a , of a buck converter in a closed loop configuration employing the PWM control scheme is given by V a = dV B = (D + d)V s = DV S + dV s . (5.4) The average output voltage, V a , therefore contains a steady-state value DV S and a modulated value dV s . The modulated duty cycle, d, compensates the Control Schemes of Switching Converters 165 1IT $Di» + I«1 T c 2 £h l v a Gate Drive Circuitry PWM out Comparator Re V„» «r CLOCK »- V e A -«v^ M Error Amplifier Sawtooth signal V = — — — s p R^ + R 2 (a) PWM. Sawtooth CLOCK 1/«, 2IL (b) -* f Figure 5.3 (a) A fixed-frequency PWM controller for a buck converter, (b) Switching waveforms for the fixed-frequency PWM controller. ■m ]66 Power-Switching Converters output voltage for either load or input voltage variations. The value of d will be positive when the instantaneous output voltage is less than the desired output voltage, and negative when the instantaneous output voltage 1S higher than the desired output voltage. The DC open-loop gam is cm ^-^l-ML^^L (5.5) where K = (VJV^, and V a ' is the open-loop input voltage to the error amplifier and K is the DC gain of the error amplifier. The PWM controller can be implemented using either a combination of discrete components and integrated circuits or just integrated circuits. An implementation of a voltage-mode PWM controller using a combinationof discrete components and integrated circuits is shown in Figure 5.4. The NE555 timer in its astable mode generates an asymmetnc square-wave output at a fixed frequency. The capacitor C, differentiates this square wave into a sawtooth waveform with its slope determined by the time constant *,C, at the base of Qi. assuming that the phototransistor is not conducting. The resistor R 2 and the phototransistor m the optoisolator modulate the sawtooth waveform by changing its time constant from R x C, to R'C U thereby changing the slope of the sawtooth waveform. R is the parallel combination of *,, R 2 and the phototransistor. The normally con- ductive transistor, Q u is switched off when the negative-going sawtooth signal is above an emitter-base drop compared to its emitter voltage. The inverter Q 2 inverts the negative-going pulse at the collector of ft- Thi* produces a positive-going pulse at its collector. This positive-going pulse switches on Q 3 , the upper transistor of the output totem-pole, which m turn switches on the switching transistor Q 5 of the boost converter. The out- put voltage of the boost converter is regulated by comparing its sampled output voltage with a fixed reference voltage, F ref . The increase m the output voltage, due to either line (i.e., input voltage) or load variations, is detected by the error amplifier that drives the photodiode of the optocoupler Q op , by modulating its light intensity. Consequently, the negative-going pulse at the base of Q, attains a larger negative slope since the effective time constant 7TC, is smaller, causing Q„ Qi, and Q 4 to be switched on for a longer duration, while transistors Q 3 and Q 5 are switched on for a shorter durat ion. Therefore, the output voltage decreases. Thus, the pulse width applied to the switching transistor Q 5 is modulated according to load and line variations, stabilizing the output voltage of the boost converter. The schematic of an integrated circuit PWM controller is shown in Figure 5.5(a). The error amplifier compares the sampled feedback voltage from the output of a switching converter with a fixed reference voltage, K ref . Control Schemes of Switching Converters 167 Wr- it -Wr- it -Wir- -&- q"S t± ■*-+ Y - 1 - h- -AWr Y -> Ul < o o as 1 "^ -VA BU o 7"^ IE - J WV- H> tt -VAr- 4> ■* r>- id a: I tyWr- j| CM — Wr-* H> o HI- H> ft S =3 \— CD w C i T3 < iri a> 168 Power-Switching Converters Error amplifier V rel o Feedback signal Oscillator output . / // "~\/ I /' il V / Comparator output V c FIFO FIFO Base of O, Base of Q^ n (b) Figure 5.5 (a) An integrated-circuit PWM controller, (b) Switching waveforms of the integrated-circuit PWM controller. W Control Schemes of Switching Converters 169 The error signal is amplified and fed into the inverting input of a compara- tor. The noninverting input of the comparator accepts a linear-slope saw- tooth signal generated by a fixed frequency sawtooth oscillator. The output from the sawtooth oscillator is also used to toggle a trailing-edge-triggered flip-flop that produces square wave outputs Q and Q. The output of the comparator is high only whenever the sawtooth signal is higher than the error signal. The comparator PWM signal output is used to drive the AND gates, enabling each output only when both inputs to the gate are "high." The result is a variable duty cycle pulse train at the bases of the two uncommitted collector-emitter switching transistors Q x and Q 2 . The switch- ing waveforms for the integrated PWM controller are shown in Figure 5.5(b). 5.2.2 Current-Mode PWM Scheme In the current-mode or current-injected PWM scheme, the duty cycle of the switching converter is determined by the time at which the inductor current reaches a threshold value determined by the reference control signal. The current-mode PWM scheme has several advantages over the conventional voltage-mode PWM scheme [1,2]. First, since the switching transistor is switched off when the inductor current reaches the control signal level, failure due to excessive switch current can be prevented by simply limiting the maximum value of the control signal. Second, several switching con- verters can be operated in parallel without a load-sharing problem because all the switching converters receive the same PWM control signal from the feedback circuit and they carry the same current. During current-mode conversion, the average inductor current follows a reference voltage. As such, the inductor acts as a current source (CS). Thus, the output filter behaves as a voltage-controlled current source that supplies the output capacitor and the load, thereby reducing the order of the system by one. This simplifies its feedback compensation considerably. The major drawback of the current-mode PWM scheme is its instabil- ity. An oscillation generally occurs whenever the duty cycle exceeds 50%, regardless of the type of switching converter. However, this instability can be eliminated by the addition of a cyclic artificial ramp either to the sample of the inductor current or to the voltage control signal [3]. Discrete modeling can also be used to stabilize the loop [4]. Figure 5.6(a) shows a fixed-frequency current-mode PWM boost con- verter. It contains two feedback loops, an outer one which senses the output voltage and delivers a control signal to an inner loop which senses the current flowing through the switching transistor and keeps the output volt- age constant on a pulse-by-pulse basis. For a given cycle of operation, the 770 Power-Switching Converters turn-on of the switching transistor is coincident with the clock pulse and the turn-off is coincident with the time that the analog voltage of the switch current (coincident with the inductor current) intercepts the error voltage as shown in Figure 5.6(b). Clock X Comparator Error amplifier (a) PWM signal i ; i r i ! 27 (b) 3T Figure 5.6 (a) A boost converter implemented with a fixed-frequency current- mode PWM controller, (b) Fixed-frequency current-mode PWM controller wave- forms. pF Control Schemes of Switching Converters 171 5.2.2. 1 Instability for D > 50% When the duty cycle is greater than 50%, the inductor current shows subharmonic oscillations corresponding to the proportional current-mode control [5]. Figure 5.7 depicts the inductor current waveform, 7 L , of a cur- rent-mode converter being controlled by an error voltage V e . As can be seen in Figure 5.7, the instability can be initiated when the system is excited with small perturbations in the inductor current. Assume that the inductor current is perturbed by an amount A/„ at the beginning of the switching period, it can be seen that if the duty cycle is greater than 50%, then the perturbation A/, for the following period is greater. This trend keeps evolving, producing the above- mentioned instability. If the duty cycle is smaller than 50%, the perturbation is A) DUTY CYCLE < 0.5 INDUCTOR CURRENT A/ B) DUTY CYCLE > 0.5 A/ n COMPENSATION SLOPE C) DUTY CYCLE > 0.5 WITH SLOPE COMPENSATION Figure 5.7 Current-mode control instability. U2 Power-Switching Converters attenuated in the successive periods until it disappears. In this case, the system is stable. Mathematically this can be stated as 5.2.2.2 Compensation with External Ramp By introducing a linear ramp of slope -m, as shown in Figure 5.7(c), the instability can be compensated. Note that this slope may either be added to the current waveform, or subtracted from the error voltage. The compen- sating slope can be introduced in Equation (5.6) giving: A/, If _A, f!S±SY (5.7) m>--m 2 < 5 - 8 ) then A/, < A/ c , and the effect of the perturbation vanishes. Therefore, to guarantee the stability of the current loop, the slope of the compensation ramp must be greater than one-half of the down slope of the current waveform. For the buck converter of Figure 5.8, m 2 is a constant equal to (VJL) R*. The magnitude of the compensating waveform, A, should be chosen such that A > TR^ (5-9) to ensure its stability above a 50% duty cycle. It has been shown in Ref. [5], and is easily verified from Equation (5.7), that by choosing the slope com- pensation m equals -m 2 , a critically damped transient response is obtained. This allows the current to stabilize in exactly one cycle as illustrated in Figure 5.9. If an external voltage control loop is added, then it has also to be compensated to achieve the desired transient response. 5.3 HYSTERESIS CONTROL: SWITCHING CURRENT SOURCE In this control strategy, the main switch is switched on when the inductor current goes below a certain value, and it is switched off when the inductor m Control Schemes of Switching Converters 173 SLOPE . COMPENSATION J, SWITCH CURRENT Figure 5.8 A current-mode controlled buck regulator with slope compensation. Figure 5.9 Slope compensation m equals — m 2 . current goes above a specified maximum value. Thus, the amplitude of the current becomes bounded between these two limits. Hysteresis control finds its main application in power inverters, motor drives, and power factor correc- tion circuits; nevertheless, it can be used to control a switching current source. m 174 Power-Switching Converters The natural way to implement a regulated switching current source is to sample its output current and compare this value with a reference signal to close the regulator loop. A switching current source should have large output impedance. When the feedback loop is closed, this output impedance will become even larger. A switching current source usually has an inductor at its output. A basic switching current source using a hysteresis control is shown in Figure 5.10. Figure 5.11 shows ihe output current of the current source using a hysteresis control. The desired DC current value is represented by IM = 1 A; while the maximum and minimum current values are IPN and JVN, respect- ively. A load transition occurs at r = 5 msec. Notice that the frequency of the current waveform changes at the load transition, while their maximum PARAMETERS: Figure 5.10 Switching current source with hysteresis control. 1.2V: 1.0V 0.8V 0s 2msec 8msec * V(H_Conlrol:IL) Figure 5.11 Hysteresis control waveforms 4msec 6msec Time • V(H_Control:ILP) ' V(H_Control:ILP) 10msec Control Schemes of Switching Converters 175 and minimum values remain unchanged. The width of the hysteresis band sets the maximum operating frequency; therefore, the narrower the band, the higher the switching frequency. By an appropriate choice of the hysteresis band, the current ripple can be made triangular. If the band is too wide, the current ripple follows the exponential charge-discharge law of an LR circuit. The main disadvantage of the hysteresis control is the variable switching frequency, which makes EMI a more challenging problem to deal with. 5.3.1 Steady-Slate Analysis During ton Figure 5.12 displays the equivalent circuit of the switching current source during f n- The voltage across the inductor is v L d/ Ar / n (5.10) Then, tor, = L- Ai (5-11) v c -v - For a small hysteresis band, the output current can be considered constant, then V = 1 R, (5-»2) and ton = L- _Aj (5.13) ' on ~V C -I R' During t ofT , the left end of the inductor is grounded and the energy stored in the inductor keeps the current flowing in the same direction, as shown in Figure 5.13, + V L - I- 'o + fcc== EI R > [ 1 Figure 5.1 2 Equivalent circuit during f n 776 Power-Switching Converters + L - 'o Ft * Figure 5.13 Equivalent circuit during i ofr . V L is given by At Ar t n Then, t ot f becomes A/ Ai 'off = L— = L-r-^, V since T — t on + f fr, then r = LA ''Gc^ + ^)- (5-14) (5.15) (5-16) (5-17) The switching period versus the load resistance is shown in Figure 5.14. When the load changes, its switching frequency automatically adjusts to maintain the output current within the bounds. 3 4 5 6 Load resistance (Ohm) Figure 5.14 Switching period versus load resistance. Control Schemes of Switching Converters 177 5.4 COMMERCIAL INTEGRATED CIRCUIT CONTROLLERS 5.4.1 Fixed-Frequency Voltage-Mode SG3524 Controller [6] The SG3524, originally introduced by Silicon General Corporation, is the first commercially available fixed-frequency voltage-mode integrated circuit PWM control chip. A functional block diagram of the SG3524 is shown m Figure 5.15. A programmable sawtooth oscillator generates a 3.5- V saw- tooth waveform K st with a base DC voltage of about 0.5 V. The period of the sawtooth waveform T = R x C t /(1 .15) is set by external timing-resistor R t and timing-capacitor C t at pins 6 and 7, respectively. The timing-resistor R t establishes a constant charging current for C t that result in a linear voltage ramp at pin 7, which is fed to the voltage comparator. An error amplifier compares the sampled output voltage (pin 1) with a fixed reference voltage V K{ (pin 2) and produces an error voltage V e at pin 9. The high impedance at the output of the error amplifier (pin 9) presents some diffi- culties in the use of the conventional feedback compensation scheme for this error amplifier. A current-limit comparator compares the voltage propor- tional to the output current to a fixed reference voltage of 200 mV. Oscillator -^ output A rial Reference regulator +5 V to all inte circuitry 16 i Compensation ©■ Noninverting input o- Inverting input o- Shutdown o- Figure 5.15 Functional block diagram of the SG3524 PWM controller. ([6], Reprinted by permission of Texas Instruments.) 178 Power-Switching Converters Its purpose is to shut down the output transistors should an overcurrent situation arises, when the sample of the output current is higher than 200 mV. The output of the error amplifier is compared to the sawtooth K s , in a voltage comparator. Since the sawtooth K st is fed to the nomnverting input and the error voltage K e is fed to the inverting input, the comparator output is high only whenever the sawtooth signal voltage is higher than the error signal, as shown in Figure 5.16. Thus, the comparator output is a pulse 3.5 V 0.5 V Sawtooth \ -* t II DJL. o * ->• 1 o i -> t Vbo, t "BO, ' ■ Figure 5.1 6 Switching waveforms of the SG3524 controller. Control Schemes of Switching Converters 179 with a width corresponding to the time while the sawtooth voltage is higher than the error voltage. The resulting trailing-edge modulated pulse is then steered to the appropriate output transistor by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to assure that both the output transistors are never switched on simultaneously during the transition times, otherwise a catastrophic "shoot through," resulting in overcurrent damage to the transistors may occur. The SG3524 is designed for push-pull switching converters which have a switching frequency half that of the oscillator. The output transistors may also be connected in parallel for single-ended switching converters in which the switching frequency is the same as the oscillator frequency. Example 5.1. Design a pulse-width modulator using the SG3524 for a buck converter with an input voltage of 10V and an average output voltage of 5 V. The switching frequency is 1 kHz. The values for the output inductor and filter capacitor are 45 mH and 62.5 p.F, respectively. Solution. The switching frequency of the SG3524 is given as r 1-15 ,, IT * = ^cT lkHz - Hence, if a C t of 0.1 jjlF is chosen, then *, = ^=n-5ka The required steady-state duty cycle is 50%. Since the sawtooth signal of the SG3524 increases from 0.7 to 3.5 V, the required error voltage is (V p - V m ) ' or V e = 1.4 +V m = 2.1V. From operational amplifier theory, V e =V ref -^(V sp -V ie r). 750 Power-Switching Converters Assuming a reference voltage of 2.5 V and unity gain with R t = R 2 = lOOkft, the sampling voltage, K^, is ^-^(^-n) + ^r-^|(2.5-2.1) + 2 .5 = 2.9V. %< The sampling network can now be designed. Using the voltage divider rule, Rs2 KP Rsl+Rs2 V a , or 5R s2 = 2.9(* sl + i?s2). If R st is chosen to be 1 k£2, then R s2 is equal to 1.38 kH. Figure 5.17 shows the SG3524 PWM for the buck converter. 5.4.2 Variable-Frequency Voltage-Mode TL497 Controller [7] The Texas Instruments' TL497 is a fixed on time variable-frequency voltage- mode PWM controller. Its functional block diagram is shown in Figure 5.18. The on time of this controller is determined by an external capacitor C, V IN = 10V q=iouF -tt- I vw -=fc- 11.5K — VW 100 H ■ J WV- 100 K -VW- 0,100 K .R 2 -100 K 7 £ 6 16 2 1 12 13 11 14 SG3524 ± 0.001 uF X >47K to 45 mH I45mH T Dfw 4= I' C 62.5 uF -oV a = 5V Hs1 1 K "s2 1.4 K Figure 5.17 Circuit schematic of the SG3524 PWM in Example 5.1. ?r Control Schemes of Switching Converters 181 BASE (11) BASE {12) DRIVE — — CURUM SENS FREQ CONT INHIBIT (13) (3) (2) COMP (1) INPUT SUBSTRATE CATHODE W (6) CURRENT LIMIT SENSE 1.2V REF FC^i o s c L L A T O R -*J- (10) (8) (7) COL OUT EMIT OUT ANODE Figure 5.18 Functional block diagram of the TL497 controller. ([7], Reprinted by permission of Texas Instruments.) connected between the frequency-control pin 3 and ground. The timing- capacitor is charged by an on-chip constant-current source to a predeter- jnined threshold. The on time varies from 19 |xs for a C, of 200 pF to 180 |xs for a C t of 2000 pF. A comparator compares the feedback voltage at pin 1 with the internal fixed reference voltage of 1.2 V. The oscillator is enabled only when the feedback voltage is below 1.2 V. The uncommitted collector- emitter output transistor is switched on during the charging of the timing capacitor as shown in Figure 5.19. The oscillator is disabled whenever the =feedback voltage is higher than 1.2 V. Thus, the off time and the switching frequency are varied according to the duration of the feedback voltage above 1.2 V. A programmable current-limit circuit protects the output transistor against excessive peak current. It is activated when 0.7 V is developed across the sense resistor connected between pin 13 and the supply voltage. An inhibit input (pin 2) is available for external gating. The controller is switched off when the inhibit input is high. 5.4.3 Fixed-Frequency Current-Mode UC3842 PWM Controller [8,9] The Unitrode's UC3842 is the first commercially available fixed-frequency current-mode PWM controller. Figure 5.20 shows the functional block diagram of the UC3842. The feedback voltage Vn, (pin 2) is compared with an internal fixed reference voltage of 2.5 V in an error amplifier. The output of the error amplifier (pin 1) is available for external frequency Power-Switching Converters Figure 5.1 9 Switching waveforms of the TL497 controller. compensation. The error voltage is fed to the inverting input of the current- sense comparator via a voltage level shifter, while the sample of the inductor current is fed to the noninverting input of this comparator. This constitutes the inner current feedback loop of the current-mode controller. The on time is determined by both the voltage-sensmg error amplifier output V c , and the current-sense comparator, which compares the error voltage K e with the top of a ramp-on-a-step analog voltage from an external current sensing resistor. The comparator output is high only when the voltage error signal is higher than the sample of the inductor current. The UC3842 also includes an under-voltage-lockout feature that will only enable the controller if the supply voltage is above 16V with a 6V hyster- esis, i.e., it will pull in when the supply voltage is 16 V and drop out when the supply voltage drops to about 10 V. Current sensing and limiting. The UC3842 current sense input is configured as shown in Figure 5.21. Current-to-voltage conversion is per- Control Schemes of Switching Converters 183 B 3 -y^Hi- AA > s .> to i cS 1 * Q A O W O DC ccs UJ < 5? 3 o O o o o 6 I- Hi Z CO ui z EC LU cr co o B o o cu oo m <_> 3 s 35 O o 3 c o 3 in 3 Ll. 184 Power-Switching Converters ERROR J\MP 2.R -W — W — WV CURRENT SENSE COMPARATOR Figure 5.21 UC3842 current sensing. formed externally using a ground-referenced resistor R s . Under normal operation, the peak voltage across R s is determined by the error amplifier according to the following relation: h = ' 1.4 V 3* s (5.18) where V c is the control voltage and is equal to the output voltage of the error amplifier. For purposes of small-signal analysis, the control-to-sensed-current gain is: v c 3R S (5.19) When the sensing current is flowing through a switching transistor, a large current spike at its leading edge is always present. This is due to the reverse recovery of the diode or the interwinding capacitance present in the power transformer, or both. If this transient is not attenuated, the output pulse may be prematurely terminated. A simple RC filter as shown in Figure 5.21 is usually sufficient to suppress this spike. The RC time constant should be approximately equal to the duration of the current spike that usually lasts for a few hundred nanoseconds. The inverting input to the UC3842 current-sense comparator is intern- ally clamped to 1 V. Current limiting occurs if the voltage at pin 3 reaches this threshold value, i.e., the current limit is defined by: IV Rs' (5.20) Control Schemes of Switching Converters 185 Figure 5.22 Error amplifier configuration. Error amplifier. The error amplifier (E/A) configuration is shown in Figure 5.22. The noninverting input is not brought out to a pin, but is internally biased to 2.5 V ± 2%. The output of the error amplifier is available at pin 1 for external compensation, allowing the user to choose the desired closed-loop frequency response of the switching converter. Fig- ure 5.23 shows a typical application for the UC3842 family in an off-line flyback switching power supply. The detailed design of this off-line power supply will be presented in Chapter 10. 5.4.4 TinySwitch-li Family of Low Power Off-Line Switchers [10] In the TinySwitch-II family, a 700 V power MOSFET, oscillator, high voltage switched current source, current limit, and thermal shutdown circuitry are integrated to yield a controller with four effective pins, namely "Drain," "Source," "Enable," and "Bypass." In the normal operation of this device, a heat sink is not required. Unlike conventional PWM controllers, TinySwitch- II uses a simple ON/OFF control to regulate the output voltage. Figure 5.24 shows the functional block diagram along with some of its important features. The start-up and operating power are derived directly from the voltage on the "Drain" pin, eliminating the need for a bias winding and associated circuitry. In addition, the TinySwitch-II devices incorporate auto-restart, line under- ' voltage sense, and frequency jittering. The design also minimizes audio fre- quency components to practically eliminate audible noise with standard taped-varnished transformer construction. The auto-restart circuit limits the output power during fault conditions, such as output short circuit or open loop. 186 Power-Switching Converters o±12VCOM Figure 5.23 Off-line flyback regulator. Enable under- (EN/UV) Z. Leading edge blanking Source (S) Figure 5.24 TinySwitch-11 Functional block diagram. ([10], Reprinted by permis- sion of Power Integrations, Inc.) An optional line sense resistor externally programs a line under- voltage threshold, which eliminates power down glitches caused by the slow discharge of input storage capacitors in applications such as standby supplies. The operating frequency of 132 kHz is jittered to significantly reduce both the quasi-peak and average EMI, minimizing filtering cost. TinySwitch-II devices operate in the current limit mode. When enabled, the oscillator turns the power MOSFET on at the beginning of Control Schemes of Switching Converters 187 each cycle. The MOSFET is turned off when the current ramps up to the current limit or when the DCMAX limit is reached. Since the highest current limit level and frequency of the TinySwitch-II design are constant, the power delivered to the load is proportional to the primary inductance of the transformer and peak primary current squared. Hence, designing the supply involves calculating the primary inductance of the transformer for the maximum output power required. If the TinySwitch-II is appropriately chosen for the power level, the current in the calculated inductance will ramp up to current limit before the DCMAX limit is reached. Figure 5.25 shows a typical application of the TinySwitch, implementing a universal power supply, where the input AC voltage can range from 85 to 265 V. 5.5 CONTROL SCHEMES FOR RESONANT CONVERTERS The output of the resonant converter is regulated by changing its switching frequency. As in the conventional converters, the output voltage is first compared with a fixed reference voltage in an error amplifier. The output of the error amplifier determines the frequency of the output waveform of a voltage-control-oscillator (VCO). This VCO controller can be implemented using a combination either of digital-analog integrated circuits or by a microprocessor. A circuit schematic of a digital-analog implementation of this VCO controller for a push-pull resonant converter is shown in Figure 5.26. It consists of a CD4046 digital phase-locked-loop, a CD4013 D-flip- flop, a CD4528 retriggerable-resetable monostable multivibrator, a CD4050 hex buffer, and two CD4081 AND gates. The CD4046 generates switching pulses of varying frequencies, v y (t), according to the error voltage, v T (/), Figure 5.25 TinySwitch typical standby application. (From TNY 264/266-268 TinySwitch-II. Family data sheets, Power Integrations, Inc., April 2003. With permission.) 188 Power-Switching Converters ; -2.SK ;:S1 K "„,<<> 5.1 K J j/i/v — »v Figure 5.26 Circuit schematic of a digital-analog integrated circuit implementa- tion of a VCO for push-pull resonant converter. from the error amplifier, as shown in Figure 5.27. These variable-frequency pulses are fed to the inputs of the CD4013 D-FF and the CD4528 mono- stable multivibrator. The CD4013 D-FF generates an out-of-phase signal to yield the out-of-phase signals Q and Q, necessary to drive the push-pull converter topology. The pulse-width of these pulses is controlled by the combination of the CD4528 and CD4011 through the adjustment of the 5-kfl potentiometer, connected to pin 2 of the CD4528 multivibrator. The CD4050 hex buffer provides the drive capability to the gate drive circuitry and usually consists of a totem-pole configuration for fast switching in power MOSFET output transistors. Current-mode control eliminates the need for a voltage-controlled- oscillator in some quasi-resonant converters [11]. This control scheme also increases the noise immunity of the quasi-resonant converter since the function of the voltage-controlled oscillator is now replaced by a simple voltage comparator whose operation is far less noise sensitive. Figure 5.28 shows a circuit schematic of a direct-inductor current sensing implementa- tion of a current-mode control for a quasi-resonant buck converter. The error amplifier compares the sampled output voltage, K a ', with a fixed reference voltage K ref . The output of the error amplifier is then compared Control Schemes of Switching Converters 189 VolW v o2 <0 v/O Vx(') n n n n n n n n . n n n n n n n a -M T* ►»" nnnnnnnnnn -M X>1<- Figure 5.27 Waveforms for the VCO controller. — < T-, >*- v s Q i c, in -e Logic / gate drive Circuit ±C„ El, ^a -«V re rror Comparator - Amplifier Figure 5.28 A current-mode-controlled quasi-resonant buck converter. jpQ Power-Switching Converters with the sample of the output inductor current, v iL , in a voltage comparator. The output of the comparator is then used to provide constant on time pulses to the switching transistor Q s via a combination of logic and dnve circuitry. The switching transistor Q s is switched on when the down-slope of the sample of the output inductor current intersects the error voltage as shown in Figure 5.27. 5.5.1 Off-Line Controllers for Resonant Converters Half-bridge quasi-resonant controllers are available commercially for off-line switching converter applications. Their main applications are in universal power supplies for TVs and monitors, battery chargers, power supplies for tele- communications equipment and car radios, and high-voltage power supplies. 5.5. 1. 1 L6598 Operation [12, 13] The STMicroelectronics' L6598 is designed for applications based on half-bridge topology, using a 50% duty cycle at variable frequency. In this type of switching converter, control of the output parameters will be accom- plished by changing the switching frequency. Figure 5.29 shows the functional block diagram for the L6598 controller. This controller has an under-voltage lock-out (UVLO) feature. Below the UVLO threshold, both the high- and low-side drivers for the external power MOSFETs remain off. As the supply voltage is beyond the UVLO threshold, the circuit is operational. The low side driver is active during the first half switching period, fully charging the bootstrap capacitor. One salient feature is that the integrated bootstrap function does not require an external diode to charge the bootstrap capacitor. By choosing the appropriate biasing using R fmin and Rfstan, one can define the minimum and maximum frequency operation limits of the current controlled oscillator. The device has a soft start function with a delay capacitor, Css, which controls the time for the soft start. At start up, the frequency is set to the maximum value (F^J and will gradually decrease to the desired operating frequency. The oscillator controls the power stage circuit from the low and high side gate drivers that are connected to the external power MOSFETs. The closed-loop frequency is controlled by the value of R rmin . The high current carrying capability of the high- and low-side drivers (typically 450 mA source and 250 mA sink), ensures fast switching transitions for the external power MOSFETs. At the same time, the internal logic ensures a typical dead time of 300 ns between the turn on and off of both switches. A typical application for the L6598 is the multiresonant zero-current- switching (ZCS) converter for a high-end TV power supply as shown m Figure 5.30. Its simplified schematic is shown Figure 5.31. A half-bridge resonant topology is chosen due to its small size, high efficiency, and low Control Schemes of Switching Converters 191 Cbl VS OPOUT OPIN- OP1N + 'f f «f OPAMP_ J VREF I ,te,art ^,VREF BOOTSTRAP DRIVER UV DETECTION DEAD TIME llC CONTROL LOGIC HVG DRIVER DRIVING LOGIC LEVEL SHIFTER LVG DRIVER < ®'„ Vlhe l Vthe2 H. V. BUS Hfc5 Vr^ HVG.J OUT -^ "T-c 1- Figure 5.29 Block diagram of the L6598. ([12], Reprinted by permission of STMicroelectronics.) noise operation. The operating waveforms are shown in Figure 5.32. This half-bridge converter consists of the power MOSFETs, Q x and Q 2 , the resonant inductor L x , the magnetizing inductance of the transformer L 2 , the resonant capacitors C, and C 2 , rectifier diodes £>, and D 2 , and the output capacitor C out . G QX and Cqz are the parasitic capacitors of the 2, and Q 2 , respectively. D QX and Dqz are the parasitic reverse diodes of Q x and Q 2 , respectively. The two power MOSFETs, g, and Q 2 , are switched on alterna- tively at near 50% duty cycle. This circuit has three modes of operation. Mode 1. In this mode, the series resonance of the circuit formed by L, and C x + C 2 , supplies power to the load. Mode 2. Resonance occurs between L, + La and C x + C 2 , without supplying power to the load. Mode 3. In this mode of operation, resonance occurs between C QX + Cq2, L x + L 2 and C, + C 2 , allowing the zero-voltage switching of the MOSFET. There are eight operating intervals as shown in Figure 5.31. t - t x . During this time interval, a reverse current flows in Q x through the parasitic diode, D QX . Q 2 is switched off. The initial value of the resonant current between L x and C, + C 2 at t is -I 2 , which coincides with the current flowing through L 2 . The current flowing through L 2 increases at the rate ol lip 192 Power-Switching Converters (52 tf 2£ -V* <?S tf «R y iQ i ■*vjvA^»»j n+ F-C CM n 1L ,5 ^rW— I 1/3 C o -*-fca 4 I -WV — rF^ c? CNJO f-HI- cS"S -Vft- r> f ^ — ■VW-»-|l- -wvi-Hi-^- iC BJ Hi 5 § -w- •wv- * ofS L„--|l>-S: o r i-.co EC (d a °«fK ?s o CO c5" ui r 1 OIL <5Z ccS •hi— fy <5"5 c o CS e o CO 0> OS co in 9» u. Control Schemes of Switching Converters + BUS 193 Figure 5.31 Typical application of the L6598. ([13], Reprinted by permission of STMicroelectronics.) nV JLa, where n = N x /N 2 and N 2 = N 3 . At t , C Q1 is completely dis- charged; therefore, the voltage across Q\ becomes zero and zero-voltage switching (ZVS) is achieved. The voltage across C 2 decreases while C 2 is discharged. /, - t 2 . During this time interval, £?, is switched on and Q 2 is switched off. The resonant current flows through 0, in the positive direction. The resonant current increases sinusoidally and reaches the maximum value, then deceases until it coincides with the current in L 2 at t 2 . The difference between the resonant current and the current in Z- 2 flows through the primary winding N x of the transformer (see Figure 5.30). In this interval, power is supplied to the load. t 2 - t 3 . During this time interval, Q x remains on and Q 2 remains off. The current /, flowing through L x coincides with the current in L 2 at t 2 . No current flows through the secondary winding of the transformer. In this mode, L\ + L 2 and C\ + C 2 resonate. t 3 - t 4 . This interval starts when. Q t switches off at t 3 . Both <2i and Q 2 are off. The charge stored in the parasitic capacitor C Q2 of Q 2 is discharged by means of the resonant current between L x + L 2 and C\ + C 2 . At the same time Cqi is charged. 194 Power-Switching Converters 16 18 17 O03IN1426 Figure 5.32 Switching waveforms. ([13], Reprinted by permission of STMicroe- lectronics.) U - t 5 . During this time interval, Q x remains off and the resonant current flows through the parasitic diode of Q 2 , D Qr At t 4 , C Ql is completely discharged and the voltage across Q 2 becomes zero, achieving the ZVS. The voltage of C 2 increases further. / 5 - t 6 . During this time interval, gi remains off and Q 2 is switched on. The resonant current flows through Q 2 in the opposite direction that was flowing during the time interval from t 4 to t 5 . The resonant current decreases sinusoidally and reaches the minimum value; then increases until it coincides with the current in L 2 at t 6 . The difference between the resonant current and the current in La flows through the primary winding iV, of the transformer. In this interval, power is supplied to the load. t6 _ f 7 . During this time interval Q x remains off and Q 2 remains on. The current -J 2 in Z., is equal to the current flowing through L 2 at t 6 . No current flows through the secondary winding of the transformer. In this mode, Li + L 2 and C\ + C 2 resonate. Control Schemes of Switching Converters ^5 t 7 - t z . During this time interval, Q 2 turns off at / 7 . Thus, gi and Q 2 are both switched off during this interval. The parasitic capacitor C Ql of Q 2 is charged by means of the resonant current that flows through L x + L 2 and C, + C 2 . At the same time, C Gl is discharged. At time t s , the circuit returns to the first mode and the cycle is repeated. A main feature of this resonant converter is the ZVS of the power MOSFETs. However, there are still turn-off switching losses, but they can be reduced by placing small snubber capacitors directly across the MOSFETs. Discharge resistors are not needed in the snubber, because the capacitor is not discharged by turning on the power MOSFET, but rather by turning off the opposite power MOSFET. The switching losses due to C oss and C r5S are also eliminated by the snubbers. The energy stored in the capacitors across the switching device is returned to the DC source through the opposite device when turned off. PROBLEMS 5.1. A pulse-width modulator is shown in Figure 5.33. Operational ampli- fiers for the error amplifier and the comparator are considered to be ideal. The minimum sawtooth signal is IV with a peak of 3 V and a frequency of 1kHz. Determine the error voltage, V e , of the error amplifier if the feedback voltage is 2 V and the reference voltage is 1.8 V. Sketch waveforms at the outputs of the AND gates for four switching periods. 5.2. Design a pulse-width modulator based on the SG3524 for the boost converter shown in Figure 2.1E-The input voltage, V s , is 9 V and the average output voltage, V a , is T2V. The switching frequency is 1 kHz. Component values for the boost converter are: C = 1 00 pF, L = 10 mH, andi? L =10n. 5.3. Design a 5-W continuous conduction mode flyback converter using the UC3842 current-mode controller. The line input voltage is 110 V at 60 Hz. The load requires an output voltage of 5 V + 50 mV at a load current of 1 A. 5.4. A solar cell panel provides the energy for a meteorological station that gathers data and sends them via an RF link. The terminal voltage of the solar cell depends on the energy from the photons impacting on its surface. Therefore, the available DC voltage across the solar panel fluctuates between 17 and 21 V-during the daylight hours (when the equipment is used). The electronic equipment requires a DC voltage of 5 V + 5%; as such voltage regulation is required at the load. The load 196 Power-Switching Converters Error Amplifier Figure 5.33 Pulse-width modulator for Problem 5.1. current may change from 300 mA to 1 A. Design a switching voltage regulator using the integrated circuit TL494 that would provide the appropriate voltage to the meteorological station. The regulator has to be designed to operate in the discontinuous mode. REFERENCES 1. 2. 4. 5. S. Cuk and R.D. Middlebrook, Advances in Switched-Mode Power Conversion, vol. 1, TESLAco, Pasadena, 1982, p. 169. S. P. Hsu, A. Brown, L. Rensink, R. Middlebrook, Modeling and analysis of switching DC-to-DC converters in constant-frequency current-programmed mode, Record of the IEEE PESC 79, 1979, pp. 284-301. C. W. Deisch, Simple switching control method changes power con- verter into a current source, IEEE Power Electronics Specialists Con- ference, 1978, pp. 135-147. C. C. Fang and E. H. Abed, Sampled-data modeling and analysis of the power stage of PWM dc-dc converters, Int. J.Electron., 88 (3), 347-369, 2001. Modeling, Analysis and Compensation of the Current-Mode Converter, Unitrode Applications Note U-97, Unitrode Corporation, 1995: Linear Circuits Data Book, Texas Instruments Inc., Dallas, TX, 1984, pp. 6-69. Linear Circuits Data Book, Texas Instruments Inc., Dallas, TX, 1984, pp. 6-119. Control Schemes of Switching Converters 197 8. Unitrode Data Book, Unitrode Corporation, Lexington, MA. 9. Unitrode, UC3842/3/4/5 Provides Low-Cost Current-Mode Control, Application Note U-100A, Texas Instruments, Inc., Dallas, TX, 1999. 10. TNY264/266-268 TinySwitch-II Family Data Sheets, Power Integra- tions, Inc., April 2003. 11. R. B. Ridley, F. C. Lee, V. Vorperian, Multi-loop control for quasi- resonant converters. PCIM, 13-21, July 1987. 12. U. Moriconi, L6598; Off-line Controller for Resonant Converters, Application note AN1673, STMicroelectronics, October 2003. 13. H. Ding. ZVS Resonant Converter for Consumer Application Using L6598 IC, Application note AN 1660, STMicroelectronics, September 2003. 14. Philips Semiconductors TEA 1610 Zero- Voltage-Switching Resonant Converter Controller, April 2001. Dynamic Analysis of Switching Converters 6.1 INTRODUCTION In the preceding chapters, analyses of switching converter topologies have so far been performed under the steady state condition. Predicting its dynamic characteristics has not been easy due to the complexity of the operation of the switching converter. The dynamic characteristic of the switching converter can be used to predict: (a) the margin of stability of the switching converter, (b) the input supply ripple rejection and the transient response due to input supply perturbation, (c) the output imped- ance and the transient response due to load perturbation, and (d) the compatibility with the input electromagnetic interference (EMI) filter [1]. Thus, dynamic or small-signal analysis of the switching converter enables designers to predict the dynamic performance of the switching converter to reduce prototyping cost and design cycle time. Generally, dynamic analysis can be either numerical or analytical. Numerical methods can be useful for computer simulations, but they cannot reveal basic relationships among circuit elements in the switching converter. Switching converters are 799 200 Power-Switching Converters nonlinear time-variant circuits. Nevertheless, it is possible to derive a continuous time-invariant linear model to represent a switching converter. Continuous-time models are easier to handle, but not very accurate. Since a switching converter is a sampled system, a discrete model gives a higher level of accuracy, and also models some aspects of the converter (like the instability in current-mode control) that are not covered by a continuous model. A discrete-time modeling technique, such as sampled data modeling [2,3] must be used for this last case, or when more accurate results are needed. This chapter is divided in two parts; the first part discusses continuous- time models for switching converters, while the second part presents a discrete-time model. In Part I, classical control techniques are used to analyze and stabilize closed-loop switching converters. A brief review of negative feed- back applied to electronic circuits is performed. The stability analysis is performed using Bode plots, and a compensator is calculated to shape the loop gain to a desired phase margin. Variations on the load are modeled as a small-signal current source at the output of the converter. The output impedance is calculated to evaluate the effect of the variations of the output current on the output voltage. Output impedance and load vari- ations are related to stability and transient response. The concept of audio susceptibility is introduced and the corresponding transfer function calcu- lated. After a review of linear system analysis using state-space representa- tion, the state-space averaging model developed by Middlebrook and Cuk [4] is introduced. The transfer function and loop compensations are calcu- lated using state-space representation. A method based on full-state feed- back is explained, which permits locating the closed-loop poles of the converter to achieve a desired dynamic response. This method is more precise than using the phase margin method. In Section 6.2.12, the need for an EMI filter is described and its influence on the converter stability is analyzed. Part II discusses the discrete-time modeling of switching converters. This modeling technique is more accurate than the continuous-time mod- eling and suitable for controller implementation using a DSP chip. After developing a discrete-time model, a full-state feedback technique is used to place the closed-loop poles to obtain a desired transient response. The use of additional dynamics permits achieving a zero steady-state error. Both voltage-mode and current-mode control schemes are discussed. Dynamic Analysis of Switching Converters 201 6.2 CONTINUOUS-TIME LINEAR MODELS 6.2.1 Switching Converter Analysis Using Classical Control Techniques Within certain limits, classical control techniques can be applied to switching converters. Different degrees of accuracy can be achieved depending on the model. A basic small-signal linear model of a switching converter is first introduced. 6.2. 1. 1 Basic Linear Model of the Open-Loop Switching Converter This model considers all the constitutive blocks of the switching con- verter as de-coupled blocks. Therefore, it is not applicable to all cases. Nevertheless, it provides a first insight to the calculation of the gain of each individual block. The block diagram and small-signal linear model for a switching converter are shown in Figure 6.1. The reference voltage, F ref , enters the pulse-width modulation (PWM) block to generate the nominal duty cycle, D, that drives the switches of the (a) V, el PWM ->i Switch LPF Load J_ w „ Load _L Figure 6.1 Linear model of a switching converter. 202 Power-Switching Converters power stage. Since this is a small-signal linear approximation of the switch- ing converter, no switching action takes place in the power stage. Instead, the output of the power stage is a modulated DC value, which is a function of D multiplied by the unregulated DC input voltage, V DC . This waveform enters the low-pass filter, allowing only the DC component and the low- frequency dynamics of the circuit to reach the load. A linear circuit approxi- mation of the switching converter is shown in Figure 6.1(b), where Z is the output impedance of the switching converter, Z L is the load impedance and K is the open-circuit gain. The DC output voltage is given by: Vo=-^rkV tsU (6-D where A: is a function of K DC that depends on the PWM modulator imple- mentation. Then, if Z L or K DC varies, it will be reflected in the output voltage. If V a needs to be bounded between certain limits, then a closed- loop controller is required. Various models for the constitutive blocks of the block diagram of the linear switching converter shown in Figure 6.1(a) are discussed in the following sections. 6.2. 1 .2 PWM Modulator Model 6.2.1.2.1 Voltage-mode control. The PWM modulator generates the duty cycle, D, by comparing a sawtooth (or triangular) signal to the reference voltage, V ret . For a voltage-mode constant-frequency PWM modu- lator, the sawtooth signal is applied to the inverting input while the K rrf is applied to the noninverting input of the error amplifier. The output of the comparator is high at the beginning of the switching period, and remains high until the ramp reaches the reference voltage and the output changes to a low level. The width of the output pulse is DT. The DC gain of the PWM modulator can be easily calculated from Figure 6.2 using a geometric method. Consider a sawtooth signal of period Tand amplitude V p , for the nominal reference voltage, F ref , the nominal duty cycle, D, is given by: Z> = 2k. (6.2) Yp When a perturbation on the reference voltage v ref is applied, it produces a variation on the duty cycle, d, which can be calculated by comparing the two shaded areas, yielding Dynamic Analysis of Switching Converters 203 Figure 6.2 Sensitivity of the duty cycle with respect to v ref . 6.2.1.2.2 Current-mode control. In current-mode control, the in- ductor current is compared with a reference current, J p , to determine the nominal duty cycle, D. At the beginning of each switching cycle, the inductor current increases linearly, until it reaches the amplitude set by l p . The switch driving the inductor is turned off and the current decreases linearly until the next switching cycle. The positive slope of the inductor current is given by dh = VL = I p ^h dt L D (6.4) where /, is the magnitude of the inductor current at the beginning of the switching cycle. Then, the nominal duty cycle is determined by D = (/ P - h)L (6.5) A linear expression for d can be found by approximating-the function with the linear terms of its Taylor series expansion. Thus, -, dd ~ dd . dd ~ (6.6) The sensitivities of Equation (6.6) are different for every switching converter. They are usually evaluated by a geometrical analysis, similar to the one performed in Figure 6.2. Example 6.1. Calculate the approximate linear expression of d for a cur- rent-mode buck converter operating in the continuous-conduction mode. 204 Power-Switching Converters Solution. The first term on the right-half hand of Equation (6.6) represents the sensitivity of the duty cycle as a function of the current through the inductor. Figure 6.3 shows the variation of the duty cycle due to a perturb- ation i L > on the inductor current at t = 0. If the input and output voltages are considered constant during t m , then the slope of the ramp corresponding to the inductor current does not change. There is only a vertical shift given by i L . The slope of the ramp in this interval is given by: V A -V C (6.7) An analysis of the figure shows that: i L = r(-dT) and solving: L d=- Therefore, (V d - V C )T IL- (6.8) (6.9) dd L di L ~ (V d -V C )T- (6.10) &r / ^xf\ ^^XxVw v.. / L (0) 'l 1 * t0 ^ g ^ r 'v. (D+d)T DT Figure 6.3 Variation of the duty cycle due to a perturbation in the inductor current. Dynamic Analysis of Switching Converters 205 The sensitivity of the duty cycle as a function of the voltage across the capacitor can be evaluated from Figure 6.4. A perturbation on the output voltage changes the slope of the inductor current waveform during t on . To obtain the expression for rfasa function of v c , the equations for the slopes corresponding to the nominal {r{) and perturbed (/) cases are analyzed. r, = (K d - V c )/L / = [F d -(K c +v c )]/Z.. Also, from the figure r, = M/DT r' =M/(D + d)T. Dividing r, by f, AI/DT (v d -v c yL r 1 M/{D + d)T [V* - (K c + *c)l/£ and solving for d yields: d = D \ \ \ [y d -v c - v c j (6.11) (6.12) (6.13) (6.14) (6-15) (6.16) A **$ )*■ -^ .-few 'p \ ^ pr ; A/ /^ „.-*' ■■■» -** **• DT {0*-d)T Figure 6.4~ Variation of the duty cycle due to a perturbation in the output voltage. 206 Power-Switching Converters Considering v c «: (V d - K c ) the following approximation can be obtained: = ' Vc [v^t}- Thus, 8d_ dv c \y d - v c \ (6-17) (6.18) The sensitivity of the duty cycle as a function of the control variable I p may be evaluated from Figure 6.5. The peak current through the inductor, 7 p , will be set by the control strategy. A perturbation on its value has the following effects on the nominal duty cycle: r where V A (6.19) (6.20) Then, * = h-±- T V d (6-21) \^^ j i :t DT (Ch.d)T Figure 6.5 Variation of the duty cycle due to a perturbation on the peak current. Dynamic Analysis of Switching Converters 207 Thus, (6.22) dd__}_ L 9/ p ~ T V d -V c 6.2. 1.3 Averaged Switching Converter Models 6.2.1.3.1 Averaged-switch model for voltage-mode control. Vor- perian [5] developed an averaged-switch model, which replaces the nonlinear switching action of the converter using a simple small-signal equivalent circuit. This model can be used for all two-switch PWM converters in either the continuous-conduction mode or discontinuous-conduction mode of op- eration. Figure 6.6 shows the three-terminal averaged switch model. The amplitudes of the two dependent sources are determined by the DC operat- ing conditions of the power stage. The voltage source, v t , is determined by the steady-state DC voltage across the active and passive terminals, and the duty cycle of the power stage; i.e., v,=-^. (6-23) The current source is determined by the steady-state DC current, /„ of the common terminal. U=hd. (6.24) Both dependent sources are controlled by the duty cycle modulation, d. The polarities and current directions must be consistent throughout the analysis. Figure 6.7 shows the small-signal models with an averaged switch for the buck and boost converters. Notice that the averaged switch replaces both the a (active) c (common) P (passive) Figure 6.6 Three-terminal averaged-switch models 208 Power-Switching Converters i "1 Avg swilch a c P r 't Avg switch (a) averaged buck converter. <<>> averaged boost converter. Figure 6.7 Examples of switching converters with an averaged switch. transistor and the diode. The common terminal is connected to the node where the transistor and the diode are connected together. The active ter- minal is the other end of the transistor and the passive terminal is the other end of the diode. The main advantage of this model is that once the switching devices have been replaced by the averaged switch model, linear circuit analysis techniques can be applied to analyze the circuit. Moreover, PSpice can be used to simulate the small-signal AC and transient behaviors of the con- verter. The library swit_rav.lib, included in PSpice, contains averaged-switch models for voltage-mode, current-mode, continuous-conduction and discon- tinuous-conduction modes of operation. The averaged switch model for the discontinuous conduction mode [5] is shown in Figure 6.8. The values of the parameters are given by: »=£. '-*£* *-*£* *- 2 £* *-£■ (6.25) Notice that the sources are controlled by the modulation of the duty cycle in both the continuous and discontinuous conduction models. There- fore, most averaged-switch components for circuit simulation program have a a w 'i oy '2 w '3 ^ 9o Figure 6.8 Small-signal averaged-switch model for the discontinuous mode. 209- Dynamic Analysis of Switching Converters fourth terminal to incorporate the duty cycle modulation. The PWM modu- lator has to be modeled on a separate block, as shown in Section 6.2.1.2. 6.2.1.3.2 Averaged-switch model for current-mode control. Ridley [6] expanded the voltage-mode averaged-switch model for current-mode control that is valid up to half the switching frequency. All the small-signal characteristics of current-mode control are predicted, including low- frequency effects and high-frequency subharmonic oscillation. This model can also be used for all switching converters using constant frequency, constant on-time, or constant off-time control [7]. The linearized continuous sampled data model is approximated by a second-order system as follows: iw.)=i+-^+4. (6 ' 26) where 6z = Zl (6.27) tr and -■5 v (6.28) where T s is the period of the compensating ramp. As shown in Figure 6.9, the power stage model remains the same as that in Figure 6.7, except that current-sensor and gain blocks have been added to represent the current feedback. The resistance R, is the linear gain ofithe current-sense network, and H e (s) models the sampling action of the current-mode control. With no current feedback, R-, and the gains k T and k T are zero. In this case, the model consists of only the voltage-mode control loop. Other parameters are: . -DT S R, ( y D\ (1-DfTsRj 1 (6 29) kf =— ETA 27' * r=_ 2L ' Fm -(S n + S c )T s > lb - y; where F m is the modulator gain, S n and S c are the slopes of the sensed-current ramp and the compensation ramp, respectively. Contrary to the averaged- switch model, the PWM modulator is included in this model. Therefore, the control input for Ridley's average model is the error voltage, v c . Other averaged models of the switching converters have been devel- oped, like the averaged-inductor model by Yaakov [8]. This model replaces the inductor and the switches by a block that models their average behavior. 270 Power-Switching Converters ■i POWER STAGE MODEL -► Q |^ »- H e {s) |^-[q|-^-' Figure 6.9 Small-signal model for current-mode control. (From Figure 5 of Ridley, R.B., A new continuous-time model for current-mode control, IEEE Trans. Power Electron., pp. 271-280, April 1991. With permission.) In contrast with the averaged-switch-based PSpice components, a different component is needed in PSpice for each averaged-inductor switching con- verter model. Chapters 9 and 10 include examples of the use of averaged models in PSpice simulations. 6.2. 1.4 Switch Losses The ON resistance of the MOSFET transistor will only affect the amp- litude of the square waveform applied to the low-pass filter, according to D R on , where D is the duty cycle and R oa is the on resistance of the switching device. The voltage drop across the diode may be modeled by an ideal voltage source in series with the passive terminal of the small-signal model circuit. 6.2.1.5 Switch Delay The time delay associated with the switch may play an important role in the evaluation of the phase margin. The time delay contribution to the phase margin is: phase (delay) = -360 x f dday x/,, (6-30) where f de i ay is the time delay in seconds and/, is the unity-gain crossover frequency. This phase delay must be added to the loop phase to determine a Dynamic Analysis of Switching Converters 211 more accurate phase margin. The phase delay degrades the phase margin because its sign is negative. 6.2. 1.6 Output Filter Model The output filter model can only be calculated separately for those switching converters where the switching devices cannot be merged into the output filter such as in a buck converter. For all the other topologies, the filter transfer function is affected by the switching action. Therefore, the switching converter transfer function is generally evaluated using an aver- aged model. The output filter of a buck converter is used as an example to evaluate the response of a second-order system. The frequency response of the out- put filter often dictates the required feedback compensation in a buck- switching converter. The output filter L C is essentially a second-order low-pass filter. The transfer function of this output filter can be derived by transforming the reactive components into their j-domain parameters, as shown in Figure 6.10. The output voltage V (s) is r ,, *o//(l/*C ) Vois) -sL + (R //{l/sC )) Vs(S) - The transfer function of the output filter is then V {s) (1/C L ) (6.31) (6.32) V s (s) si + {slC o Ro) + (\/L C o y It can be shown from feedback system theory [9] that the transfer function of a second-order system can be represented as ms) - S i + 2£<0 o s + a>l' (6.33) V (s) Figure 6.1 Output filter of a switching converter. 2J2 Power-Switching Converters where C is the (dimensionless) damping ratio and io is the natural frequency of the system. When f = 1 , the response is critically damped. When f < 1 , the response is underdamped. The response is increasing oscillatory as ( ap- proaches zero. When £ > 1, the response is overdamped. Comparing Equa- tion (6.33) to Equation (6.32), the damping ratio and natural frequency of the output filter are C = , * («4) 2Ry/(C /L ) and 1 y/L C (6.35) The magnitude and phase can be evaluated at any to using Equations (6.36) and (6.37), respectively: 201og|G(o,)| = -101o g n 1 - (^-) 2 ) +4(f£) J, (6-36) <!>(.,) = -tan-' «W"°> \. (6.37) ., / 2g(o>M,) " \ Vl-(«/«o)7" Figure 6.11 and Figure 6.12 show the magnitude and phase responses versus normalized frequency (i.e., (/7/ )) of the output filter for several values of the output resistance R . The magnitude response has a constant value up to the natural frequency f Q of the output filter. It then decreases linearly with a slope of -40dB/decade. As shown, the magnitude response is critically dampe d when th e output resistance, R , is equal to the characteristic imped- ance V (Z. /C ) o f the output filter. The response is und erdamped whenever Ro > ^/CWCo) and it is overdamped whenever R < ^/{L /C ). The phase transition becomes sharper as the response becomes more underdamped. The rapid phase shift with frequency is to be avoided in the second-order system, since this may lead to instability. In a practical switching converter, the equivalent-series-resistance (ESR) ifl the output capacitor must be taken into account in feedback compensation. Figure 6.13 shows the equivalent circuit of the output filter when considering the capacitor ESR. The corresponding transfer function of the output filter of the buck converter is Figure 6.1 1 Magnitude response of the output filter for several values of the output resistance R„. Figure 6.12 Phase response of the output filter for several values of the output resistance R a . 274 Power-Switching Converters Sto V s (s) sC a Figure 6.13 Output filter with a capacitor /J^. V (s) H{s)-- RoRcs s+V/CqRc) L {Ro + Rtst)? + ((L. + CvRoR^yUColK + *«)>* + (R<,/L C {R„ + R^)) .(6.38) Thus, the capacitor ESR, R^r, introduces a zero at / ES r = (MlirR^Co), when the capacitive impedance is equal to R^. The magnitude response of the output filter is modified by the presence of the ESR in the output capacitor, as shown in Figure 6.14. Figure 6.15 shows the phase response of the output filter as a function of R . The magnitude response before the / ESR is unaffected. Beyond/ E SR, the magnitude response decreases linearly at a slope equal to -20dB/decade. This is because after / ES r, the impedance contribution from the output capacitor C is increasingly small compared to R esl . As such, the output filter is now an RL rather than a LC circuit. The effect of the ESR in the output capacitor is to contribute with a phase angle equal to ta.rT x {fl /es R ). Hence, the phase lag of the output filter considering the capacitor ESR at any given frequency /is LC = tan ., ( iqf/fo) \ t3n -i ( j_\ Id - (///o))J UJ- While the magnitude response is 20 (6.39) log|G(a,)| = 101og(l + a,V)-101ogni-Q 2 ) + 4^) J. (640) where R L C (Ro + ^esr) (6-41) Dynamic Analysis of Switching Converters 215 fif„ Figure 6.14 Magnitude response of an output filter with a capacitor having a R csr for several values of the output resistance R . *=(fe +C °*»')T- T = Co-Resr- (6.42) (6.43) Example 6.2. The output filter of a buck converter shown in Figure (6.10) has an inductor of lmHanda capacitor of 100 \iF. Determine: (a) the corner frequency and (b) the load resistance R for a critically damped output response. Solution. (a) The corner frequency of the output filter is 1 1 /»=: = 503.3 Hz. 2-ayfUC 2iry/10- 3 {\00 x 10-") (b) For a critically damped output response, the load resistance is r= 1.58ft. jRd = 2YQ~2V" io- 3 100 x 10- 6 216 Power-Switching Converters -2a — >- -i-f-HtH —- h -40 £ -60 S -100 -160 - 0.001 Figure 6.1 5 Phase response of an output filter with a capacitor having a R^ for several values of the output resistance R . Example 6.3. The output filter of the buck converter shown in Figure 6. 1 3 has a capacitance of 200 p.F with an equivalent series resistance of 0.1 fl, an output inductor of 1 mH and a load resistor of 10ft, respectively. Determine (a) the corner frequency and (b) the^zero introduced by the R esT . Solution. (a) The corner frequency of the output filter is 1 1 /o = 2tryfL^C 2<nVl° -3 (200 x 10" 6 ) = 355.9 Hz. (b) The zero introduced by the R\st is 1 1 fsSR = 2irC 7?esr 2tt(200 x I0r«y0.\ 7.96 kHz. Example 6.4. The boost converter shown in Figure 2.10 has the following parameters: K in =10V, K o = 20V, / s =lkHz, Z-=10mH, C=100p.F, and R h = 20Cl. The reference voltage is 5 V. The converter operates in Dynamic Analysis of Switching Converters 2J7 the continuous-conduction mode under the voltage-mode. Using (a) the averaged-switch model, calculate the output-to-control transfer function and (b) MATLAB®, draw the Bode plot of the transfer function found in (a). Solution. (a) The nominal duty cycle can be calculated as 1 \-D — SH— % for the given input and output voltages, we have D = 0.5. The averaged-switch model of the boost converter is shown in Figure 6.16, where the switching devices have been replaced by their aver- aged model. The parameters for the averaged model are I c = -(1 - D)I = -(1 - Z>)^ and K ap = - V . The small-signal gain, (vjd), can be calculated using linear circuit analysis. The two mesh equations that include the transformer are v + V2 — ijsL = Solving for vi yields: {-■ Vl Kpd D — v„. Thus, v o + D(^--v o )-i 2 sL = 0. 7,-/2 Figure 6.16 Small-signal model of the boost converter. 218 The current i 2 is given by: Vq + Vapd — DVq Power-Switching Converters n = sL The currents i x and i 2 are related by the transformer ratio by r"i = Di 2 , h=-jj- Then, m The current flowing out of the passive terminal is given by *(£ i I) +4 »-«,(£ i i), ip = l'l - »2 + W = »1 I or z p = (1>-1)- Vo + Vapd - Dv sL + I c d. I c d The output voltage can be found RfsC •-^^H'"-)**^^ Replacing i p , the output voltage becomes sL ( R/sC \ \R + (\/sC)J (D - l)v V ap d(D - 1) (D - l)£>v [ 7 ^ J? $CK+1 sL sL sL Rearranging \sCR+\ , (1 -Z>) I>(1 - J>)1 _ - jVyiD-1) , J ■+■ sZ, xL .]= 3 [1 sL Dynamic Analysis of Switching Converters Solving for the output-to-control transfer function, yields: ((K ap (D-l)+/^L)AI.) 219 ~ d ~ {(sCR + l)/R) + ((1 - D)/sL) - {{D{\ - D))/sL) V ap {D-l) + sLI c s*LC + (sL/R) + (l-D)- D{\ - D) V av (D-\) + sLh s 2 LC + s(L/R) + (l-D) 2 ' Finally, we have V ap (D - I) + sLIc 'd (1 - D? [s*(LC/{\ - Df) + s(l/(r{\ - D?)) 4- l] The natural frequency and the damping factor are 1 LC (\-D) 2£ L . a» m L (\-D) L _ t _ (Z 1 ^ = R{l-D) 2 ^-~2R{\-Df- VLC 2R(\-Df V C2R{1-D) The PWM modulator gain (d/v c ) can be calculated by using Equation (6.3) i.—L The amplitude of the sawtooth signal of the PWM modulator, V p , is 2i = !^=> K,= — = 10V. 1 D p D (b) The following MATLAB program evaluates the parameters of the model and draws the Bode plot. % Boost example L=10e-3; C = 100e-6; V d = 10 V„ = 20 IP 220 Power-Switching Converters f s = 1000 R o = 20 V re , = 5 D=^ -(K,/V ) / c =-(1 -oyvjR num = [L*/ c V4 p *(D- 1)] den = [L*C/power((1 - D),2) L/(fl *power( (1 - D),2)) 1] k=1/(V p * power((1 - D),2)) sysl = /c*tf(num,den) bode(sysl) As shown in Figure 6.17, the boost converter behaves as a second- order system, with an additional right-half plane zero at a frequency near 300 Hz. Bode diagram -270 102 103 Frequency (rad/sec) Figure 6.17 Bode plot of the small-signal transfer function of the boost converter. Dynamic Analysis of Switching Converters 221 6.2.2 Summary of Small-Signal Models of Switching Converters Table 6. 1 to Table 6.5 summarize the small-signal models of the basic switch- ing converter topologies, operating in the current and voltage modes and in the continuous- and discontinuous-conduction modes. The tables are com- piled from several sources [5,10-14]. The models were obtained using the averaged models described in Section 6.2.1. It can be seen that depending on the mode of operation, the conversion ratio of a linear converter may become nonlinear and vice versa. Also, the order of the transfer function of the switching converter is reduced by one order when operating either in the current mode or in the discontinuous mode. In addition to the left half-plane zero introduced by R CST , some topologies (e.g., boost, flyback) have a right half-plane zero that causes a nonminimal phase response. This is an unwanted phenomenon in voltage regulators because any output voltage variation becomes larger before the controller can correct it (see Table 6.1 to Table 6.5 for the notations). 6.2.3 Review of Negative Feedback Using Classical-Control Techniques 6.2.3.1 Closed-Loop Gain Figure 6.18 displays a block diagram representation of a closed-loop system. The feedback network, /3, produces a voltage, V u which is a sample Table 6.1 List of Symbols Used in the Models Symbol Definition /. Switching frequency R Output load resistance Rcsr Output capacitor's ESR C Output capacitor v, Input voltage v Output voltage L Filter inductor D Duty cycle v c Control voltage k * peak,max' *c,max 'peak kV c M V oul IVi Conversion ratio ■"sec Secondary transformer inductor = LpN V.N = iV p : N s Transformer ratio 222 Power-Switching Converters Table 6.2 Small-Signal Model of the Buck Converter Buck voltage mode Frequency of the first-order pole Frequency of the second-order pole Frequency of the left half-plane zero Frequency of the right half-plane zero VJVi DC gain Ko/K e DCgain Continuous conduction 1 2-n-VXC 1 2-irR^C D Vi Discontinuous conduction 2-M 2ir(l - M)RC None because of DCM l 2irR es tC 1 + Vl + mL/R)T/&) yj2(L/R)T Buck current mode Frequency of the first-order pole Frequency of the second-order pole Frequency ofcthe left half-plane zero 1 2ttRC None because of CM 1 2irR csr C 2-M 2ir(l - M)RC None because of DCM 1 2irRes T C Frequency of the right — half-plane aero VJVi DC gain D See Ref. [14] Ko/K e DCgain kR See Ref. [14] of V . The error signal, V e = V^ - V f , is multiplied by the plant transfer function, A(s), to obtain the output voltage, V . The closed-loop transfer function can be derived as V te{ i+PA (6.44) dynamic Analysis of Switching Converters Table 6.3 Small-Signal Model of the Boost Converter 223 Continuous conduction Boost voltage-mode Frequency of the first-order pole Frequency of the second-order pole Frequency of the left half-plane zero Frequency of the right half-plane zero Ko/KjDCgain Ko/K e DCgain Boost current-mode Frequency of the first-order pole Frequency of the second-order pole Frequency of the left half-plane zero Frequency of the right half-plane zero Ko/P'iDCgain VJV K DC gain 0-D) 2-irVLC 1 2-jtR^C (1 - DfR 2trL 1 (l-D) ttRC None 1 2-irR^C (1 - DfR 2-trL 1 k RVj 2 V„ Discontinuous conduction 2 + (l/>/l + (4D*/(2Lf s /R)j) 2-nRC High frequency 1 2ttR csi C High frequency \ + y /\+{2D 2 R/Lf s ) 2 vmjm i-w/2v ) i 2+ E AD 2 {2Lf,/R) 2-nRC High frequency 1 2-nR^C High frequency 2+ (l/^(l/4) + [* Vc/ V,] 2 /(2Z/.//0 )) RC * y/l-{Vi/yo) ^/VlZm i-Ci/a^o) The loop gain 7" L is defined as follows: 71 = pA. (6.45) 224 Table 6.4 Small-Signal Model of the Buck-: Power-Switching Converters Boost Converter Continuous conduction Discontinuous conduction Buck-boost voltage mode Frequency of the first-order pole Frequency of the second-order pole Frequency of the left half-plane zero Frequency of the right half-plane zero Ko/KiDCgain Ko/KeDCgain Buck— boost current mode Frequency of the first-order pole Frequency of the second-order pole Frequency of the left half-plane zero Frequency of the right half-plane zero VJV; DC gain VJV e DC gain 0-D) 2irVLC 1 2irR csr C RQ - Df 2-rrLD D (l-Z>) Vi U-Bf 0+D) 2-nRC l 2-irR^C R{\ - Df 2trLD D 0--D) kR V x 2V + V; l trRC High frequency l 2-irR^C High frequency D V, l ttRC High frequency l 2-rrR^C High frequency kV c For 71 » 1, the closed-loop gain becomes independent of the gain A, and depends only on the feedback network. Therefore, V _1 (6.46) Dynamic Analysis of Switching Converters Table 6.5 Small-Signal Model of the Flyback Converter 225 Continuous conduction Flyback voltage mode Frequency of the first-order pole Frequency of the second-order pole Frequency of the left half-plane zero «s;-3". Frequency of the right half-plane zero VJVi DC gain VJV,. DC gain Flyback current mode Frequency of the first-order pole Frequency of the second-order pole Frequency of the left half-plane zero Frequency of the right half-plane zero VJ K; DC gain yjV e DC gain (1-Z>) 1 2irR esf C R(\ - Df JirLsxD D 0-0) (1 - Df N N (1-/)) 2irVXsecC 1 2-rrR^C R(\ - Df 2-trLxcD D N V-D) kR Vi ~N 2V Q +Vi Discontinuous conduction 1 ttRC High frequency 1 High frequency ND \ / * 2i-sec/s ViNy 1 / * |/ 2L xc f s ttRC High frequency 1 2ir/? esr C High frequency ND 1 R ND ]l2 Lx J s k lRL se J s n\I 2 If the feedback network is made with precision components, then V is proportional to V ref . This is usually the goal in designing a closed-loop switching converter. 6.2.3.2 Stability Analysis A system becomes unstable when the denominator of its transfer function is zero. In this case, at least one of its poles lies on the imaginary axis. This situation implies that 226 Power-Switching Converters v re , , A(s) v a A ej? T B(s) Figure 6.18 Block diagram representation for a closed-loop system. BA - -1 or i l/3/>l = l PA- 1 or | phase()3) + phase(y4) = 180°. (6.47) 6.2.3.2.1 Relative stability. The relative stability is a measure of how far the system is from instability. The relative stability of a feedback system can be inferred from its gain and phase margins. The gain margin is defined as the increment of the loop gain required to drive the feedback system into instability. This is the amount of the loop gain necessary to reach OdB when the phase shift of the loop gain differs -180° from the phase at DC. 1 The phase margin is defined as the phase shift necessary to reach -180° 2 when the loop gain is unity (or OdB), as shown in Figure 6.19. Both the gain margin and the phase margin must be positive for the system to be stable. To ensure a stable loop response of the switching converter, the usual practice is to design for a gain margin of at least 6 dB and a phase margin of about 45°. Under these conditions, a second-order system would have a critically damped step response. 6.2.3.2.2 Stability analysis using Bode plots. A Bode plot is a plot of the magnitude and phase versus frequency. It is a very convenient method of determining the stability of a switching converter. Consider the Bode plot of the three-pole system of Figure 6.20, where the amplitude and phase of the loop gain has been graphed. The loop gain crosses the horizon- tal axis at/j (i.e., the amplitude of the loop gain is 1 or dB at frequency /0- At this frequency, the phase of the loop gain is close to -270°, giving a negative phase margin. Thus, the system is unstable. The gain margin of this system is determined at frequency / p , where the phase of the loop gain is 180°. At this point, the magnitude of the loop gain is positive, and so is the gain margin. Since one of the two stability margins is negative, the system is unstable. 1 Assuming that the system has singularities at high frequencies only. 2 From the phase at DC. Dynamic Analysis of Switching Converters 20 227 0.2 to u r Figure 6.19 Definitions of gain and phase margins. 10 6.2.3.3 Linear Model of the Closed-Loop Switching Converter A closed-loop model of the switching converter displayed in Figure 6.21 is analyzed next. 6.2.3.3.1 Feedback network. The feedback network is usually formed by a voltage divider (Ri and R 2 in Figure 5.26). Then its transfer function is given by v' = v Ri R\ +R 2 (6.48) 6.2.3.3.2 Error amplifier compensation networks. When the loop is closed, the switching converter may become unstable or exhibit an undesir- able transient response. The switching converter can- be stabilized by add- ition of a compensator network in the error amplifier- to increase the phase Power-Switching Converters Of -45° -90° -135° -180° -225° -270° Figure 6.20 Loop gain of a system with three poles. Compensation Switch 1 B(s) * 1 Figure 6.21 Closed-loop switching converter. u m Dynamic Analysis of Switching Converters 229 margin. At the same time, the compensator can also serve to shape the loop transfer function to achieve a desired transient response. The following subsections introduce the basic concept of frequency compensation for switching converters. A more detailed treatment of the feedback loop sta- bilization can be found in Pressman [1 5]. According to Nyquist sampling theory, the unity-gain crossover fre- quency, /i, must be less than half the switching frequency to ensure system stability. The usual practice is to choose a unity-gain crossover frequency to be one-fourth to one-fifth of the switching frequency in order to reduce the switching ripple at the output of the switching converter [15]. The unity-gain crossover frequency should be high enough to allow the switching converter to respond quickly to its output transients [15]. Having set the unity-gain crossover frequency, the gain of the error amplifier is selected to yield a total loop gain of OdB at the unity-gain crossover frequency. The magnitude response of the error amplifier is designed to cross OdB at a slope equal to — 20dB/decade with the desired gain margin. PI compensation network — There are many compensation networks for the error amplifier. Figure 6.22 shows a compensation network that consists of two capacitors and two resistors connected to the error amplifier in an inverting configuration to conform to a PI controller. The correspond- ing transfer function is , (iAC 2 Xft2 + 0ACi)) " (S) R l {R 2 + (\/sC l ) + (l/sC 2 )y (6.49) Since C, is generally much larger than C 2 , the transfer function of Equation (6.49Xcan be simplified to q, II Vib o vw i VtAr- HI- -O V Figure 6.22 Compensation network with two poles and a zero. 230 Power-Switching Converters H(s) = \+sR 2 Ci S R l (C i +C 2 + sR 2 C,C 2 ) (6.50) The magnitude response of the compensation network is shown in Figure 6.23. It has two poles, one at the origin and the other at/ p = \l2-n R 2 C 2 . The zero of this compensation network is at f x — l/2irR 2 Ci. The high-frequency pole serves to attenuate the high-frequency gain of the switching converter to reduce high-frequency switching noise. The low-fre- quency pole serves to maintain a sufficient gain at low frequencies in order to minimize the steady-state error in the average output voltage. The locations of the pole and zero define the component values of the compensation network. The phase response of the compensation network is shown in Figure 6.24. It starts at -90° due to the pole at the origin. The low-frequency zero,/ z , causes a phase boost, while the high-frequency pole,/ p , introduces a phase lag and causes the phase response to approach —90° again. This compensation network is used when the slope of the open-loop magnitude response of the switching converter at the unity-gain crossover frequency is —20 dB/decade, usually due to the contribution of the output capacitor ESR. 0.001 0.01 .1 10 a 100 / z = 854.3 f p =21,832 f(kHz) 1000 10000 Figure 6.23 Frequency response of the compensation network shown in Figure 6.22. Dynamic Analysis of Switching Converters 231 -20 •§ -SO S -60 0.001 10000 Figure 6.24 Phase response of the compensation network shown in Figure 6.22. The zero introduces a phase lead while the pole introduces a phase lag. At the unity gain frequency, the phase lead due to the zero is ©lead = tan" 'GD while the phase lag due to the pole is tW^an-'f^ (6.51) (6.52) The total phase lag introduced by the compensation network and the error amplifier at the unity-gain crossover frequency, f u is lag = 270° - tan-'^l) + tan_ '(^) - (6.53) The 270° phase lag is due to phase inversion introduced by the inverting error amplifier (180°) and the pole at the origin introduced by the compen- sation network (90°). Thus, the locations of the pole and zero are chosen to yield the desired phase margin. 232 Power-Switching Converters Proportional-integral-derivative (PID) compensation network — Figure 6.25 shows a 3-pole, 2-zero compensation network. This compensation is also known as PID because it provides terms, which are proportional, integral, and derivative of the error signal. The integration is provided by a third pole, located at zero, which is used to minimize the steady-state_error. The transfer function for this compensation network is //(» = (1 +ju>R 2 Cy) (1 +MRj + J?3)C 3 ) - w 2 R 2 Q C 2 +MC, + C 2 ) Ri +jtoRt R 3 C 3 (6.54) having one pole at zero and two high-frequency poles, one atf p i = 1/2-jt R 3 C 3 and the other at/ p2 = (C, + C 2 )/2-n- R 2 C X C 2 . The zeros are at/ 2l = l/2ir R 2 C t and fa = \l2-niRx + R 3 )C 3 , respectively. The two gains of the compensation network are K 1 =R 2 /R } and K 2 = R 2 (Ri + R 3 )/RiR 3 , respectively. The asymptotic approximated magnitude response is shown in Figure 6.26. As shown, the low-frequency gain below fa decreases at a rate of -20 dB/ decade due to the pole at the origin. The gain is constant between the two zero frequencies. After fa, the magnitude response starts to increase at a rate of +20dB/decade until fa. It is flat again between f p] and/ p2 . After f p2 , the magnitude response decreases at a rate of — 20dB/decade. This compensa- tion network is used primarily for a switching converter with no output capacitor ESR. The slope of the open-loop magnitude response at the unity- gain crossover frequency of such switching converter is —40 dB/decade. In order to yield a -20 dB/decade slope at the unity-gain crossover frequency, the magnitude response of the compensation network must have a slope of +20 dB/decade at the unity-gain crossover frequency. Thus, the unity-gain crossover frequency should occur between fa and fa where the magnitude response increases at a rate of +20 dB/decade. Figure 6.27 shows tfie-mag- nitude response of the compensated network with Ci=Q.16(iF, C 2 = 532pF, C 3 = 14.3nF, i?, = 10kO, i? 2 =10kO, and R 3 = 1.1 kO. The o V«. Figure 6.25 Compensation network with three poles and two zeroes. Dynamic Analysis of Switching Converters 233 20 dB/decade Figure 6.26 Asymptotic approximated magnitude response of the compensation network shown in Figure 6.25. two zeros are at 100 Hz and 1 kHz, respectively. The two poles are at 10 and 25 kHz, respectively. It should be noted that the gains between the zeros and poles are not constant, as depicted in Figure 6.26. Figure 6.28 shows the phase response of the compensation network. As can be seen, a phase boost occurs between / zl and/ p2 . The wider the separation between the poles and zeros, the larger is the phase margin. As such, this compensation network yields a very good transient response. To simplify the design process, the two zeros in the compensation network shown in Figure 6.25 are usually chosen to be equal to each other (i.e.,/ z i =fi2=fzd) such that 1 1 27ri? 2 Ci 2tr{Ri + R^C} (6.55) or R2C1 = (/?!+ i?3)C3- The phase boost at the double zeros, zll , is zd =2tan- 1 '^- (6.56) (6.57) 234 Power-Switching Converters 20 V I M 7 I I ! ; hi I I I --;-tV4 :| j lb « \ E ! i I I li H; i i iii'1 -i-lU 10 5 \ \ "T;V j H-U / i j ii|[ , ; ■ ill ]-^ _ ( .L.Ll — ]- --—L HIM 1 M iV- : ; * !;!;:; 1 ! ' 1:1:: i i ■ i| j (— '- V T*- L„i._ *"HiH : —5 ■ ;|| i H ! ' 1 : * ! '!: ! Mi '■ Ml : i ! . ^ ! ■ I i i \ L-._L Hi ' : i ' ■ I -'& 01 0.1 1 10 100 1000 10000 r 4 * 'p2 f(kHz) Figure 6.27 Frequency response of the compensation network shown in Figure 6.25. since there are two zeros atf zd . To simplify the design process, the two high- frequency poles are usually chosen to be equal to each other such that 1 (C, + C 2 ) 2ttR 3 C3 2irR 2 CiC 2 (6.58) or R± c CtC 2 R 2 3 Ci + C 2 ' (6.59) The asymptotic approximated magnitude response of the compensation network shown in Figure 6.25 with a 2-zero and 2-pole is displayed in Figure 6.29. The phase lag due to the double pole, 0pd, is approximately 0pd=2tan- UJ" (6.60) The total phase lag introduced by the compensation network and the error amplifier at the unity-gain crossover frequency is Dynamic Analysis of Switching Converters 235 0.001 f(kHz) 1000O Figure 6.28 Phase response of the compensation network shown in Figure 6.25. 20 dB/decade Figure 6.29 Asymptotic approximated magnitude response of the double-zero, double-pole compensation network shown in Figure 6.25. 236 bg = 270° - 2 tan" ■(£)♦"--(£)• Power-Switching Converters (6.61) Again, the 270° phase lag is due to phase inversion introduced by the inverting amplifier and the pole at the origin of the compensation network. Example 6.5. The compensation network shown in Figure 6.22 has the following component values: Ci=6.8nF, C 2 = 270pF, i?i = 10kfl, and R 2 = 27k£l. Determine (a) the zero introduced by the compensation net- work, (b) the high-frequency pole introduced by the compensation network, and (c) the phase lag introduced by the compensation network at 5 kHz. Solution. (a) The zero frequency is 1 1 U = 2irR 2 Ci 2ir(27 x 10 3 )6.8 x 10~ 9 (b) The pole frequency is = 854.3 Hz. /p = 1 1 2ttR 2 C 2 2<n-(10 x 10 3 )270 x KH 2 = 21,832 Hz. (c) The phase lag contribution from the compensation network at 5 kHz is so- +„„-(£) -„„-(£). 22.59°. 6.2.4 Feedback Compensation in a Buck Converter with Output Capacitor ESR A closed-loop buck converter is shown in Figure 6.30. In this converter, the average output voltage is specified to be 5 V with an input voltage of 12 V and a load resistance, R L ,_o{ 5 ft. The objective of the feedback compensation is to shape the closed-loop magnitude response of the switching converter to achieve a -20 dB/decade roll-off rate at the unity-gain crossover frequency with a sufficient phase margin for stability. The sampling network, R 2 and R*, contributes attenuation according to its sampling ratio ofR^iRj + R4). Since the average output voltage of the buck converter is 5 V and the sampled voltage is chosen to be 2.5 V, the gain attenuation of the sampling network is 20[logio(2.5/5)] = -6dB. The PWM modulator gain is the gain from the error amplifier output to the average Dynamic Analysis of Switching Converters 237 Output fitter Pulse-width modulator Figure 6.30 Circuit schematic of a closed-loop buck converter. voltage at the input end of the output inductor. When the output of the error amplifier is at its peak value of 3.5 V, the duty cycle is 100% and the average voltage at the input end of the output inductor is 12 V. Thus, the PWM contributes a gain of 20 log«(jy K p ) or 10.7 dB, where V p is the peak ampli- tude of the sawtooth voltage"(315 V). The low-frequency gain of the open-loop buck converter is +4.7 dB. The natural frequency of the output filter, / D , is y /R /L C {R + Jtcsr) V5/(100 x 10-")(100 x lQ-")(5 + 0.5) Jo ~ 2tt ~ Itt = 1.517kHz (6.62) while the ESR break frequency, /esr. i s 1 yksR 2ir(0.5)l00 x 10-« = 3.1 8 kHz. (6.63) The unity-gain crossover frequency, f\, is chosen to be one fifth of the switching frequency of 25 kHz (i.e., /,=5kHz). The loop magnitude 238 Power-Switching Converters response of the uncompensated buck converter, excluding the compensation network and the error amplifier, is shown in Figure 6.31 as ABCD. From Figure 6.31, the attenuation at the unity-gain crossover frequency is -14.5 dB. Hence, the gain of the error amplifier should be chosen to be + 14.5 dB so that the gain at the unity-gain crossover frequency is dB_This is achieved by selecting the ratio ^^i such that a 14.5 dB gain is attained by the error amplifier. Thus, if R t is chosen to be 47kft, then R 2 is about 250 kft. The locations of the pole and zero of the compensation network are then determined to yield the desired phase margin of 45°. The total phase shift at the unity-gain crossover frequency should be 360°— 45° = 315°. Since the output filter contributes a phase lag of 6 LC = tan J2^(/// )\_ tan _,/-X,\ m90 \\-{flfof) V/iW (6.64) Then, the phase lag contribution from the compensation network and the error amplifier is flea = 315° - 109.9° = 205.1° (6.65) 1000 Figure 6.31 Magnitude response of the open-loop (ABCD) and closed-loop (J KLMNO) buck converter. The magnitude response of the error amplifier is-EFGH. Dynamic Analysis of Switching Converters 239 From Equation (6.53), the phase lag contribution from the compensation network is thus Assuming that the pole and zero are equidistant from the unity-gain cross- over frequency, 3 then tan-'/" - tan ~'(^) = 64 " 9 °- (667) Solving iteratively for/" yields a value of 4.5 to achieve a phase lag of 64.9°. Hence, the high-frequency pole should be located at 4.5 times the unity-gam crossover frequency, or 22.5 kHz, while the low-frequency zero should be located at 1/4.5 of the unity-gain crossover frequency or 1.11 kHz. The magnitude response of the error amplifier is shown in Figure 6.31 as EFGH. The components of the compensation network can be determined now. The capacitor C\ is C,= T 4-r= 573 P F < 6 " 68 > ItrRrf-L and the capacitor C 2 is The overall loop magnitude response of the feedback compensated switching converter is shown in Figure 6.3 1 as JKLMNO. Notice that the loop gain at the unity-gain crossover frequency in the overall magnitude response of the feed- back compensated switching converter is dB. Above the high-frequency pole, /p, the loop gain attenuates at -40 dB/decade. Thus high-frequency switching noise is suppressed. If high-frequency noise is a problem, then the location of the high-frequency pole can be made to be less at the expense of a more sluggish transient response. If/ P is chosen to be at 12.5 kHz, then / z is 0.288 kHz according to Equation (6.66). 3 This is an approximation to simplify the calculations. An exact solution would satisfy magnitude and phase constraints simultaneously. The exact solution is used in the design examples of Chapters 9 and 10. 240 Power-Switching Converters 6.2.5 Feedback Compensation in a Buck Converter with no Output Capacitor ESR The output ripple voltage of a buck converter depends largely on the magnitude of the ESR in the output capacitor. Thus, it is necessary to choose an output capacitor with a low ESR to reduce the output ripple voltage. A different compensation network from that considered in Section 6.2.4 must be employed, as the capacitor manufacturers strive to manufac- ture aluminum electrolytic capacitors with essentially zero ESR. Consider the buck converter shown in Figure 6.30 but with no output capacitor ESR. The corner frequency of the output filter, f , was found to be 1.59 kHz. Curve ABC in Figure 6.32 shows the magnitude response of the open-loop buck converter. The unity-gain crossover frequency is again chosen to be 5 kHz, which is one fifth of the switching frequency. Since the slope of the magnitude response at the unity-gain crossover frequency is —40 dB/decade, the compensation network shown in Figure 6.25 is chosen. From the open- loop magnitude response of the buck converter shown in curve ABC of Figure 6.32, the attenuation at the unity-gain crossover frequency is -16dB. Hence, the gain of the error amplifier at the unity-gain crossover -■;•» Figure 6.32 Magnitude response of the open-loop (ABC) and closed-loop (HIJKL) track converter. The magnitude response of the error amplifier is DEFG. Dynamic Analysis of Switching Converters 241 frequency is chosen to be +16 dB in order to yield a OdB at the unity-gain crossover frequency. The locations of the double-pole and double-zero of the compensation network are chosen to yield the desired phase margin of 45°. The total phase shift at the unity-gain crossover frequency is 360° - 45° or 315°. Since the output filter contributes a phase lag of approximately 180°, the allowable phase lag contribution from the compensation network and the error amp- lifier is 135°. Hence, from Equation (6.61), the phase lag contribution from the compensation network is 2 tan"' (j£\ - 2 tan"' U±\ = 270° - 135° = 135°. (6.70) Assuming that the double-pole and double-zero are equidistant from the unity-gain crossover frequency, then tan-'/" - tan" 1 (± = 135°. (6-71) Solving iteratively for/" yields a value of 5 to achieve a phase lag of 135°. Hence, the high-frequency double-pole should be located at five times the unity-gain crossover frequency or 25 kHz, while the low-frequency double- zero should be located at one fifth of the unity-gain crossover frequency or 1 kHz. The magnitude response of the error amplifier is shown in Figure 6.32 as DEFG. The overall magnitude response of the feedback compensated switching converter is shown in Figure 6.32 as HIJKL. Notice that the gain at the unity-gain crossover frequency in the overall magnitude response of the feedback compensated switching converter is OdB with a slope of -20dB/decade. There are six components to be selected for the compensa- tion network. As shown in curve DEFG of Figure 6.32, the gain at the double-zero is 2dB or 1.26. Assuming an R t value of 1000 ft, then R 2 is 1260 ft. The gain at the double-pole is measured to be 30 dB or 31.6 from curve DEFG in Figure 6.32. Assuming that R t » jR 3 , then i? 3 is R2/K2 or 40ft. From /pi =/ pd , the capacitance value for C 3 is C 3 = o ) g =0.16pF. ( 6 - 72 > 27T/p d i?3 From Equation (6.56), the capacitance value for Cj is C, = <*'+* 3 > C3 = 0.13 uF. (6-73) R2 y .~ Power-Switching Converters From Equation (6.59), the capacitance value for C 2 is (6.74) C 2 = _ C ' C ^/* 2 _L = 5.29nF. [C, - C 3 {R 3 /R 2 )} In practice, commercially available component values are chosen for the capacitors and resistors. It is necessary to check the influence of the time delay on the phase margin/Assuming a time delay of 1 us, from (6.30), the phase(delay) = -360° x 1 |xs x 5kHz (6-75) phase(delay) = -1.8° which is not significant in the phase margin. 6.2.6 Linear Model of the Voltage Regulator Including External Perturbances In the linear model, the nominal load impedance can be modeled as a constant current source /„ at the output of the switching converter. Load variations are represented by a small-signal current source f , as shown in Figure 6.33. The perturbations of the output voltage may be expressed by the linear terms of its Taylor series expansion as V„ = GKtfVref + GkdcVdC + Gi„ l o, where G v*t = dv dv iv DC =0 'ref ' '° ;„=o c=0 Vref ''°=° (6-76) (6-77) Vnr. + Switching converter -@ (# ©" Figure 6.33 Linear model of a voltage regulator including external perturbances. | 243 Dynamic Analysis of Switching Converters where G v is the sensitivity of the output voltage with respect to the reference "oltage. There is usually a direct relationship between the output and the reference voltages, meaning that the voltage regulator will not be better than the reference itself. The audio susceptibility, defined as c _j^r" r=o = A.r" rf=o (6.78) KDC 0Vdc '*»=° VDC l? °=° is a measure of the influence of the variations on the unregulated DC input voltage on the regulated output voltage. The most important variations on Kdc are due to fluctuation of the line voltage, the rectified ripple voltage, and voltage drop in the line source impedance. The audio susceptibility models the effects of the variations of the DC input voltage on the output voltage. Usually, V oc is an unregulated voltage derived from a diode bridge and a capacitor filter; thus, it has the same voltage ripple at twice the line frequency (i.e., 100 or 120 Hz). It is desirable that (G rac ) be much less than 1 . G Vx is equivalent to the PSSR of an OP AMP circuit. The output impedance is defined as 3v„r =0 _v<>r =0 =7 (6.79) r = — I = — I =Z '' di„ I*dc=o ? o '*dc=0 It is desirable that the output impedance of the voltage regulator be much smaller than the load impedance. In addition, the bandwidth of the output impedance should be larger than the bandwidth of the load to ensure fast recovery from load transients. -6.2.7 Output Impedance and Stability The current, /„ represents the nominal load and 1 is a source of perturbation to the voltage regulator of Figure 6.33. If f„ is a step function, the corre- sponding v„ is the system step response given by the transfer function Z c . The output voltage of a voltage regulator should be bounded within certain limits (e.g., 5 ± 0.1 V) to avoid damaging sensitive loads. Tnerel ore, trie step response should be overdamped or, at the most, critically damped. 1 he phase margin of a second-order system corresponding to a critical y damped step response is 45°; therefore, the phase margin for a voltage regulator must be greater than 45°. r . According to feedback circuit analysis, the output impedance ot the circuit of Figure 6.33 can be calculated as „ Zoo (6.80) m 244 Power-Switching Converters where Z^ is the open-loop output impedance, including the load, calculated from Figure 6.34. Z„f can also be expressed as _L-_L _L Z r Z Zl ' (6.81) where Z is the closed-loop output impedance seen by the load. Then if \&A\ » 1, then Z of <c Z 00 , and if Z of «: Z L , then Z of *» Z and Z L will not have much influence on Z of and its stability. This is a desirable condition, but not always possible to achieve. Z of = (Z 00 /(l + pA)) has the same poles as the transfer function vjv^, its phase and gain margins can also stabilize the gain and shape its frequency response. K„, >^ I 1 V a T Load 1 I (a) Zoo "^ > >> v n J 1 i^ B(s) Z (b) Figure 6.34 Output impedance. _L Dynamic Analysis of Switching Converters 2 45 6.2.8 State-Space Representation of Switching Converters 6.2.8. 1 Review of Linear System Analysis Consider the simple linear circuit shown in Figure 6.35. The circuit is a second-order system since it has two storage elements: a capacitor and an inductor. It is also a low-pass filter as the capacitor attenuates or Filters the high-frequency signal beyond the corner frequency of the filter. State vari- ables of this second-order low-pass filter are chosen to be the current flowing through the inductor, x u and the voltage across the capacitor, x 2 . The source variable is designated as u x . Applying KirchofPs voltage law, the source variable, w u is equal to the sum of the voltage drop across the inductor and the voltage across the capacitor u\ Lx\ + X2, (6.83) where X| = dx^ dt (6.84) and is equal to the time rate of change of the inductor current, x,. Applying Kirchoffs current law, the inductor current, x v , is equal to the sum of currents flowing through the capacitor, C, and the resistor, R: X\ = CX2 + R' (6.85) where x 2 = dx 2 dT (6.86) and is equal to the time rate of change of the capacitor voltage, x 2 . Equation (6.83) can be rearranged to yield the rate of change of the inductor current, x, as Figure 6.35 A simple second-order low-pass circuit. w 246 X2 , Ml Power-Switching Converters (6.87) while Equation (6.85) can be rearranged to yield the time rate of change of the capacitor voltage, x 2 as X2 x\ -xz C RC' (6.88) From the context of linear system analysis, these equations can be written in matrix form as i = Ax + Bu, (6.89) where x is the state vector, A is the state coefficient matrix, u is the source vector, and B is the source coefficient matrix. In our example, these matrices are LC RC. and » = [«i], -»]• (6.90) (6.91) (6.92) (6.93) If either A or B contains a function of x or u, then it is a nonlinear system. For the case of a linear system, the DC solution is obtained by setting Equation (6.89) to zero to yield x = -A~ l Bu, (6.94) where A~ l is the inverse of the state coefficient matrix. The inverse of a matrix is the adjoint matrix divided by its determinant. It should be noted that the determinant of A must be nonzero for a valid DC solution. Taking the Laplace transform of Equation (6.89), gives (6.95) or sX(s) = AX(s) + BU{s) X(s) = (si - A)'* BU(s), (6.96) Dynamic Analysis of Switching Converters 247 where / is the identity matrix having the same dimension as A. For our simple second-order example, we have [X 2 (s)\ s 2 +Tk + -& Equation (6.97) yields two transfer functions. The transfer function relating the inductor current, x u to the input voltage, u u X x (s)IU\{.s), is Xds) (l/L)(s + (l/RCy) (698) f/,(5) (s 2 + (s/RC) + (l/LC)) while the transfer function relating the capacitor voltage, x 2 , to the input voltage, mi, X 2 {s)/U } {s), is X 2 (s) _ l/LC (6 .99) U,{s) (5 2 + ( 5 / J RQ + (l/Z.Q)' It can be seen that the linear system analysis lends itself readily to computer simulations. 6.2.9 State-Space Averaging State-space averaging is an approximation technique that approximates the switching converter as a continuous linear system [4]. State-space averaging requires that the effective output filter corner frequency, /„ to be much smaller than the switching frequency, / s or fjf s <C 1- This is smular to the requirement for a low output-switching ripple. Final results of the state- space averaging can be either a mathematical or equivalent circuit model. The mathematical model permits the designer to determine voltages, cur- rents, and small-signal transfer functions of the switching converter. How- ever, this model does not enable the designer to physically visualize electrical processes occurring in the switching converter. The equivalent circuit model provides the designer with a better understanding of the physical operation of the switching converter. In general, both the mathematical and equivalent circuit models are necessary and recommended in the design of practical switching converters. There are two drawbacks of the state-space averaging technique. The major one is that it does not result in a general linearized model of a switching converter (a model that is independent of the switching converter configuration, operating mode, and control variable). The other drawback is that it requires extensions and modifications if the control 248 Power-Switching Converters variable is other than the duty cycle {16J. The major advantages of this method are the establishment of a complete converter model with both steady-state (DC) and dynamic (AC) quantities, and the mathematical rigor with which it can be carried out [17]. Procedures for state-space averaging are as follows: Step 1. Identify switched models over a switching cycle. Draw the linear switched circuit model for each state of the switching converter (e.g., currents through inductors and voltages across capacitors). Step 2. Identify state variables of the switching converter. Write state equations for each switched circuit model using KirchofFs voltage and current laws. Step 3. Perform state-space averaging using the duty cycle as a weighting factor and combine state equations into a single averaged state equation. The state-space averaged equation is x = [Aid + A 2 {\ - d)]x + [Bid + #2(1 - d)]u. (6.100) This results in a set of nonlinear continuous equations. A nonlinear continuous equivalent circuit can be drawn from this set of nonlinear equations. Step 4. Perturb the averaged state equation to yield steady-state (DC) and dynamic (AC) terms and eliminate the product of any AC terms. Step 5. Draw the linearized equivalent circuit model. Step 6. Perform hybrid modeling using a DC transformer, if desired. We will make use of the above procedures to obtain state-space averaged models for (a) an ideal buck converter operating in the continuous mode, (b) an ideal buck converter operating in the discontinuous mode, (c) a continuous-mode buck converter with an output capacitor containing an equivalent-series-resistance (ESR), and (d) an ideal boost converter. 6.2.9. 1 State-Space Averaged Model for an Ideal Buck Converter We now illustrate the state-space averaging method for an ideal buck converter shown in Figure 6.36 operating in the continuous mode. State variables for this buck converter are chosen as the inductor current, X\, and the capacitor voltage, x 2 - With the assumption of ideal switching devices, two switched models are shown in Figure 6.37(a) and (b), respectively. Using KirchofFs voltage law in Figure 6.37(a), the state equation is u i =Lxi+x 2 (6-101) Dynamic Analysis of Switching Converters and using KirchofFs current law, the state equation is x\ = Cx 2 + — X2 R 249 (6.102) for the interval when the switching transistor is switched on, i.e., dT^ Simi- larly, applying Kirchoff's voltage law to the switched model shown in Figure 6.37(b), the state equation is = Lx l +x 2 (6-103) and applying Kirchoff's current law, the state equation is _. Xj xi = Cx 2 + — (6.104) for the interval when the switching transistor is switched off, i.e., (1 — d)T. Equations (6.101) to (6.104) can be written in matrix form as [£]-[,?c --$£>]£] + ['?]" for the AT interval and [s]-[,?c -<«;HSH for the (1 - d)T interval, respectively. The state-space averaged state coef- ficient matrix is A -_[ -(1/1)1 d \ -d/DL rf) 4 ~[l/C -{\/RC)\ a+ [\/C -(1/J?C)J 11 ; (6.107) Figure 6.36 Circuit schematic of an ideal buck converter with the state and source variables indicated. 250 Power-Switching Converters (b)(1-d)Tinterval Figure 6.37 Switched models for the ideal buck converter. or r o -a/Q 1 [l/c -( (6.108) (6.109) -a/Roy The state-space averaged source coefficient matrix is M'fl'-ra'—'-H- State-space averaged equations for the buck converter in matrix form are [£] - [v°c -Z%] [s] + ["fh- From Equation (6.110), two nonlinear equations describing the state-space averaged model of the buck converter are x\ X7 d (6.111) Dynamic Analysis of Switching Converters and 1 RC *2- 251 (6.112) These equations are nonlinear because the duty cycle, d, is a function of u\. Equations (6.1 1 1) and (6.112) can be rearranged to yield u\d = Lx\ +x 2 and X\ = CX2 + *2 R (6.113) (6.114) A nonlinear continuous equivalent circuit can be drawn based on Equations (6.113) and (6. 114). This is shown in Figure 6.38. In this figure, u i d represents a pulsed voltage source. The next step is to linearize the state-space averaged equation. It should be noted that any nonlinear continuous system can be approximated as a linear system within a small neighborhood about its DC operating point. Each of the state and source variables is assumed to comprise of a steady-state (DC) term and a dynamic (AC) term as shown below: and *i = jcio + Xi, X2 = *20 + X 2 , "I = "10 + "1, d = D+d. (6.115) (6.116) (6.117) (6.118) *2 Figure 6.38 A nonlinear continuous equivalent circuit of the ideal buck con- verter. 252 Power-Switching Converters In the above equations, the AC terms are identified by the "hat" notation. The amplitudes of the AC terms are assumed to be small so that the product of any AC terms is negligible. Substituting these variables into state-space averaged Equations (6.1 1 1) and (6.1 12), the perturbed state-space averaged equations are ^ = -] ; (x 2 o+ic 2 ) + i(z> + rf)(» 1 „ + « I ) (6.119) and d*2 1 , -. -. 1 , - n. -dT=c ( * ,0+x,) -:Rc ( * 20+ * 2) - (6.120) Neglecting the AC product term of du ly Equations (6.1 19) and (6.120) can be simplified to yield xi = y ( - *20 + Duio) + y(~x 2 + Du\ + du l0 ) and 1 / x 2 o\ , 1 ( - x 2 \ From Equation (6.31), the DC solution is = -{-x 20 + Duiq) (6.121) (6.122) (6.123) 10. *20 "10 = D. (6.124) This is the steady-state voltage conversion ratio for an ideal buck converter operating in the continuous mode. The AC term from Equation (6.121) is — = —{- x 2 + Dui + du w ) (6.125) or X2 = D- Ul +d Ul0 - L-jj-. (6.126) Dynamic Analysis of Switching Converters Equation (6.126) reveals that the output voltage modulation is due primarily to changes in the input voltage, w,, the modulation in the duty cycle, d, and the modulation in the inductor current, x x . From Equation (6.122), the steady-state or DC solution is or *20 (6.128) X,0= lf- Equation (6.128) reveals that the steady-state input current is equal to the steady-state output voltage, x 20 , divided by the output resistance, R. The AC solution from Equation (6.122) is ***-L(x t -&\ (6129) dt ~ c \ Xl Rj or . _ c *&.*2. (6.130) Xl ~ C dt + R ' Equation (6.130) shows that the current modulation in the inductor is the sum of the current modulation due to the charging or discharging of the capacitor and the output current modulation due to modulation in the output voltage across the load. Equation (6.121) can be rearranged to yield x M + x 2 = -Lk\ + -D("io + mi) + duw (6.131) or x 2 = Du i +dui -Lx l (6.132) The above equation shows that the output voltage, x 2 , is equal to the sum of a steady-state input, Du x , and a modulated dependent voltage source of duw minus the voltage drop across the output inductor, Lx v . Equation (6.122) can be rearranged to yield „. , *20 + *2 (6.133) *I0 + X\ = Cx 2 + Jj v ' x, = Cx 2+ f. < 6 - 134 ) 254 Power-Switching Converters The above equation satisfies Kirchoff's current law at the output node. A linear equivalent circuit of the ideal buck converter operating in the continuous mode described by Equations (6.132) and (6.134) is shown in Figure 6.39. The input source, Du u is a function of the DC operating point as represented by the steady-state duty cycle, D. The dependent voltage source du\ is a consequence of the modulation in the duty cycle. The linearized equivalent circuit in Figure 6.39 does not actually represent the buck converter since the input source is represented by a modulated voltage source of Du\. As mentioned previously, the linearized equivalent circuit shown in Figure 6.39 is not unique. It can be manipulated to yield either a source- or a load-reflected equivalent circuit [17]. The source circuitry comprises of the input voltage source, u\, while the load circuitry consists of the output capacitor (C 2 ), output inductor (L), and load resistor {R). To draw a source-reflected linearized equivalent circuit for the ideal buck converter, Equations (6.132) and (6.134) can be manipulated to pre- serve Mi. From Equation (6.132), d x 2 L . n (6.135) and from Equation (6.134) (6.136) since the output voltage state variable is x 2 ID. The source-reflected linear- ized equivalent circuit for the ideal buck converter is shown in Figure 6.40. Figure 6.39 is already in the form of a load-reflected equivalent circuit since the load variables x 2 , L, C, and R are "preserved" [17]. The hybrid modeling technique introduced by Middlebrook and Cuk [4] can be used to combine the source-reflected and the load-reflected linearized equivalent circuits into *2 Figure 6.39 A linear equivalent circuit of the ideal buck converter. Dynamic Analysis of Switching Converters 255 a single equivalent circuit using a pseudo-element called a "DC trans- former." This element was introduced only as a convenient modeling tool in the state-space averaging technique [4]; so it cannot be realized physically. The linearized equivalent circuit of the ideal buck converter using the DC transformer is shown in Figure 6.41. The turn-ratio of the DC transformer is D, which corresponds to the duty cycle of the buck converter. It should be noted that both input and output variables are preserved in this equivalent circuit. As such, the linearized equivalent circuit using the DC transformer is a very convenient model for the simulation of the switching converter as a component in a complex power electronic system. 6.2.9.2 State-Space Averaged Model for the Discontinuous-Mode Buck Converter There are three switched models for the buck converter operating in the discontinuous mode as shown in Figure 6.42. Since there are three intervals in one switching period, the state-space averaged coefficient matrices are A=Aid 1 + A 2 d 2 + A 3 (l -dj- d 2 ) (6.137) and ?2. D Figure 6.40 A source-reflected linearized equivalent circuit of the ideal buck converter. ©"' 1 :D -o- L ywrv C T= x. Figure 6.41 transformer. A linearized equivalent circuit of the ideal buck converter using a DC 256 B = Bidi + B 2 d 2 + # 3 (1 - d, - d£). Power-Switching Converters (6.138) Equations (6.101) to (6.104) now apply for the d^Tand d 2 T intervals. During the (1 - d x - d 2 )T interval, Kirehoff's voltage law yields x\ =0 and KirchofFs current law .gives The state and source coefficient matrices during this interval are *-[! 4] and State-space averaging using Equations (6.137)"and (6.138) yields (a) c^T interval L * + c- - *2 ~k L (6.139) (6.140) (6.141) (6.142) (b) d^T interval (c) (1 - d, - cfe) T interval Figure 6.42 Switched models for the buck converter operating in the discontinu- ous mode. Dynamic Analysis of Switching Converters A = and B = d\ +d 2 L 1 RC J 257 (6.143) (6.144) State-space averaged equations in matrix form for the discontinuous-mode ideal buck converter are (d i +d 2 y X2 which gives d t +d 2 L 1 RC "*i + d x - L . x l- .0. mi (d, + d 2 ) , d\ (6.145) (6.146) u\d\ = (^i +d 2 )x 2 since x, = from Equation (6.43), and x 2 id^+dj) x\ - X2_ RC' (6.147) (6.148) A nonlinear continuous equivalent circuit derived from Equations (6.147) and (6.148) is shown in Figure 6.43. It can be seen that the state-space averaged discontinuous mode buck converter is a first-order system. The disappearance of the output inductor is a direct consequence of the con- straint that jci =0. In the discontinuous mode, x,(0) = x,(D = 0. (6.149) This implies that the inductor current starts at zero and resets to zero with no net increase in one switching period. Thus, x, no longer qualifies as a state variable in the discontinuous mode of operation since it has lost its dynamic properties. However, an input voltage perturbation does cause a perturb- 258 Power-Switching Converters WSt *t (hc/ lUl w*M> Ay (di+djx. C -r *2 Figure 6.43 A nonlinear continuous equivalent circuit for the discontinuous- mode buck converter. ation of the instantaneous inductor current from its steady-state value, which in turn results in a corresponding perturbation of the steady-state output voltage. The "average inductor current" is the quantity, which reflects the effect of this perturbation [4]. Thus, the average inductor current is introduced as a substitute for the "lost" state-variable. The instantaneous inductor current, x u can be expressed in terms of h, and x 2 . The instantaneous inductor current, x u in the steady state is x\ =■ 2 ' (6.150) where 7 Lp is the peak inductor current. The voltage across the inductor during the d t T interval can be expressed as u\ - x 2 (6.151) Combining Equations (6.150) and (6.151), the instantaneous inductor cur- rent, X\, can be written as X\ = (mi - x 2 ) 2Lf s Equations (6.147), (6.148), and (6.152) are perturbed to yield (hio + £*i)(Z>i + d t ) = (£>i +di+D 2 + d 2 )(x2o - x 2 ), dx 2 (Di + d t + D 2 + d 2 ) , (X20 + x 2 ) 7; WO + X\) dt RC and ~ADi+d,) xw + x\ — (mio + mi - x 2 o — x 2 ) — 2^7 — • (6.152) (6.153) (6.154) (6.155) 259 Dynamic Analysis of Switching Converters Steady-state or DC terms are: = -(£>, + £> 2 )X20 + Diu i0 , (6.156) = (A+D2)x,o-^, < 6 - 157 > and x,o=(w 1 o-x 20 )^. ( 6158 > Dynamic or AC terms are: = -(Z>i + D 2 )x 2 + (hio - x 20 >/i ~ X20 ^ 2 + D, " u (6.159) C^= (D, +2> 2 )3c, -? + *,otfi +d2), (6160) a/ -K and jj-r [D|(«i - x 2 ) + (u,o - x 20 y,]. (6161) Xi "2L/ 5 Equations (6.156) to (6.158) can be manipulated to yield the DC voltage conversion ratio for the discontinuous-mode buck converter. Equating Equations (6.157) and (6.158) to eliminate x 10 yields X2o _ («io - x 2 q)I>i (6.162) R(Di+Dz). 2Lf s A quadratic equation results after substituting (D x + D 2 ) = (DiU 10 /x 20 ) from Equation (6.156) into Equation (6.162) ^x| + x 2 o«,o-^ = 0. (6163) The DC voltage conversion ratio, M, is M = ^ = 2 (6-164) M 'o 1 + yj\ + (SLfs/RD 2 ) 260 Power-Switching Converters which is similar to Equation (2.39) after substituting R from Equation (2.31). From Equation (6.164), M+M 'lm +I=2 - Solving for D\ yields (6.165) D\=M 2Lf s ' R(\ -M)' Then, from Equation (6.156) (6.166) 2Z/ S Di+D2= li D,= j4 M ]lR0-M) VRV-My 2Lf s (6.167) The DC inductor current, x i0 , is found by substituting the voltage conver- sion ratio, M, and Dj into Equation (6.158) to yield x\o fu 10 .\ My/ 2Lf s /R(\ -M) = X2 °fe"V Ws X2 °\M ) ^2Lf s R(l - M) or *io = x 20 1 -M 2Lf s R- (6.168) (6.169) Substituting the DC voltage conversion ratio M, D\, and (Di + D 2 ) into Equation (6.159) yields 0=- 2Lf s R(l - M) X 2 + JC20 fel-l\d l -X20d2 + Mj- 2L/ S i?(l - M) «, (6.170) = _, I-JVL-SC2 + xJ-^-'d, - x 20 d 2 + mJ J^'^u i . (6.171) R{\ - M) M R(l - M) Dynamic 'Analysis of Switching Converters Solving for d 2 261 2L/ S Substituting D x and Af into Equation (6.161) yields 1 «,. (6.172) x\ 2Lf s -if&*-» + «(£- , H (6.173) or *i Af „ . .^ * 20 P l\ V2I/ S /?(1-M) 2L/ S (6.174) or xi = — + - M . X20 1 - M j y/2Lf s R(l - M) 2Lf s M M -.U\. y/2Lf s R{\ - Af) Substituting (£>i + D 2 ) and jci into Equation (6.160) yields (6.175) c d*2 = 2I/s d/ V^ 1 --^) 1 M y/2Lf s R(\ - M) ft-*>+^(i-'> - -£-K2+*2o(<*l + <&) (6.176) or djc 2 Af „ ... *2o / I -^5 . ! *, +X2 °)l 1 2m^ i + ' d2 )' (6.177) 262 Power-Switching Converters or ,d£ 2 _ 1 x 20 /i- ' dr R(M- \) Xl M ]J2l^R {l + M)di + M . /l R(l-M) Ul+X20 p - M h. 2Lf s R (6.178) Because /1-M- 2Lf s R /l-M [ /1\ / 2L/ ] M) •JC2- 1-M M x 20 a/ /?(i - My dx (6.179) or *20 &--(s)* + 5&--* + 7*- <«"» then, ^d.x 2 _ C At ~~ 1 11- *20 ft -M i?(M - 1) J?J "' ' M y 2Lf s R [(1+M) or „d* 2 12-M. 2x 2 o C-r- = — — -X 2 + dr RM-Y {\ M~ M2-M„ M A/ 2L fs R R \-M (6.181) (6.182) Eliminating x 10 and 5t { in Equation (6.160) and taking the Laplace transform yields fii(*)=[- sRC(l - M) JL1 X2(S) M{2 -M) M\ 2x 20 IR(\ - M? M 2 (2 - M) V 2Lf s di(s). (6.183) 263 Dynamic Analysis of Switching Converters Equation (6.183) can be used to draw a linearized equivalent circuit for the discontinuous mode buck converter. Let [18] JX = 2^20 1 -M 2Lf s R' n - M yilfsR 2Lf s R ' r 2 = R{\ - M), 1 M 2 gi R{1-MY and g2 = M (2-Af) R (\-M)' (6.184) (6.185) (6.186) (6.187) (6.188) (6.189) Using the above parameters, a linearized equivalent circuit for the discon- tinuous mode buck converter is shown in Figure 6.44. 6.2.9.3 State-Space Averaged Model for a Buck Converter with a Capacitor ESR Figure 6.45 shows a buck converter with an output filter capacitor that has an equivalent series resistance of R^. With the assumption of ideal elements except for the output filter capacitor, two switched models are shown in Figure 6.46(a) and (b), respectively. Using Kirchoff 's voltage law in Figure 6.46(a), the state equation is M, = LX } + X 2 + J?esr CX 2 < 6 - 1 90 > Figure 6.44 A linearized equivalent circuit for the discontinuous-mode buck converter. 264 Power-Switching Converters R y z Figure 6.45 Circuit schematic of a buck converter with a R CST . L R y 2 (a) dTinterval *1 L + c -- -X2 > tsr :" yz (b) (l-d)Tinterval Figure 6.46 Switched models for the buck converter with a R^. and using Kirchoff s current law, the state equation is X 2 + /*esrC*2 *1 = Cx 2 + '■ R (6.191) for the interval when the switching transistor is switched on. Solving for x 2 in Equation (6.191), *2 = R :X\ - 1 dR^r + R) CiR^r+R) x 2 . (6.192) Dynamic Analysis of Switching Converters 265 Substituting x 2 from Equation (6.192) into Equation (6.190) and solving for x\ yields x\ = R^R R + «l LiResr + R)* 1 L(R esT + R) 2 L' (6.193) Equations (6.192) and (6.193) can be written in matrix form as -R ar R -R ia- UResr + R) URnr + R) R -1 CCR esr + /?)C( J Resr + *). Xl X2 Hoh (6.194) Similarly, applying KirchofTs voltage law to Figure 6.46(b), the state equa- tion is = Lk\ +X 2 + Res r Cx 2 . Using Kirchoff 's current law, the state equation is X 2 + ResTCx 2 x\ = Cx 2 + '■ R (6.195) (6.196) for the interval when the switching transistor is switched off. Equation (6.196) can be solved for x 2 to give *2 = R 1 7*2 C(i?esr + ^) CiResr + R) X 2 . (6.197) Substituting x 2 from Equation (6.197) into Equation (6.195) and solving for x 2 yields — ResrR Xl =-T77: 7-^*1 — R :x 2 . UResr+R) L(R esr + R) Equations (6.197) and (6.198) can be written in matrix form as -RResr -R (6.198) *i x 2 UResr + R) L(i?esr + R) R -1 C{R ttr + R) C(*esr + R) X\ \_X 2 [«ll- (6.199) 266 Power-Switching Converters Hi The state-space averaged state coefficient matrix is -R&R -ft A=A t d + A 2 (l -d) = A\=A 2 = UR^+R) UR&+R) R -I CiR^+R) C{R„,+R)J The state-space averaged source coefficient matrix is . (6.200) B = B t d+B 2 (l -d) = (6.201) State-space averaged equations for the buck converter with an output capacitor R ssr in matrix form are *2 which yield — ResrR -R UResr + R) L{R esi + R) R -1 C(R esl + R)C(R esr + R) x\ X2 4- d/L M (6.202) — RestR R d X 2 + T U U UResr + R) HResr + R) L and X2 R xi x 2 C(R esr + R) CiR^ + R) Equation (6.203) can be rearranged to yield au\ = Lx\ +-r-r ™ x i R (R eS r + R) (Rest + R) X2 (6.203) (6.204T 3 (6.205) I or dt/j = Lk\ + y 2 , where y2=^^ + T^^-(^//R')x l+] Rx * (R esT + R) (Rm + R) (R esT + R) (6.206) (6.203) Dynamic Analysis of Switching Converters 267 is the voltage across the load resistor, R. Equation (6.204) can be rearranged to give X\ = CX2 + (X2 + /?esrC*z) R (6.208) Equation (6.206) is a consequence of the Kirchoff's voltage law while Equation (6.208) is a consequence of the Kirchoff's current law. A nonlinear continuous equivalent circuit can be drawn based on Equations (6.206) and (6.208). This is shown in Figure 6.47. The next step is to linearize the state- space averaged equations given in Equations (6.203) and (6.204). The per- turbed state-space averaged equations are dJc 2 -RexRiXM + i, ) R[X2Q + x 2 ) j_ (P + ^Xmiq + mQ L dt LiRe* + R) UResr + R) and dx 2 R(xio + xi) dt (x 2 0+X 2 ) dR^ + R) CiResr + R) The DC or steady-state terms are = -ResrR HResr + R) *10 — HR^ + R) *20 + Du w and = R dRcsr + R) X\0~ *20 C^csr + i?)" (6.209) (6.210) (6.211) (6.212) Ft y 2 Figure 6.47 A nonlinear continuous equivalent circuit for the buck converter with a R„ 268 Power-Switching Converters The dynamic or AC terms are "dT = L(j? esr +j?) JCi -z.(/? esr+ /?) JC2+ ^r + ^r (6213 > and dx 2= R x 2 (6 2\d\ dt CiR^ + R)* 1 CiR^ + RY K " } From Equation (6.21 1), Dut0 = vtrRf" + vdrR) X2 ° = n (6215) which yields the output voltage across the load resistor. From Equation (6.212), x 20 = Rxw (6.216) which indicates that the DC voltage across the capacitor is equal to the product of the DC current and the load resistor. Equation (6.209) can be rearranged to yield Rxj Du x + du 10 = Lx, + (R esr //R)x 1 + — f^r = Lx x + y 2 (6.217) while Equation (6.210) can-be rearranged to give CJC2 = r£^r Xi -r^Tr X2 - (6218) A linearized continuous equivalent circuit for the buck converter with an output capacitor R^ can be drawn using Equations (6.217) and (6.218). This is shown in Figure 6.48. This linearized continuous equivalent circuit is similar to the linearized continuous circuit for the ideal buck converter shown in Figure 6.4 1 , except that the output capacitor is replaced by an ideal capacitor in series with an equivalent series resistance, 7*^. Figure 6.49 shows the linearized equivalent circuit using a DC transformer with a turns-ratio of D. 6.2.9.4 State-Spae& Averaged Model for an Ideal Boost Converter Figure 6.50 shows an ideal boost converter with a source variable u 2 to simulate the load current modulation. With the assumption of ideal circuit w ii Dynamic Analysis of Switching Converters 269 *i + :« y 2 Figure 6.48 A linearized continuous equivalent circuit for the buck converter with a Rcsr- R y 2 Figure 6.49 A linearized equivalent circuit using DC transformer with a turns- ratio of D. — 3»- ©- M,Os C -r *2 < R "2 Figure 6.50 Circuit schematic of an ideal boost converter. elements, two switched models are shown in Figure 6.51. The state variables for this boost converter are chosen as the inductor current, x u and the capacitor voltage, x 2 . In the dT interval, state equations are Ml =Ufc, ( 6 - 219 > according to Kirchoff's voltage law and u 2 = CX2 + X2 R (6.220) WM 270 Power-Switching Converters m m (a) dT interval mi 1 (b) (1-d)7"inlerval Figure 6.51 Switched models for the ideal boost converter. according to Kirchoff's current law. The state equations in matrix form are During the (1 - </)r interval, the state equation using Kirchoff's voltage law is mi = Uiri + x 2 (6.222) and the state equation using Kirchoff's current law is Xl+U2 = Cx 2 +%. (6-223) These state equations can be expressed in matrix form as [s]-[.?c^ffi,][s]-[ , i i ./°c][:]- <**» m Dynamic Analysis of Switching Converters Applying state-space averaging, the state coefficient matrix, A, is 2=A\d + A 2 (l-d) = RC d + H RC (l-d) 271 (6.225) or A = d-rf) L C L L RC The averaged source coefficient matrix is B=B l d + B 2 (l-d) = i ° d + i ° o c d-d) (6.226) (6.227) or B = i ° ^ State-space averaged equations in matrix form are r*il_ [ ° -{\-d)/L}\xA [xz\- [Q-dyC -d/RC) \[x 2 \ + ri/L o ][»■] [ o i/cj[ M2 J (6.228) (6.229) X\ x 2 . -(1 ~ d)x 2 L (1 - d)x t x 2 C RC + L U2 CJ (6.230) From Equation (6.230), the two nonlinear state-space averaged equations are -(1 -d)x 2 , 1 ... ■ (6.231) or x\ = "i + L Ul (l-d) (1-d) X\ +X2 (6.232) 272 and Power-Switching Converters k ^ (1 -d)xj x 2 u 2 2 C RC C (6.233) or u 2 (l-*0 + x, = ■X 2 + X2 0-d) R(i-dy (6.234) From Equations (6.232) and (6.234), a nonlinear continuous equivalent circuit can be drawn, as shown in Figure 6.52. The next step is to linearize the nonlinear continuous Equations of (6.231) and (6.233) into a set of linear continuous equations. Applying small-signal approximation to Equations (6.231) and (6.233) yield and die, -(\-D-d), . x 1, -£- = £ (*20 + x 2 ) + — ("10 + "i) dx 2 (\-D-d), . x \ , . . 1 . -d7 = C i^+x x -)-—{x 20 +x 2 ) + -u 2 , (6.235) (6.236) assuming that w 2 consists of only the modulation term. Neglecting AC cross- product terms, the above equations can be simplified to die, -(1 - D) . d 1 _ -df = — — X2+ L X20 + L U 1 -D 1 ■JT X20 + L UW (6.237) Figure 6.52 Nonlinear continuous equivalent circuit of the ideal boost converter. Dynamic Analysis of Switching Converters 273 and dJc 2 (1 - D) . d 1 . 1 . (1 - £>) _J_ X20 . (6.238) The steady-state or DC solutions are 0= _O-£) X2o + «J0 (6239) and = ii^x IO -^. (6.240) Equation (6.239) can be simplified to yield x\o _ 1 u 20 (1 - £>) (6.241) which is the DC voltage conversion ratio for an ideal boost converter. Equation (6.240) can be rearranged to give X\0 = **!* (6.242) (1-Z>) or *„ = "'° 2 , (6-243) /?(1 - Z>) 2 which is the DC or average input current of the ideal boost converter. The dynamic or AC solutions are L^p- = -(1 - D)x 2 + dx 20 + «i (6.244) at and C^ = (1 - D) Xl - x i0 d - § + "2- (6-245) 274 Power-Switching Converters The small-signal averaged state-space equation for the continuous- conduction mode boost converter is (\-D) (1 - D) L 1 RC r X2 ° i n l x + L *10 d + I ° 1 L c J ia- (6.246) Equation (6.246) shows that the system has three inputs. u x and u 2 represent the perturbations of the input voltage and the output current, respectively, d represents the perturbations in the duty cycle; this would be modified by the control variable in a closed-loop system. A linearized equivalent circuit can be obtained by rearranging Equa- tions (6.237) and (6.238) to give (1-D) , x 2 pd x\ = — x 2 + — ^r + 1 (1 - D) (1 - D) Ml (6.247) and (1-D) X2=X\- x\od 1 X2 -U 2 . (6.248) A linearized equivalent circuit of the ideal boost converter based on Equa- tions (6.247) and (6.248) is shown in Figure 6.53. The dependent voltage source x 20 d/{l - D) and the dependent current source x l0 d /(l-D) are due to modulation in the duty cycle, i.e., d. A linearized source-reflected equivalent circuit for the ideal boost converter can be found by manipulating Equation (6.247) to preserve u u x\, and L. Equation (6.247) becomes Figure 6.53 Linearized equivalent circuit of the ideal boost converter. Dynamic Analysis of Switching Converters Lx\ = -x 2 {\ - D) + *2od + mi - Equation (6.248) can be manipulated to yield -[JC 2 (1 - #)] = X, - — — + «2 (!-»)" (1-Z)) i?(l--D) 2 U--D)' 275 (6.249) (6.250) since the output voltage state variable is x 2 {\-D). Equation (6.249) repre- sents the Kirchoff's voltage law while Equation (6.250) represents the Kirchoff's current law for the linearized continuous equivalent circuit. Figure 6.54 shows the source-reflected linearized equivalent circuit for the ideal boost converter. A load-reflected linearized equivalent circuit can be found by manipu- lating Equation (6.248) to preserve output variables of u 2 , x 2 , C, and R. This can be attained by multiplying (1-Z>) to both sides of Equation (6.248) CJc 2 = x,(l-D) X2 R - xiod + u 2 . (6.251) It can be seen that the inductor current is now defined as x, (1-X>) instead of Xi- Thus, Equation (6.247) must be modified to yield (1-D) ,*,(! -J»=--*2 + (rTB) + (f3lD)- Mi _ x 2 od (6.252) A load-reflected linearized circuit using Equations (6.251) and (6.252) is shown in Figure 6.55. The source- and load-reflected linearized equivalent circuitsr can be combined into a single equivalent circuit as shown in Figure 6.56 using a DC transformer with a turns-ratio of 1/(1 - D). Figure 6.54 Source-reflected linearized equivalent circuit for the ideal boost converter. 276 Power-Switching Converters a© 1-D (1-D)2 x,(1-0) *2 <|>^io2(j) % Figure 6.55 Load-reflected linearized circuit for the ideal boost converter. Figure 6.56 DC transformer equivalent circuit for the ideal boost converter. 6.2.10 Switching Converter Transfer Functions From the results of state— space averaging, transfer functions of the switching converters can be readily obtained using Laplace transformation. Transfer functions are useful for dynamic analysis of the switching converter. The transient response due to input supply perturbation of the switching con- verter can be found from the input voltage susceptibility transfer function. On the other hand, the transient response line to load modulation can be found from the output impedance of the switching converter. The open-loop transfer function is first used to predict the margin of stability of the switching converter. Loop compensation is then employed to improve the stability of the switching converter. 6.2. 10.1 Source-to-State Transfer Functions From the results of state-space averaging, the perturbed state-space averaged equation can be written as x = A x + B u + Ed (6.253) where A = A t D + A 2 (l-D) (6.254) Dynamic Analysis of Switching Converters ^ 77 Bo = BiD + B 2 (\ - D) (6.255) and E = (Ai - A 2 )x + (B t - B 2 )uo- (6.256) Applying Laplace transform to the perturbed state-space averaged Equation (6.253) sX(s) = A X(s) + B 1/(5) + Ed(s) (6.257) or (si - A )X(s) = Boms) + Ed(s), (6.258) where / is the identity matrix having the same dimension as A . Equation (6.258) can be rearranged to yield X(s) = (si - AoT 1 Bo U(s) + (si - A y } Ed(s). (6-259) In the above equation, ~d is usually a function of x and u. The dependency of d(s) on X(s) and U(s) is called the control law. Since ~d is a function of x and u, the control law is usually nonlinear. The linearized control law can be expressed as [19] d(s) = F T (s)X(s) + Q T (s)U(s), (6-260) where F T (s) and Q T (s) are coefficient matrices. Substituting Equation (6.260) into Equation (6.259) yields X(s) = (si - AoT^Boms) + E[F T (s)X(s) + Q T (s)U(.s)]). (6-261) or X(s) = [si -A - EF T (s)T i lBo + EQ r (s)]U(s). (6.262) Thus ^ = [sJ _ A - EF T (s)T i (B + EQ T (s) ) (6-263) U(s) 278 Power-Switching Converters is the transfer function matrix relating the state variables to the source variables for a closed-loop switching converter [19]. Derivations of the source-to-state transfer functions for the buck and boost converters are illustrated below. 6.2.10.1.1 Buck converter. The perturbed state-space averaged equations from Equations (6.121) and (6.122) can be rewritten to yield the form of Equation (6.253) as follows: The coefficient matrices are A [ -(1/Z.) 1 [i/c -a/Roy (6.265) and *-[T]- ■-ftr]- (6.266) (6.267) In a closed-loop converter, the control law describing the voltage-mode PWM controller shown in Figure 5.3(a) is in the form of [19] d(s)- V e (s) [1 + H{s)] V R (s) - H(s)X 2 (s) (6.268) where H(s) is the transfer function of the error amplifier and its compensa- tion network, V R {s) is the transfer function of the reference voltage, and V p is the peak amplitude of the sawtooth signal. Since the reference voltage is normally a fixed DC value, the modulation in duty cycle can be expressed as d(s) = H(s)X 2 (s) (6.269) The coefficient matrices for the control law are "»-[-^l (6.270) Dynamic Analysis of Switching Converters and Q T (s)=[0 0]. From Equation (6.263), the state variable matrix is uwH(s)~ 279 (6.271) X 2 (s a- i+ 1 ."* S+ RC J D/L Wi(s)] (6.272) or (6.273) \s + (l/RC) -«u w H{s)/LV p ) + (\/L))\ \D/L\ -^ [JfiWl L */ C f 1L2J . L X 2 (s) J ~ s 2 + (s/RC) + ( 1 /LQ + (w 10 H(s)/LCV p ) The transfer functions relating the state variables to the source variables for the buck converter are X«s) (D/L)[s+(l/RQ\ I/,(-0 s 2 + {s/RQ + (1/Z.Q + (moH (j)/LCK p ) and X 2 (s) (D/LC) Uds) s 2 + (s/RC) + (\/LC) + iu w H{s)/LCV v ) ' (6.274) (6.275) 6.2.10.1.2 Boost converter. The perturbed state-space averaged equations from Equations (6.237) and (6.238) can be rewritten to yield the form of Equation (6.253) as follows: r*il_r ° — (d — Z>>/Z0"| I" jc, "I [* 2 ]-[(i-2>)/c -V/RC) \[xz\ [1/L ][«,][ *2o/L V d + [ 1/cJ [u 2 \ + [-(x.o/Oj From the above equation, the coefficient matrices are r _((!_£>)//,)-] a °-[(i-d)/c -v/rc) y (6.276) (6.277) 280 Power-Switching Converters and * 0= [ 1/Cj' L-(xio/oJ" (6.278) (6.279) The source-to-state transfer functions for the boost converter can be obtained by substituting Equations (6.270) and (6.271) into Equation (6.262). The state variable matrix is X,(. X 2 s 1- 1-.P x 2 qH(s) L LV D f l_\ x P l0 H(s) ■ \ RCj CV P -1 n i - L 1 — L CJ (6.280) Taking the inverse matrix, 2(S)J ~ A- 2 (. ^ 1 * 10 Z/(.s) RC CV p -(1-D) jc 2 o#(*) LV„ p - I) /, 1 (J s*+([s- {sxi H(s)R/V p )]/RC) + ((l-Df/Le) + (x 20 H(s)il -D)/LCV p )' (6.281) Since the input and output variables of the boost converter are x\ and x 2 , respectively, the transfer function relating the state variable, x\, to the source variable, 1*1, X\{s)IUi(s), is the input admittance of the boost converter ■T|(J) = U t (s) (\/L)[s+{l/RC)-{x l oH{s)/CV p -)] s 2 + (j[l - (x 10 H(s)R/ V p )]/RC) + ( (1 - Z>2)/£C) + (x 20 # (*)(1 - D)/LCV P ). (6.282) . 281 Dynamic Analysis of Switching Converters Substituting x w =u 10 /R(i - Df from Equation (6.243) and x 20 =u^{\ - B) from Equation (6.241) into the above equation to yield Ui(s)' (l/L)[5+(l/^Q(l-(».o//(5)/K p (l-£>) :! ))] JMs/RC) [1 - (u w ti(s)l K p (l - Df)} + ((1 - Df/LC) [l + (u n H (*)/ K p (l - Z>) 2 )] ' (6.283) The output current susceptibility, X l (s)/U 2 {s), for the boost converter is U 2 {s) -((1 - D)/LC)[\ + (»,q//(s)/K p (1 -J)) 2 )] ^ + (s//JC)[l - («.oWW/K p (l - Z>) 2 )] + ((1 - Df/LC) [1 + (ii.o/ZW/l'pO -^) 2 )] " (6.284) The input voltage susceptibility, X 2 {s)/U l (s), is X 2 (s) _ ((1 -D)/LC) s* + {s/RC)h - («,oWW/K p (l - £>) 2 )] + ((1 - Df/LC) [1 + («,o//(*)/ K p (l - Df)] (6.285) The output impedance, X 2 (s)/U 2 (s), is *>C0 _ 1/ 2 (j) WO 5* + (s//JC)[l - ( Ul0 //(5)/K p (l -D) 2 )] + ((1 - /?) 2 /^C)[l + {u x0 H(.s)/y p 0-Df)}. (6.286) 6.2. 7 0.2 Open-Loop Transfer Functions The stability of a linearized switching converter can be evaluated by examining its open-loop transfer function using Bode plots for adequate gain and phase margins. To find the open-loop transfer functions, the feedback loop can be mathematically opened by replacing the transformed 282 Power-Switching Converters AC state vector, X(s), with an independent test vector, V(s), in the control law given in Equation (6.260) to yield [20] d{s) = F T V(s) + Q T (s)U(s). (6.287) The open-loop transfer function matrix, j$, is found by combining the above modified control law equation with Equation (6.257) with U(s)= to yield V(s) = (si -A o y* E(s)F r (s). (6.288) For a negative-feedback system with touching feedback loops, the overall open-loop transfer function, G(s)H(s), is the sum of the diagonal elements of the open-loop transfer-function matrix, -(X k {s)/V k (s)). Thus, the open-loop transfer functions for the buck and boost converters are 6.2. 10.2. 1 Buck converter. The open-loop transfer-function matrix of the buck converter can be expressed as I***) J = l-d/o s+(i/ro\[o o J[k 2 (5)J (bU ™ } or [X 2 (s)\ \s+(l/RQ -(1/Z.)1[0 -(u w H{s)/LV v )}\V x (s)} •)] [ i/c s |[o o \\.VM\ (6291) s 2 +{slRC) + (\/LC) Since ^(.sy^iCs) — 0, then the open-loop transfer function for the buck converter is G(»=-|, < 6 - 292 > or GtsiHis) = u "> H W CLV r . (6.293) wmw s2 + {s/RC) + (1/LC) Dynamic Analysis of Switching Converters 2 ° 3 6.2.10.2.2 Boost converter. The open-loop transfer-function mat- rix for the boost converter can be expressed as *,(,)! r s (l-DVLl-'rO -{xjaHWLVMVAsft xM = [-((\-D)IC) s + (l/RC)\ [0 x l0 H(sycV p \[v 2 (s)\' (6.294) or \s+(l/RC) -((1 - D)/L)] [0 -(x 20 i/(*)/LK p )l [ F,(s)l rr,(5)l [d-PyC s ][0 x w H(s)/CV v j[n(j)J tftC5J ~ J 2 + <*/*C) + (d - 5) 2 /iQ (6.295) From Equation (6.289), the open-loop transfer function for the boost con- verter is -,„,,. {H(s)u l0 /CV p R(l - D) 2 )[(R(l - Df/L) - 5] G(s)//(5) = * + WRO + ({l-DY/LO using the relationships from Equations (6.241) and (6.243). It can be seen that the open-loop transfer function of the boost converter includes a right- half-plane zero. This is because the output current in the boost converter decreases as its duty cycle increases. The right-half-plane zero complicates loop compensation in the boost converter since it introduces an additional 90° phase lag. The loop gain of the compensated boost converter is usually forced to roll off at a relatively low frequency with a concomitant decrease in its unity-gain crossover frequency. Thus, in general, the voltage-mode PWM compensated boost converter has inherently narrow bandwidth, and thereby, relatively poor frequency response. 6.2. 10.3 Loop Compensations in Buck Converter As discussed previously, loop compensation involves the selection of the transfer function of the error amplifier, H(s), to shape the frequency response of the switching converter. In some cases, it is possible to satisfy performance specifications of the switching converter by simply adjusting its open-loop gain-factor. This is also known as gain-factor compensation. Assuming that the transfer function, H(s), is equal to a constant, K. The transfer function of the buck converter with gain-factor compensation or a 284 Power-Switching Converters proportional control scheme can be found from Equation (6.293) as fol- lows: G{s)H(s) = u l0 K/CLV p s 2 + (s/RC) + {\/LC)' (6.297) Figure 6.57 and Figure 6.58 show the magnitude and phase responses of the buck converter with a 16mH output inductor and a 100 p.F output capacitor for several values of load resistance, R. As shown, the magnitude response has a constant gain of 20 log, {u x0 K/LCV^ with a minimal phase shift at low frequencies. Beyond the corner frequency of 1 /lir^LC, the magnitude response begins to decrease with a slope of —40 dB/decade and the phase tends towa rd — 180 c . The magnitude resp onse is overdamped when R < y/L/C , und erdamped when R > y/L/C, and critically damped when R = (i/2)y/L/C. The underdamped open-loop buck converter changes its phase rapidly at the corner frequency as shown in Figure 6.58. A more gradual phase transition is observed for the overdamped open-loop buck converter. Since the open-loop phase lag is close to 180°, any additional phase lag can render the buck converter unstable when the loop is closed. •■= -40 -60 -80 0.0001 0.001 ■ ! ' 1 1 |ii; ; i i ■ ! ■! V i I i ! ' ! Mi 1 I I ! i \ 'M * i t s it U j i ! • ° I M i = i I : H=- ' ^ n ■ H h I ! n Hill 1 ! n hj-i = ■ l n i Mi * M u i: [ iiiiii i 1 !i!;;i 1 i iiiili i l - ■ : t iiii ; * ? - i - ii ■ i — i i i ; i! 0.01 0.1 1 flf 10 100 1000 Figure 6.57 Magnitude response of an open-loop buck converter for several || values of y/L /C - Dynamic Analysis of Switching Converters 285 0.0001 0-001 Figure 6.58 Phase response of an open-loop buck converter for several values of The transfer function for a lag-compensator is S + lO p (6.298) where w p is the pole angular frequency of the lag-compensation network. In general, to p must be low enough to achieve a sufficient gain margin. Substi- tuting Equation (6.298) into Equation (6.293) yields the transfer function for a lag-compensated buck converter G(s)H(s) = K'io p *> 2 (s 2 +2C<o s + w 2 )(s + o p y (6.299) where £= \/(2Ry/cJL) is the damping ratio, ta is the natural angular frequency, and K = Ku i0 fV p . Figure 6.59 and Figure 6.60 show the magni- tude and phase responses of the buck converter with a lag-compensator for a pole frequency of 0.01 x/„. As can be seen, a lag-compensated buck con- verter has a narrower bandwidth compared to that of the open-loop buck converter at the expense of an increase in stability. In practice, the lead-lag compensators shown in Figure 6.15 and Figure 6.25 are employed for loop compensation. 286 Power-Switching Converters S -20 S -40 ! 1 : \ i ^""^^L = ' • ' ' ' I ■ ' ' • -•■!■• ! ■ T^s^t : ; ;A j ! iijii ! { j \\ j ^^^^i ; . \l\ \ ; i 1 1| i i j .; i u ! i M ! 1 1 I [ \ \ \ i L J_i ' ■ M ! : .••: : ■ "•.' ' \' . ',' ! I ) M if I i I j l M M » i ■ i ■ \ • i i j ; i ! );■):!• ; I M :• M J I ; j ^ i ) i ; i i __1!.[1[!1._ ! lUJ!jII 1 [.lift. LiM M M iiii ! i ; n iill : ! i ; ; ; ;i i ! NiMH i i ; :;iil i '■ \ \\ -11 i ' n imi ; ; I .Mil 0.01 k 0.1 4 10 f p fit Figure 6.59 O.Ol/o. Magnitude response of a lag-compensated buck converter with/ p = 6.2.11 Complete State Feedback An important application of the state-space representation is the complete state feedback of the switching converter. All the states of the converter are sensed and multiplied by a feedback gain. This technique allows us to calculate the gains of the feedback vector required to place the closed-loop poles at a desired location. 6.2.11.1 Design of a Control System with Complete State Feedback [9] Consider a continuous-time linear system, having the following state- space representation: x = Ax + Bu. (6-300) A usual control strategy is to generate the error signal as a function of the measurements of the states of the system. In case of a switching converter, the control variable, u, may be chosen proportional to the states as u=-Fx. < 6 - 301 > Dynamic Analysis of Switching Converters 287 -30 r- -60 s -^o - » -150 - -240 til. Figure 6.60 Phase response of a 0.01/ o . compensated buck converter with f p = Then x = {A - BF)x. (6.302) The closed-loop eigenvalues are found by solving the characteristic equation: det[sl - A + BF] = 0. Several observations are • If the state vector has dimension i and the control vector has dimen- sion j, the matrix F will have i x j elements. . If the system described by (A,B) is controllable, the choice of the elements of F will control the position of the closed-loop poles on the S plane. . If the elements of F are real, the closed-loop poles will be real or complex conjugates. . If the applied control is of scalar type, the resulting F is a row vector, having i elements. The elements of F are unique if the i roots of the characteristic equations are-Specified. 288 Power-Switching Conveners * The closed-loop poles can be arbitrarily placed by choosing the elements of F. 6.2.11.2 Pole Selection One way of choosing the closed-loop poles is to select an ith order low- pass Bessel filter for the transfer function, where i" is the order of the system that is designed [21]. The step response of a Bessel filter has no overshoot; thus, it is ideal for a voltage regulator. The desired filter can then be selected for a step response that meets a specified settling time. The minimum settling time should be chosen to avoid saturating the control variable. The desired closed-loop poles of the filter, ^s = {P\,P7.} (6.303) can be designed with the aid of the filter toolbox that comes with MATLAB [22] or with any other filter package, like Filter Wiz® [23]. 6.2.11.3 Feedback Gains The values for the elements of the feedback vector F can be obtained by pole placement. The MATLAB command, F= PLACE (A, B, F), can be used to compute the state-feedback matrix /"to yield the eigenvalues of (A — B F) as specified in vector P. Example 6.6. A buck converter designed to operate in the continuous conduction mode has the following parameters: R = 4Cl, L=1.330mH, C=94u.F, F s = 42 V, and V a = 12 V. Calculate (a) the open-loop poles, (b) the feedback gains to locate the closed-loop poles at P= 1000 x {—0.3298 + O.lOf -0.3298 - 0.1 Oi, (c) the closed-loop system matrix A c ^. Solution. (a) The state-space matrices during t on are 1 1 \_ C L 1 RC B, = The state— space matrices during f jr are _1_ ~L ]_ 1_ C RCi A 2 = B 2 = Dynamic Analysis of Switching Converters The state-space averaged model matrices are A=Ai xD + A 2 *(l-D), 289 B = B x x D + B 2 x (1 - D). Then 1 - ' D L , B = L 1 1 .0 c RC. The open-loop poles can be found by the MATLAB command to yield polesoL = eig(A) to be polesoL = 1000 x {- 1.3298 + 2.4961 i, - 1.3298-2.4961/} (b) The equations for the linearized AC small-signal model are xi -(-x 2 +Du + dU), Then, the small-signal averaged state-space equations are The following MATLAB script can be used to define a state-space model sysOL and plot the step response of the open-loop converter: sysOL=ss(AB,C,0) step(sysOL) where A is the system matrix, B is [D/L 0]' and C=[0 1]. Figure 6.61 shows the transient response of the small-signal model of the converter for a step input atwi. To design the control strategy, first assume that the perturbations in the input DC voltage are null, i.e., u = 0. Then, i = Ax + Ed with £ = ~U~ L mm ■■Is 290 Power-Switching Converters Step Response From:U(1) 4 4.5 x 10-3 Figure 6.61 Step response of the linearized buck converter. for voltage-mode control d = (i>/K re r) v re r- If we apply complete state feedback v re r = -Fx then x — Ax + E (-£») or *-(*-«£'> The closed-loop system matrix is then D Acl=A-E——F. Viet Dynamic Analysis of Switching Converters To locate the closed-loop poles at P= 1000* [-0.3298 + 0.101 -0.3298 - 0.10i]', we calculate the feedback gains as P = 1000 x [-0.3298 + O.lOi - 0.3298 - 0.10i]' F = place \A,E—,p\ Then, F= {-2.6600 -0.3202}. (c) The closed-loop matrix is Aci.=A-E-£-F, - .[0.2000 -0.0511] Acl - le4 1^ j 0fi3g _ 2660 J we can check the locations of the closed-loop poles with eig(A c &, which gives ans = le+ 2 x [-3.2980 + l.OOOOi - 3.2980 - l.OOOOi] Figure 6.62-displays the schematic circuit of the closed-loop buck converter used for the simulations. The parameter loop changes from to 1 in the pwro I?' VON = 1.0V S VOFF=O.OV ROFF=1e6 RON = 0.05 (H%I W)> V(%IN 2),0.1) . ■ * — ■ control pwm„oul V, = Vj=10 TD = "IB = 99.9 u TF = 1n -*-„ PW=1n PER = 0.1m -0.3202 9^ 2.6600 -V *t Mn) *<- 3 Figure 6.6£ PSpice schematic of the switching converter under study. Hi 292 Power-Switching Converters parametric simulation to obtain the open-loop and the closed-loop responses, respectively. The turn-on transient of the switching converter is shown in Figure 6.63 for the open-loop and the closed-loop converters. Notice that the open-loop response overshoots the steady-state output volt- age, while the closed-loop response shows the behavior of a second order system with real poles. The dynamic of the tum-on transient does not necessarily correspond to our previous calculations because this is a large signal swing not modeled by the linear small-signal approximation. A small perturbation is added to the input voltage source at 5 ms; at that time, the input voltage changes from 42 to 44V to simulate a line transient. Figure 6.63 shows that the open-loop system evolves to a new steady-state voltage after overshooting. The perturbation in the output voltage of the closed-loop switching converter is hardly noticed. Figure 6.64 displays an expanded view of the output voltage transient at 5 ms. The closed-loop switching converter follows the calculated dynamic response for the small- signal model. 6.2.12 Input EMI Filters Switching converters, in particular buck or buck-boost converters, have a notorious reputation as one of the worst electromagnetic interference (EMI) generators due to its pulsating input current waveform and switching actions of its semiconductor switches. Electromagnetic interference is the Os 0.5 4.5 5.5 Time (msec) 6.5 7.5 8.5 9.5 Figure 6.63 Transient response of the open-loop and closed-loop converters. Dynamic Analysis of Switching Converters 12.602, 293 12.000 11.104 Closed loop r n ft A/wwvvvywvvWvvwwvvvwvwv ww AAAA/V v '* * AAAA/i ' V V v f V 4.61 5.00 5.50 6.00 6.50 7.00 7.50 Time (msec) 8.00 8.50 Figure 6.64 Expanded view of the transient at 5 msec. unintentional generation of conducted or radiated energy. To preserve the integrity of the power source, an input EMI filter placed between the power source and the switching converter is often required. The major purpose of the input EMI filter is to prevent the input current waveform of the switch- ing converter from interfering with the power source. As such, the major role of the input EMI filter is to optimize the mismatch between the power source and switching converter impedances [24]. There are two conduction modes of EMI: common and differential. Common mode EMI is that component of noise current which exists on any or all supply or output lines with respect to a common ground plane such as chassis or ground return bus. The capacitance of the switching transistor insulator mounted on the chassis or ground plane is known to be a "culprit" for the common mode-coupling path. Differential mode EMI, also known as longitudinal mode EMI, occurs between any two supply or output lines. A principal source of the differential mode emission is the impedance of the input EMI filter capacitor. Another source of differential mode emission is the switching devices. The magnitude and spectral content of the EMI are often dictated by the reverse recovery characteristics of these switching devices. 6.2.12.1 Stability Considerations Figure 6.65 shows a circuit model for a buck converter with a second- order input EMI filter. As shown, the DC transformerized equivalent circuit 3H? 294 Power-Switching Converters Input EMI Filter ! Buck Converter Figure 6.65 Circuit model of a buck converter with an input EMI filter. of the buck converter shown in Figure 6.41 is used. The input EMI filter consists of an input EMI filter inductance, L u and an input EMI filter capacitance, Ci. For simplicity, the total effective impedance of the source, w,, is modeled as a single effective source resistance, R s . The effective source resistance, R s , consists of the source impedance and the series resistance of the input EMI filter inductor. In general, the values for U and Q are large enough to dominate the reactive impedance of the source. The output impedance of the second-order input EMI filter is given by Zemi = R s +ja>Li (1-w 2 CiZ.i)+./<w j R s Ci (6.304) By choosing Lj and Q sufficiently large, the interfering signals at the switching frequency and its higher harmonics of the switching converter can be adequately attenuated. The stability of a closed-loop switching converter with an input EMI filter can be found by comparing the output impedance of the input EMI filter to the input impedance of the switching converter. For a given load resistance, J? L , the controller adjusts the duty cycle to maintain a constant output voltage, and hence, a constant output power. Thus, if the input voltage increases, the input current must decrease to yield a constant input power. Consequently, the closed-loop switching converter exhibits a negative input impedance. The effective secondary-side impedance of the buck converter is RU/ l jwQ +jioL + Re, (6.305) where R e is an effective resistance that accounts for the series resistances in the output filter inductor and other components, and a "modulation" resistance that arises from the modulation of the switching transistor storage time [25]. It is a complicated function of these component resistances and _ 705 Dynamic Analysis of Switching Converters also of the duty cycle. From Figure 6.65, the input impedance of the closed- loop buck converter is the negative of the effective secondary-side impedance reflected through the DC transformer to its input at low frequencies. The input impedance of the buck converter is \RU/{l/j<oC ) +ja>L + R e ] (6 30 6 ) or where D is the duty cycle of the buck converter. At low frequencies, the input impedance is dominated by the output load resistance, /? L , and is given by 7 (**■ + **> (6.308) An ~~ D 2 At the resonant frequency of \/2vy/ZZZ, the input impedance is at its minimum and is given by 7 __^e (6.309) ^in- D 2- Above the resonant frequency, the input impedance increases inductively as 7 J™ L (6.310) The input impedance of the buck converter versus frequency is illustrated in Figure 6.66. The switching converter negative input impedance in combin- ation with the input EMI filter can under certain conditions constitute a negative resistance oscillator, and is the origin of the system potential instability. The input EMI filter output impedance is a small positive resist- ance at DC and low frequencies, but in the neighborhood of the filter resonant frequency its output impedance may be many times the associated Ohmic resistances, and if the magnitude of Z EM i increases sufficiently that the net circuit resistance becomes negative, oscillation will occur [25]. As such, the maximum output impedance of the input EMI filter, Z EM i,max, must be less than the magnitude of the input impedance of the switching converter to avoid instability [26]. Hence, 7 ^>7 < 6 " 311 > ^•'m -** "£-EMI,max- "Hi 296 Power-Switching Converters Figure 6.66 Input impedance versus frequency for a buck converter. To ensure stability, however, the poles of Zjn//Z EM j should lie in the left- hand plane. The above stability condition is only valid if the input EMI filter resonant frequency is below the frequency at which the input impedance of the switching converter begins to deviate from its low-frequency values. Thus, instability tends to occur at the resonant frequency of the switching converter since the input impedance of the switching converter is at its minimum. Also, the worst case for stability is at low input voltage since it requires a larger duty cycle that decreases the input impedance of the switching converter. The average power demand through the input EMI filter is practically constant for a constant switching converter load. Thus, the switching con- verter can be modeled as a continuous constant power element for low- frequency stability considerations [27], in accordance with the concept of state-space averaging as shown in Figure 6.67. The state variables are chosen as xi for the current flowing through the input EMI filter inductor and x 2 as the voltage across the input EMI filter capacitor. The state equations are wi = R s x\ + L\k\ + x 2 , (6.312) Dynamic Analysis of Switching Converters 297 Figure 6.67 Circuit model of switching converter with an input EMI filter, and x\ = C\x 2 + - X2 (6.313) Substituting Xj from Equation (6.313) into Equation (6.312), we have „ \ r dx 2 Pi . L d 2 x 2 P dx 2 + x 2 . (6.314) i/i d x 2 L x Ci = ~d~F W QxlJ dx 2 x 2 df L\C\ (6.315) The term, -(P/Qx^), is due to the negative input impedance of the constant power load of the switching converter. Routh-Hurwitz stability criterion can be used to determine the necessary and sufficient condition for stability from the sign and magnitude of the coefficients of the characteristic equation. From Routh-Hurwitz stability criterion, it requires that Rs> PLi Qxl (6.316) 2(min) It is clear that the input EMI filter inductance should be much smaller than the input EMI filter capacitance. A resistance in series with the input EMI filter inductor can be added to improve stability. However, it is undesirable to increase the series resistance of the input EMI filter to improve stability since it increases conduction losses. The series resistance is normally chosen to be three to five times the characteristic impedance of the filter, y/Li/Ci. However, the quality factor, Q, of the input EMI filter increases as the series resistance decreases. Also, the maximum output impedance of the input EMI filter increases as the quality factor increases. In order to avoid 298 Power-Switching Converters instability, it is necessary to utilize a low Q input EMI filter with the penalty of higher conduction losses. The nonlinear resistance associated with the constant-power element of the switching converter can be replaced by a negative linear resistance, -i? L , defined by -(x 2 2 /P). Figure 6.68 shows an equivalent circuit of a switching converter with an input EMI filter. The state equations are Mi = L\X\ + R s Xi + -ResrCl^ + *2, and x\ = C\ki + RcstCiX2 + X 2 (6.317) (6.318) Combining, rearranging, and assuming that Rj, <C R s and i? L -^ ^esr, the state equations can also be expressed as x\ {R s + J?esr) 1 1 X\ -— X2+ — Ui, and (6.319) MUSI C\ RlC\ x 2 . These state equations can be written in matrix form as I"*,"] _[-((*. + *»)/H) -(I/**) 1M [x 2 \-[ 1/C, -0/*i.C,)J|*iJ (6.320) (6.321) Figure 6.68 Equivalent circuit of a switching converter with an input EMI filter. Dynamic Analysis of Switching Converters 299 Then [5+(1/J?lC,) L -(1/Ci 5 + ((J? s + ^esr)/-Ll) im- uwi . . — — . [x 2 (s)\ ~ 52 + (((/? s + J R csr )/L,)+(l/ J RLC,))5 + (l/L,C I ) Routh-Hurwitz stability criterion required that * s + *esr *lQ >0. (6.322) (6.323) In practice, the input EMI filter with LR reactive damping shown m Figure 6.69 is used to reduce conduction losses. This filter has a -40 dB/ decade roll off beyond its resonant frequency at the expense of output impedance higher than its characteristic impedance. The Routh-Hurwitz stability criterion for this filter is [27] (6.324) Figure 6.70 shows an input EMI filter with RC reactive damping. The damping capacitor, C d , is usually chosen to be three times the filter capaci- tance, C,, to avoid the filter inductor, L lt from resonating with the damping capacitor at resonance. The damping resistor, R d , can be made to be equal to the characteristic impedance of the filter. As such, the RC reactive damped input EMI filter requires the use of a more expensive and bulky damping capacitor compared to the damping inductor of the LR reactive damped filter. However, the output impedance of the RC damped filter is generally lower than the characteristic impedance of the filter. In this configuration Figure 6.69 Input EMI filter witELR reactive damping. "IB 300 Power-Switching Converters -6 Figure 6.70 Input EMI filter with RC reactive damping. the capacitor is normally chosen with an ESR equal to Ra. The Routh- Hurwitz stability criterion for this filter is [27] *(■-£)(**-&) > Rl (6.325) The second-order input EMI filter may not provide sufficient attenu- ation and/or roll-off beyond the resonant frequency. A fourth-order filter with LR reactive damping shown in Figure 6.71 may be used to increase attenuation and roll-off beyond its resonant frequency. It is a good design practice to have different resonant frequencies for the two sections of the filter to avoid a sharp maximum in its output impedance and a sharp minimum in its input impedance at the resonant frequency. It should be noted that high-core losses in the input EMI filter inductor is desirable to dissipate the energy at the EMI frequency so as to prevent it from reflecting back to the power source. Otherwise, the EMI current would radiate and/or- couple into other circuitry. Figure 6.71 A fourth-order input EMI filter with LR reactive damping. Dynamic Analysis of Switching Converters 301 Example 6.7. The parameters for a buck converter are: input voltage = 1 V, average output voltage = 5 V, switching frequency = 1 kHz, L =lmH, C = 100u.F,.Re = 0.01 ft, and /? L = 5 ft. The input EMI filter has thefollowing parameters: Z., = 1 mH, C, = 1000 u,F, and R s = 0.001 ft. Plot the input imped- ance of the switching converter and the output impedance of the input EMI filter on the same plot. Determine if a potential stability problem exists. Solution. The magnitude of the input impedance of the buck converter can be expressed as > & " M -Bt^&*G? + *) 1+ *'( i --M^fe') J - and the magnitude of the output impedance of the input EMI Filter can be expressed as Zemi(g>) = / R2 * + V(l-^CiL, {toLtf i^dUf + (<wi? s C,) r 0.01 0.1 10 100 Frequency (Hz) 1000 10000 Figure 6.72 Input impedance, Z in ( /), of the buck converter and output imped- ance, Zemi(/)» of the input EMI filter. 302 Power-Switching Converters Figure 6.72 shows the input impedance of the buck converter and output impedance of the input EMI filter. As shown, the magnitude of the input impedance of the buck converter is always larger than the magnitude of the output impedance of the input EMI filter. Thus, the buck converter with the input EMI filter is stable. 6.3 DISCRETE-TIME MODELS 6.3.1 Introduction A discrete-time model for a switching converter will be developed based on the continuous-time small-signal model. The discrete-time model is more precise than its continuous-time model and it can be implemented using a digital con- troller. Both voltage-mode and current-mode control schemes are discussed. 6.3.2 Continuous-Time and Discrete-Time Domains For the continuous-time system of the form x = Ax(i) + Bu{t) (6.326) the solution for the differential equation (6.326) in the time domain can be expressed as x{i) = e^'xOo) + [ e^l'-^ButfdT. (6.327) The above equation is an exact representation of the continuous-time system. It implies that the state at the instant t depends only on the state at the time t Q and the convolution of the inputs and the transition matrix, considering the values of the states in between. The evaluation of the integral can be simplified by approximating e Ar with only the first two terms from its Taylor series: e 4 ' = I + At+A 2 t*2l + ■ ■ ■ . Also, assume that u(i) = u is constant over the integration interval and t = 0, Thus: t i f e A{ '- T) Bu(T)dr = [ e A 'e~ AT Bu dr ■ 303 Dynamic Analysis of Switching Converters i i f eW^>B4j)dT = e 4 ' f e~ Ar Bu dr *» to 'o t le^l'-^BWdT = e A 'Bu[A- 1 (-e- AT )]\\', o <* to I [^'-^Bui^dT = e A 'Bu[l - e- A ']A~ l if the matrix ^4 is invertible. Rearranging the above equation f e Ai '- T) Bu(T)dT = [e*' - l]A~ l Bu. 'o Replacing e 4 '' with its approximate value, f e*l'-r)Bu(T)dT = \I + At-I\A~ x Bu. Then, the solution of the differential Equation (6.326) in the continuous- time domain can be=approximated as xiO^e^'xito^+tBuito). (6.328) Making t = (n + S)T S and * = (« + 1 + D)T S , results in the discrete-time expression: x[{n + 1 + D)T S ] = ^T'xKn + D)T S ) + T s Bu[(n + D) ■ T s ]. (6.329) 6.3.3 Continuous-Time State-Space Model Switching converters are nonlinear and time-invariant circuits. Different linear models have been developed to describe the small-signal behavior of the switching converters [1,4-8,16,28]. Suppose that the converter is operat- ing in the continuous-conduction mode with a constant switching frequency / S = (1/:T S ). Let the eircuit topology be A\ during the interval when the mam 304 Power-Switching Converters switch is on (i.e., / on ). When the main switch is turned off (i.e., / ofr ), the circuit topology changes to A 2 - Writing the circuit equations in matrix form, we obtain the state-space representation of the system: -IS m x(t) = Ax(i) + Bu(i). (6.330) |j( Because the system has two different topologies during t on and t oST , the con- -WS verter is characterized by twp sets of state equations. During t on corresponding W& to the nth switching period, n T s < t < (w + d„) T s , the state equation is: 4 j9| m x = A 1 x + B 1 u. (6.331) M By analogy, during / rr> (n + d„) T s < t < (n + 1)T S , the state equation f§j becomes ;§8| x = A 2 x + B 2 u, (6.332) Jj where d n is the duty cycle. S A small-signal model of the converter can be found by following the |jj steps described in Brown and Middlebrook [2], where the switching func- IS tions in Equations (6.333) and (6.334) help to combine the two sets of 111 equations into one single equation: ill d<i)={ X XnT s <t<{n + d n )T s jj aV) \0 if(n + d n )T s <t<(n+l)T s , K ° M * } M d\i) = 1 - d(t). (6.334) m Then S x = (d(t)A , + d'{i)A 2 )x + {d(t)B x + d'{t)B 2 )u. (6.335) M Notice that if the duty cycle d„ is constant, then Equation (6.335) is linear with periodic coefficients. However, if d„ is used as the control variable, Equation (6.335) will be nonlinear because the duty cycle will be a function of the state variables. Nevertheless, it is possible to obtain a linear model if the perturbations on the duty cycle are kept small. The source variable and duty cycle can be represented by a nominal value (noted in capital letters) plus a perturbation term (noted in lowercase with ' A '). Consider the source variable as 4 To simplify the notation, the temporal dependency of the variables -will be omitted unless it may lead to confusion. Thus, for example, jc({) will be written as x. Dynamic Analysis of Switching Converters 305 u=V s + v s . (6.336) The duty cycle is d„ = D + d. (6-337) The switching functions can also be described by a steady-state part, d(i), plus a perturbation, d{t), such that d = d + d and d'=\-d, (6.338) which are defined as 3rrt _ / 1 if irr. </<(« + D)r, (6 339) * w- \o if (» + £>)7;<r<(M + i)r s and 5 (l) = J sgn(4, - £>) if f€[(" + D)r s , (n + d„)r s ] ^ (6 340) \ otherwise where sgn() is the sign function. The last two equations model the effect of a perturbation on the duty cycle. Similarly, the state vector can be represented by a time-variant steady- state part plus a perturbation: x = x + x. (6-341) Replacing the above equation in the state equation results in an expression describing the steady-state and perturbation responses. Making the perturba- tions equal to zero, the steady-state equation (6.335) is obtained: x = (dA , + d'A 2 )x + (dBi + d'B 2 ) V s - (6.342) Subtracting the steady-state response from the full response results in the expression for the perturbation in the state vector. This expression can be linearized assuming that the perturbations are small enough that the product of perturbations is negligible: x=[dAi+d , A 2 ]x + [dB t + d'B 2 ] v s + [0*1 - A 2 )x + (B t -B 2 )V s ]d. (6.343) 306 Power-Switching Converters Finally, the function d(i) can be approximated using a string of delta functions having the appropriate areas, as shown in Brown and Middlebrook [2]: d ~M0 = £ (dnT s )s[t - in + D)T S ). (6.344) 6.3.4 Discrete-Time Model of the Switching Converter In this section, a discrete model of the switching converter is obtained by integration of the continuous state-space equation (6.343) over a switching period. The discrete model describes the small-signal behavior of the con- verter only at one time instant during each cycle, saying nothing about what happens in between. Since the starting point of the integration is arbitrary, it is convenient to choose the time when the state vector is used to calculate the duty cycle. This time may depend on the implementation. We choose the instant (n + D)T S as the starting point of the integration, where the inductor current is at its maximum value. During the interval, [(n + D) T s , (« + 1) TJ, the switching functions are d— and 3 = 1 . Thus x = A 2 x + B 2 v s + Kd„ T s 8[t - (« + D)T S ], (6.345) where K = (A, - A 2 )x[{n + D)T S ] + (B x - B 2 )V S . (6.346) Since the 5 function is nonzero only at (« + D)T S , the integration yields mr+ l)T s ] = e AliyT 'e A ' iyT 'x[(n + D)T S ] + e A ^ T 'KT s d n (n+or, + f eA2V.»+»T>-*B 2 v s dT. (6.347) (n+D)T s Assume that no perturbations are present on the input voltage during the integration interval, then v s =0. Therefore, the last term of Equation (6.347) is also equal to zero. This approximation implies that the input voltage is not considered as a perturbation input; as such, it does not affect the stability analysis. By analogy, during the interval [(n + l)T s , (n + 1 + D)T S ] the state equation is x = Aix. (6.348) Dynamic Analysis of Switching Converters 307 To evaluate the integral over this interval, the value for the state vector at the end of the previous period, x[(n + 1)7;] is used as the initial condition, yielding i[(« + 1 + D)T S ] = e A > m '*e**' ,T 'xtt.n + D)T S ] + e A > DT *e A * OT >KTX- ( 6 - 349 > Notice that the transition matrix <p = ^DT^iOT^ (6.350) depends on the switching frequency. Equation (6.349) describes the state vector at the instant (n + 1 + D) T s as a function of the initial state x[(n + D) T s ] and the small-signal perturb- ation of the duty cycle with duration d„T s . A discrete model for a general switching converter has been developed. This model allows us to evaluate the behavior of the system for a small- signal variation on the duty cycle d„. Example 6.8. Find the discrete-time model for the synchronous buck con- verter of Figure 2.10. Solution. Figure 6.73 and Figure 6.74 represent the two equivalent circuits for the synchronous buck converter during / on and t ofr , respectively. /? L includes the resistance of the inductor's winding and the current-sensing resistor. R on is the on resistance of the switching devices. To develop the state-space model, the state variables are selected to be the current flowing through the inductor and the voltage across the capaci- tor. Then, the state-space model is [t] (6.351) -W\ VW 1 =F C Figure 6.73 Equivalent circuit during r on : A\. 308 Power-Switching Converters -A/VV tC R Figure 6.74 Equivalent circuit during f rr: A 2 . Ron + -Rl 1 A = B,= L C L 1 RC B 2 ia- (6.352) (6.353) For a synchronous buck converter, A X = A 2 = A then the discrete-time model is x[(n + \)T S ] = e AT '^nT s ] + e AT 'KT s d n and K = B,F S (6.354) (6.355) ■m 6.3.5 Design of a Discrete Control System with Complete State Feedback Consider a plant that has been made discrete in time, having the following difference equation: x (n + 1) = Ax(ri) + Bu(n). The usual technique in control systems consists of generating the control strategies based on measurements of the system states. In case of a voltage regulator, for example, the most commonly used feedback technique is proportional to the state. This can be of the form u(ri) = - Fx(n), then: x(n + 1) = (A - FB)x{n) M For this kind of system, the closed-loop eigenvalues are found by solving the If characteristic equation: g| det[z/ - A + FB] = 0. Dynamic Analysis of Switching Converters 309 Notes: o If the state vector has dimension i and the control has dimension j, the matrix F will have i x j elements. . If the system described by (A, E) is controllable, the choice of the elements of Fwill control the position of the closed-loop poles on the z-plane. . If the elements of F are real, the closed-loop poles will be real or complex conjugates. . If the applied control is a scalar such as in a switching converter, the resulting F is a row vector, having i elements. The elements of F are unique if the f roots of the characteristic equations are specified. . The closed-loop poles can be arbitrarily placed by choosing the elements of F. 6.3.5. 1 Pole Selection One way of choosing the closed-loop poles is to select an fth order low- pass Bessel filter, where i is the order of the system that is designed for the transfer function [21]. The step response of a Bessel filter has no overshoot, thus it is suitable for a voltage regulator. The desired filter can then be selected for a step response that meets a specified settling time. The minimum settling time should be chosen such that the control variable should not saturate. There are two possibilities in choosing the closed-loop poles; the first is to design an analog filter that meets the continuous-time specifications, and then map the poles into the z-plane. The other possibility is to design a discrete filter with the right specifications. The filters can be designed with the aid of the filter toolbox that comes with MATLAB or with any other filter package, like Filter Wiz. If the poles are chosen in the s domain, as for example P^= {s u s 2 ), the mapping into the z plane can be performed using p z = ef" % resulting m /> z ={z,, z 2 }. 6.3.5.2 Feedback Gains The values for the elements of the feedback vector L of the discrete model can be obtained by pole placement. The MATLAB command L = PLACE(3> rf , Y d , P) computes a state-feedback matrix L, such that the eigenvalues of 0> rf - T d * L are those specified in vector P. 6.3.6 Voltage Mode Control In Equation (6.354), the control input is d„. It is necessary to derive an approximate expression for d„ as a function of the state variables and the HI 310 Power-Switching Converters control variable, v ref , used in voltage-mode control. This was calculated in Equation (6.3) as d = -^-v n f. (6-356) The discrete-time model for a switching converter is given by Equation (6.349), repeated here for .convenience, x[(« + 1)T S ] = e A ' DT 'e AliyT 'x[nT s \ + e AtDT 'e A ^ T 'KT s d„. (6.357) This can be written as: x[(n + \)T S ] = 4>x[nT s ) + r'd n , (6.358) where { r = <PKT S (6-359) K = (B l -B 2 )V s . Replacing d„ from Equation (6.356) into Equation (6.358), we obtain i[(« + i)7;] = ^i[/i7;]-i-r-^-v re f. (6.360) 1 If full-state feedback is applied and the system is controllable, then the |j closed-loop poles can be arbitrarily placed to obtain a desired transient |j response. The negative feedback proportional to the states on v rer is: | v ref = -Fx[nT s ]. (6.361) | 'i The elements of the vector F are real numbers that weigh the perturbation of | each state variable and determine the closed-loop poles of the system. | Replacing the expression found for v ref in the system model: M ::M 4~ x[(n + 1)7;] = [* - r^-A x[nT s ). (6.362) | Then the expression in square bracket in the right-hand side of Equation f (6.362) is the closed-loop matrix of the system: | 4> CL =\<P-r-£-F\. (6.363) 1 Dynamic Analysis of Switching Converters 311 Then, Equation (6.362) can be written as: i[(«+i)r s ] = 4> Ci .x[/ir s ]. (6.364) Thus, the closed-loop poles can be arbitrarily placed by the right choice of the elements of the vector F. Therefore, withthis control strategy; it is possible to choose a desired transient response. 6.3.6. 1 Extended-State Model for a Tracking Regulator A voltage regulator for the vOltage-mode converter was developed in Section 6.3.6. This controller was calculated under a constant-current load. Our interest is to develop a mechanism that would allow the controller to track load changes and then, update the reference to the new load state; to do so, additional dynamics are added. Figure 6.75 represents a digital tracking system that uses a full-state feedback. The additional dynamics are represented by <P a , r a , and L 2 [21]. A state equation for the design model shown in Figure 6.75 can be obtained by defining a composite state vector: Xd[n] = idn] v c [n] x„[n\ where x a is the state vector of the added dynamics. Then, using the formula for the cascade connection of two state-space systems, the state-space description of the design plant is <Pd r a c *.]' r ' = "[o]* (6.366) where c relates the output to the states through-y = cx. A regulator for (4» d , r d ) can be designed and the vector of feedback gains can be partitioned as Figure 6.75 Digital tracking system with full-state feedback. 312 Power-Switching Converters 111 r L=[L X L 2 ] (6-367) where L, consists of the first n e elements of L, where n e is the order of the system to be controlled. L 2 is the remainder of L that relates the output to the states through y a = L 2 jc 3 . L can be found by pole location of the closed- loop regulator. The procedure to find («£ a ,.T a ) is covered in detail in Vacearo [21]. The main advantage of this configuration is that if the actual closed- loop system is stable, the actual system will track the reference input with a zero steady-state error. This is a desired feature in voltage regulators. A complete design example of a voltage-mode synchronous buck converter with digital control is given in Chapter 10. 6.3.7 Current Mode Control To apply current-mode control to the synchronous buck converter, d„ from Equation (6.354) has to be written as a function of the state variables and the control variable / p . This expression was found previously, as Equation (6.6), and re-written here as equation (6.368) dd„. dd n . dd n - OX\ ox 2 Olp j oa„ . oa„ _ oa„ ~ ,, ,,„.. d„ — -^-x\ + -^rx 2 + -^rh> 10.3&8) where Xl== i L , x 2 = v c . (6-369) Then % dd n - dd n „ dd„ ~ (f - , 7m Oil ov c dip The sensitivities in Equation (6.370) are given by Equations (6.10), (6.18), and (6.22) as i L , < 6 - 371 > (6.372) d m = (V d -V c )Ts l d n = D ^ v d - v c Vc ' and d n = {V & - L j ■ V c )T/ p - (6.373) 313 Dynamic Analysis of Switching Converters Let m = pi, ^ = |*L , „ 3 = «■ , and /2 = fe **]- (6374) 9xi ax2 a/p Replacing Equation (6.374) in Equation (6.370) yields: Thus, the perturbation on the duty cycle, d m can be expressed as the sum of a part due to the current-mode and another part due to the feedback: d„ = d CM+ d r . < 6 - 376 > The discrete-time model equation for a switching converter was found in Equation (6.358) to be: *[(» + i)T s ] = 4»i[«r s ] + rd„. ( 6 - 377 ) This can be written as x[(n + l)r s ] = <Px[nT s ] +r(d C M + d F ) • < 6 - 378 ) Thus x[(n + l)r s ] = &x[nT s ] + ri2x[nT s ] + ro> 3 I p . (6379) By grouping the terms corresponding to the current-mode, the above equa- tion can be written as: x[(n + i)r s ] = #c M £[n:r 5 ] + r<o 3 i p . ( 6 -380) Then the system matrix in current-mode is & cu =&+m. (6381) This equation states that when the converter is operating in the current- mode, the dynamic of the system differs from that of the open-loop due to the inherent feedback represented by m. This contribution may lead to current-mode instability in some switching converters [28,29]. 3J4 Power-Switching Converters For a lossless synchronous buck converter, the poles of <J>cm lie inside of the unit circle for D < 0.5 and outside the unit circle for D > 0.5. If full- state feedback is applied and the system is controllable, then the closed-loop poles can be arbitrarily placed to stabilize the system and to obtain a desired transient response. The negative feedback proportional to the states on I p is / p = -Fx[nT s ). (6382) Replacing the expression found for I p in the system model x[(ti + l)T s ] = [*«* - t*iTF]i\nT,]. (6.383) Then the expression in square brackets in the second term is the closed-loop matrix of the system: &cl = [4>cm - <*3TF\ (6-384) and x[(n + l)r,] = <PcLx[nT s \. (6-385) The closed-loop poles can be arbitrarily placed by a judicial choice of the elements of the vector F. Therefore, with this control strategy, it is possibly to stabilize the current-mode converter under a constant load, even for duty cycles greater than 50%. As was mentioned before, the converter operating with a duty cycle greater than 50% is unstable in the open-loop configuration. 6.3. 7. 1 Extended-State Model for a Tracking Regulator A voltage regulator for the current-mode switching converter was developed in Section 6.3.7. This controller was calculated under a constant current load. Our interest is to develop a mechanism that would allow the controller to track load changes and then update the reference to the new load state. To do so, additional dynamics are added, as shown in Figure 6.76, which represents a digital tracking system that uses full-state feedback. The additional dynamics are represented by <f> a , A, and L 2 . L 2 relates the output of the additional block to its states through y a = L 2 x a . A state equation for the design model in Figure 6.76 can be obtained by defining a composite state vector: '(tWl x d [n]= v c [n] , (6- 386 ) x a [n] Dynamic Analysis of Switching Converters 315 IjTH©-* Figure 6.76 Digital tracking system with full-state feedback. where x a is the state vector of the added dynamics. Then, using the formula for the cascade connection of two state-space systems, the state-space description of the design plant is <P d r^cM [r a c *.]' r ' = [»]' (6.387) where c relates the output to the states through y = ex. A regulator for {&* F d ) can be designed and the vector of feedback gains can be partitioned as L = [£i L 2 ] (6.388) where L, consists of the first n e elements of L, and n c is the order of the system to be controlled (for a synchronous buck converter n e = 2). L 2 is the remainder of L. L can be found by the pole location of the closed-loop regulator. The procedure to find (4> a , F a ) is covered in detail in Vaccaro [21]. The main advantage of this configuration is that if the closed-loop system is stable, it will track the reference input with a zero steady-state error. This feature is desirable in the operation of voltage regulators. A complete design example of a synchronous buck converter with digital control is given m Chapter 10. PROBLEMS 6.1. The output filter shown in Figure 6.13 has a R^Co product of 60 x 10 -6 fl-F. The values for the inductor and load resistance are lOmH and 10 XI, respectively. Determine (a) the filter corner frequency, f , (b) the zero introduced by the equivalent series resistance, i?e sr , (c) the magnitude in dB at 10/ o ,4d) the phase angle in degrees at 10/ o , and (e) state whether the output response is critically damped, under- damped, or overdamped. j/5 Power-Switching Converters 6.2. The compensation network shown in Figure 6.22 has a zero at 1 kHz and a pole at 5 kHz. The gain of the compensation network at 4 kHz is 4. Determine (a) values for C, , C 2 , Ri , and R 2 , (b) the phase lag introduced by the compensation network, and (c) the phase shift introduced by the compensation network and the error amplifier. 6.3. The compensation network shown in Figure 6.25 has a double-zero-at 1 kHz, a pole at 10 kHz, and a pole at 30 kHz. The gain at the double zero is OdB. Assuming that /?, is 10,000 ft, determine: (a) values for C,, C 2 , C 3 , R 2 , and R 3 , and (b) the phase lag introduced by the compensation network. 6.4. The buck converter shown in Figure 6.30 has the following param- eters: K S =12V, K a = 5V, L„= 100 uH, C o =100u-F, ^^=0.001 ft, /? 3 =100kft, 7?4=100kfl, and/ s =20kHz. If the peak amplitude of the sawtooth signal is 3 V and the unity-gain crossover frequency of the closed-loop buck converter is 5 kHz, design the compensation network (i.e., Z x and Z 2 ) for a phase margin of 45". 6.5. The gain of the error amplifier of a closed-loop buck converter at the unity-gain crossover frequency of 5 kHz is 20 dB. The rate of roll-off of the open-loop magnitude response at the unity-gain crossover fre- quency is -40dB/decade. The output filter capacitance and induct- ance are 1000|aF and lmH, respectively. Determine the phase lag required to be contributed by its compensation network and error amplifier. 6.6. Develop a linearized equivalent circuit that preserves the input and output circuits of a Cuk converter. 6.7. Develop a linearized equivalent circuit that preserves the input and output circuits of a buck-boost converter. 6.8. Obtain the output impedance, X 2 (s)/U 2 (s), for a boost converter hav- ing an Rest in the output capacitor. 6.9. Obtain an open-loop transfer function, G(s) H(s), for a boost con- verter that has an J?e Sr in its output capacitor. 6.10. Obtain an open-loop transfer function, G(s) H(s), for an ideal buck- boost converter. 6.11. Determine if a potential stability problem exists for the buck converter with an input EMI filter shown in Figure 6.30. The parameters for the buck converters are: input voltage = 10 to 15 V, output voltage = 5 V, switching frequency = 1 kHz, output inductor = 10 mH, output capa- citor = 1000 u.F, Re = 0.005 ft, and i? L = 5 ft. The parameters for the second-order input EMI filter are: L, = 10mH, C I = 2000 l i.F, and ^ = 0.005X1. 6.12. Determine if a potential stability problem exists for a buck converter with an input EMI filter shown in Figure 6.30. The parameters forthe -?/7 Dynamic Analysis of Switching Converters second-order input EMI filter are: Lj=100fi.H, Ci = 20,000 |xF, ^,. = 0.01 ft, R s = 0.005 fl. The buck converter has an input voltage range of 20 to 30 V DC. The output of the buck converter is connected to a load resistance of 0.5 ft. The other parameters for the buck converter are: C„ = 1 000 jjiF, ^=10 mH, and f s = 5 kHz. 6.13. A switching converter has an input voltage of 32 V and an input current of 3 A. Assume that the input impedance of the converter is completely resistive. Calculate the input EMI based on Figure 6.70, but do not use C,; instead, use a big capacitor C d with a large enough ESR to stabilize the converter. This technique is frequently used in many commercial circuits [30]. 6.14. Repeat Problem 6.1 3, but now model the input impedance of the switch- ing converter as a resistance in parallel with a capacitor, C. Determine a condition for the relative size of the EMI filter capacitor with respect to the converter capacitance that would stabilize the system [30]. 6.15. Repeat Problem 6.13, but now use the optimal value of the damping resistor, as discussed in Erickson [31]. 6 16 A buck converter has the following parameters: V s = 12 V, K a = 5V, L„ = 100 M.H, C„ = 100 ^.F, Resr = 0.001 ft, i? L = 5 ft, and /, = 20 kHz. The peak amplitude of the sawtooth signal is 3 V. Find the discrete- time model. 6.17. For the converter of Problem 6.16, choose a stable closed-loop pole location and calculate the feedback gains necessary to obtain those closed-loop poles when voltage-mode control is applied. 6.18. For the converter of Problem 6.16, choose a stable closed-loop pole location and calculate the feedback gains necessary to obtain those closed-loop poles when current-mode control is applied. 6.19. For the converter of Problem 6.17, design the additional dynamics to achieve a zero steady-state error. 6.20. For the converter of Problem 6.18, design the additional dynamics to achieve zero steady-state error. 6.21. Calculate the small-signal state-space averaged model for a boost converter operating in the continuous conduction mode. Consider the losses in the switch as R on and the losses in the diode as R d - There are no other losses in the converter. Show all your work. 6.22. (a) Draw the small-signal model for a voltage-mode buck converter operating in the continuous conduction mode, using the simplified Vor- perian average switch model, (b) Explain how to set up the model parameters, (c) What information can you extract from this circuit? ;lli 318 Power-Switching Converters REFERENCES 1. A. S. Kislovski, R. Redl, and N.O.Sokal. Dynamic Analysis of Switching-Mode \ DC/DC Converters, Van Nostrand Reinhold, New York, 1991 , p. xi. 2. A. Brown and R.D. Middlebrook. Sampled data modeling of switching .■; regulators, IEEE Power Electronics Specialists Conference Record, 1981, pp. 349-369. 3. C. C. Fang and E. Abed. Sampled-data modeling and analysis of the power stage of PWM DC-DC converters, Int. J. Electron., 88, 347-369, 2001. 4. R. D. Middlebrook and S. Cflk. A general unified approach to modeling switching converter power stages, IEEE Power Electronics Specialists Confer- ence Record, 1976, pp. 18-34. 5. V. Vorperian. Simplified analysis of PWM converters using the model of the PWM switch: Parts I and 11, IEEE Trans. Aerosp. Electron. Syst., 26(2), 1990. 6. R. B. Ridley. A new continuous-time model for current-mode control, IEEE Trans. Power Electron., 271-280, April 1991 . 7. R. B. Ridley. A New Small-Signal Model for Current-Mode Control, Ph.D. dissertation, Virginia Polytechnic Institute and State University, 1990. 8. B. Yaakov. Average simulation of PWM converters by direct implementation of behavioral relationships, IEEE Applied Power Electronics Conference, 1993, pp. 510-516. 9. R. C. Dorf and R. H. Bishop. Modern Control Systems, 9th ed., Prentice Hall, New York, 2001, pp. 631-667. 10. C. P. Basso. Switch-Mode Power Supply SPICE Cookbook, McGraw-Hill Pro- fessional, New York, 2001. 11. D. M. Mitchell. Switching Regulator Analysis with MAthCAD, distributed by e/j Bloom Associates (http://www.ejbloom.com). 12. L. Dixon. Closing the Loop, UNITRODE Seminar Book, Appendix C, SEM- 500. 13. R. Sevems and G. Bloom. Modern DC-to-DC Switch-Mode Power Converter Circuits, distributed by e/j Bloom Associates (http://www.ejbloom.com). 14. R. Erickson. Fundamentals of Power Electronics, Kluwer Academic Publishers, ISBN 0-412-08541-0. 15. A.I. Pressman. Switching Power Supply Design, McGraw-Hill, New York, 1 991 , pp. 427-470. 16. S. P. Hsu, A. Brown, L. Rensink, and R.D. Middlebrook. Modeling and analysis of switching dc-to-dc converters in constant-frequency current- programmed mode, IEEE Power Electronics Specialists Record, 1979, pp. 284-301. 17. D. M. Mitchell. DC-DC Switching Regulator Analysis, McGraw-Hill, New York, 1988, pp. 71-73. 18. R. P. Severns and G Bloom. Modern DC-DC Switch-Mode Power Converter Circuits, Van Nostrand Reinhold, New York, 1985, pp. 49-50. 19. D. M. Mitchell. DC-DC Switching Regulator Analysis, McGraw-Hill, New York, 1988, pp. 83-84. Dynamic Analysis of Switching Converters 319 20. D. M. Mitchell. DC-DC Switching Regulator Analysis, McGraw-Hill, New York, 1988, pp. 90-91. 21. R. J- Vaccaro. Digital Control: A State-Space Approach, McGraw-Hill, New York, 1995. 22. MATLAB, The Math Works, Inc. (http://www.mathworks.com). 23. Filter Wiz, Schematica (http://www.schematica.com). 24. M. J- Nave. Power Line Filter Design For Switched-Mode Power Supplies, Van Nostrand Reinhold, New York, 1991, 43pp. 25. R. D. Middlebrook and S. Cuk. Input Filter Considerations in Design and Application of Switching Regulator, Advances in Switched-Mode Power Conver- sion, TeslaCo, Pasadena, CA, 1983, 91pp. 26. N. O. Sokal. System oscillations, caused by negative input resistance at the power input part of a switching mode regulator, amplifier, dc/dc converter, or dc/ac inverter, IEEE Power Electronics Specialists Conference Record, 1973, pp 138-140. 27. D. M. Mitchell. DC-DC Switching Regulator Analysis, McGraw-Hill, New York, 1988, pp. 138-139. 28. R. D. Middlebrook and S. Cuk. A general unified approach to modeling switching converter power stages, IEEE Power Electronics Specialists Confer- ence Record, 1976, pp. 284-301. 29. Modeling, Analysis and Compensation of the Current-Mode Converter, Uni- trode Application Note U-97, SLUA101, Texas Instruments, 1995. 30. M. F. Schlecht. Input System Instability, Application note PQ-00-05-1 , SynQor, 2000 (http://www.synqor.com/datasheetlocator). 31. R. Erickson. Optimal single resistor damping of input filters, IEEE Applied Power Electronics Conference, 1999. IB) Hi ■3Ba ■SBs HP 1 All Interleaved Converters 7.1 INTRODUCTION Interleaved converters are the result of a parallel connection of switching converters. They usually share the same output filter. Interleaved converters offer several advantages over single power stage converters; a lower current rip- ple on the input and output capacitors, faster transient response to load changes [1], and improved power handling capabilities at greater than 90% power efficiency. An interleaved converter can be realized by "interleaving" (or driving out of phase) the control signals to each of the paralleled converters, resulting in an effective increase in its switching frequency. They are used m applications where the loads demand low ripple or very tight tolerances. Such requirements are found in the new generation of personal computers, in which core voltages and currents of the central-processing-units (CPUs) are appro- aching 1 V and 1 30 A, respectively. [2]. Interleaving converters are also finding applications in switching audio amplifiers by interleaving series or parallel combinations of power inverters [3]. Additionally, interleaving enables the converter to spread its components and the dissipated power over a larger area. 321 322 Power-Switching Converters 7.2 INTERLEAVED BUCK CONVERTER A two-stage parallel-interleaved buck converter is shown in Figure 7.1. As shown, the current to charge the output capacitor, C,, is provided by the two similar output inductors, L x and L 2 , from each of the paralleled converters. The charging current for each of these inductors comes from the individual converter stage. If the two switches were driven by the same pulse-width modulation (PWM) signal, inductors L x and L 2 would effectively be con- nected in parallel, thus resulting in an equivalent buck converter with a smaller inductor but only a half the total current flowing through each of these switches. However, if the two switches are driven by out-of-phase PWM signals, pwm t and pwm2, with a phase shift equal to 2ir/n, where n is the number of paralleled cells (in this case n = 2), then the ripple current flowing through the output capacitor would be reduced. Figure 7.2 shows the PSpice circuit schematic for a two-stage parallel- interleaved buck converter. The voltage and current waveforms of the simulated interleaved buck converter are shown in Figure 7.3. As can be seen, the phase shift between inductor currents, I Ll and I Ll , is 180°, while their current frequency is the same as the switching frequency. The current ripple of both the inductors is about 245 mA. In the steady state, the sum of IfX pwm 2 pwm 2 |Mj A D z Figure 7.1 Interleaved buck converter. Interleaved Converters 323 VI =0 V2 = 10 TD = TR = 999u^ TF . 1 r> PW = 1 n — _ PER^Im u Figure 7.2 PSpice circuit schematic for the simulated two-stage parallel-inter- leaved buck converter. V(out) 800 mA 600 mA 400 mA 500 mA 250 mA 0A _ 7 /(L,) + /(L;,) 26.34 27.00 ? l(L,) v /(Lz) 29.00 30.00 28.00 Time (msec) Figure 7.3 Voltage and current waveforms of the interleaved buck converter. 324 Power-Switching Converters 1l, + Ili provides the charging current for the output capacitor as well as v the average output load current. The amplitude of the current ripple in the ■; combined I Lt + 1^ is 80 mA but its frequency is twice the switching : frequency. Since this ripple current determines the capacitor ripple voltage, the latter is reduced as compared to that of a single buck converter. It should be noted that the output ripple voltage also has twice the switching frequency. The input and output current ripples of a paralleled interleaved con- verter are always less than or equal to those of the individual converter [4]. Under some special operating conditions, a zero current ripple can be achieved in this interleaved converter. This happens in a two-stage inter- leaved buck converter when it is operating at a 50% duty cycle. Unfortu- nately, this condition may only be achieved in the open-loop operation. In the close-loop configuration, the controller automatically adjusts the duty cycle to compensate for load or line fluctuations, thus losing the zero-ripple operation. Nevertheless, it is possible to operate near a zero-ripple point for small variations in the duty cycle. As shown in Figure 7.2, the control signals, pwmi and pwm 2 , are generated by comparing the same control signal with two sawtooth gener- ators having a phase shift of 180°. In practice, a shift register or a counter and a decoder can be used to generate the shifted clock pulses [5]. 7.2.1 State-Space Averaged Model Figure 7.4 shows the PWM signals, pwmi and pwm 2 , for the two switches of the interleaved buck converter shown in Figure 7.2. There are four modes of operation. During mode 1, both the PWM signals, pwmi and pwrn^ are high (HI). The duration of mode 1 is d x . In mode 2, pwm, is high (HI) and 1.0 V 0.5 V SEL» 0V 1.0 V 0.5 V 0V Mode 1 Mode 2-- i Vlode3J I • i i Mode 4; j « =» '. I *( =» d 3 ! ! < — >.tz ; d 4 \ \ ■ >; 1 M[pwm 2 ) 10.00 10.40 Time (msec) Figure 7.4 Switch driving signals, pwmi and pwm2. (1-D) 10.80 11.12 Interleaved Converters 325 pwm 2 is low (LO); the duration of this mode is rf 2 . Mode 3 is similar to mode 1, i.e., both PWM signals, pwm, and pwm 2 , are high (HI) and its duration is J 3 . Finally, during mode 4, pwmi is low (LO) and pwm 2 is high (HI). Its duration is d 4 . Due to the circuit symmetry, we have di=d 3 , d 2 =d4, rf,+</ 2 = 0.5. (7.1) Since there are three independent energy-storage elements, the converter can be modeled by a third-order system. The state variables are selected as: Vc (7.2) The state space mode! is where A = x = Ax + BV % , y=Cx + D a V s , o o xT o o t , B = 2di+<h L 2 11 -1 _c C RC. . o (7.3) , C = [0 1], D» = 0. (7.4) The voltage conversion ratio is given by K a = V S D. (7.5) All converter cells are phase shifted and they equally share the current at steady-state operation. The transient response can be improved by the control strategy proposed by Miftakhutdinov [1], where during a load transient all the converter cells switch to the same state simultaneously. Under this condition, the interleaved converter can be considered as a one- cell converter, which has the same input voltage, V s , as the original inter- leaved converter andra smaller output inductor L ob = LJn. Therefore, the corner frequency of the output filter is shifted up in frequency, yielding a faster transient response. 326 Power-Switching Converters 7.3 INTERLEAVED BOOST CONVERTER Figure 7.5 shows the circuit diagram of a two-cell interleaved boost con- verter, while Figure 7.6 shows its correspondent PSpice schematic. As shown, both cells share the input voltage, V s , and the output capacitor, C,. The PWM signals, pwm, and pwm 2 , are shifted by 180°, or lirln, where n = 2, as shown in Figure 7.7. The input current is equal to the sum of the inductor currents, J Ll + 1 L% . Since the inductor currents are 180° out of phase, the resulting input current has a very low ripple. This characteristic, in combination with the continuous input current of the boost converter, makes this circuit ideal for applications in personal computer power supplies and power-factor compensators [6]. 7.3.1 State-Space Averaged Model Similar to the interleaved buck converter, for the continuous conduction mode (CCM) of operation, we have d\ = d 3 , d 2 = d 4 , d,+d 2 = 0.5. (7-6) Since there are three independent energy-storage elements, the converter can be modeled by a third-order system. The state variables are selected as *-i ^- v s pWITl! out ^ c 1 "i ESR pwm 2 -w- Figure 7.5 Interleaved boost converter. Interleaved Converters 327 s VON = 1.0V VOFF = = 0.0V ROFF = 1e6 RON = 0.05 if( v pam)<vc%iN2).i. o) |pwn 2 PWM modulator il( V( %IW1)«V<%IN2),1. 0) pwn. saw 2 V 1 = V 2 =10 TD = 0.05 m TR = 99.9 u TF = 1n PW=1n PER = 0.1 m control TD = TR = 99.9 ul TF=1n -zLr PW =1 n - PER = 0.1 m Figure 7.6 PSpice schematic of an interleaved boost converter. v c The state space model is x = Ax+BV s , y=Cx + D u V s , (7.7) (7.8) mil 328 1.0 V - 0.5 V • SEL» 0V 1.0 V 0.5 V OV Power-Switching Converters Model !Mode2 : II • ■ Mode 3> Mode 4- Id." \ <k\ ?6 =» ■« i : = s «£ 5»r< 1 : &• = V(pwm^ (1-P) 10.00 V(pwm,) 10.40 Time (msec) 10.80 11.12 Figure 7.7 PWM and current waveforms of the interleaved boost converter. where A = A\d\ + A 2 d2 + A 3 d 3 + A 4 d 4 , B = B\d\+ B 2 d 2 + B 3 d 3 + B 4 d 4 , C = [0 1], and A. = (7.9) An expanded view of the input current and the two-inductor currents is shown in Figure 7.8. Since the duty cycle is not 50% (i.e., D = 0.6), the ripple of the two inductor currents does not cancel when added. Nevertheless, the input current ripple is 500 mA, while the ripple current of each inductor is 1.5 A. The input ripple current can be further reduced by forcing the operation close to D — 0.5 or by increasing the number of paralleled cells. Figure 7.9 represents the output current and voltage waveforms of the simulated interleaved boost converter. Under the simulated conditions, P o = 200W,/ s = 10 kHz, and C, =220p.f, the output voltage ripple is close to 1 V. Increasing the switching frequency or the output capacitance reduces the output voltage ripple. Figure 7.10 shows the equivalent circuits of the operating modes of the CCM interleaved boost converter. The state matrixes for each mode can be calculated as follows: -A 3 A-> = i Rl 0] o i* ■ 9 -I -1 C RC- Bi=B 3 = L, _L U B 2 = j_ L, _L Li Lo (7.10) (7.11) Interleaved Converters 35.992 A- 35.800 A-| 35.600 A- SEl» 35.413 A' 19 A 18 A- 17 A 329 14.2052msec 14.2400msec 14.2800msec 14.3200msec 14.3600msec 14.4000msec 14.4315msec . hl,) . ny Time (msec) Figure 7.8 Input and inductors currents. 15 A 10 A 5A 0A wwwww HWWWW - \ l{F>d Os V(out) 0.5 1.0 2.5 3.0 3.5 4.0 1.5 2.0 Time (msec) Figure 7.9 Output current and voltage waveforms of the interleaved boost con (7.12) and A 4 = -T . C " RC. , B 4 = - l n i-i .0. 330 Power-Switching Converters -Up (a) Mode 1 (b) Mode 2 +J_ k, U lG, % = . C 1 |fl| -o (c) Mode 3 -0 r ° (d) Mode 4 Figure 7.10 Equivalent circuits of the operating modes of the CCM interleaved boost converter. Finally, -*] r l ^2 U A = -A i 2 , B = 1 Li -tU -d 2 1 n L C c /?C- C = [ 1], A, = 0. (7.13) The conversion ratio can be calculated by imposing the volt-second balance on the inductor L\ . (7-14) d x V x + d 2 V x + d 3 V x + d 4 { V x - v c t= since 1 '1 d\ + d 2 + d 3 = D and d 4 = (1 - D) then * (l~i>)' (7-15) (7-16) This is the same expression as for a single-stage or one-cell boost converter operating in the CCM. Interleaved Converters 331 7.4 INTERLEAVED CONVERTER OPERATION BASED ON CURRENT-RHODE A family of interleaved converters based on current-mode control (CMC) could be generated by connecting N identical boost converters in parallel, as depicted in Figure 7.11. The CMC using interleaving techniques based on a binary-state transition diagram was proposed in Giral et al. [7]. In a binary- state transition diagram, the status of all the switches is represented by a binary code, a "1" is used when the switch is on and a "0" when the switch is off. From the 2 N possible binary states, one state-transition cyclic sequence is chosen to generate the required phase shift 2-ir/N among the converter waveforms. In steady state, all the binary states have the same duration and RL, 10 3= V, 1 ^o "Tfe] H 50^T ,V = 2 Q m 5 H Q ^i| Dbreak -M- RL2L2 D 2 RU Dbreak D 3 Vh [^] H S^SSs O^T **"** out IC = 28] 50 ^0 if(V(%IN1)>V(%IN2)+DI,5,0) h i I kgtk if(V(%IN1)>V(%IN2)+DI,5,0) k ' ' '39th PARAMETERS: Control if(M[%IN1)>V(%IN2)+Dl > 5,0) it — I I /i£T«2 ► %>^ |> i 3 >i, & i\>h. CMC Oil Cfe! Qo -Pi D/=50m Figure 7.11 Interleaved boost converter with CMC. 332 Power-Switching Converters the cyclic sequence imposes a complementary duty cycle 1//V for each state, resulting in an average output voltage which is N times the input voltage. An example corresponding to TV =3 is analyzed. The control is imple- mented using a comparator with a hysteresis band, Ai, combinational logics, and a shift register. The current-controlled voltage sources //; are used as current sensors for the PSpice simulation. The comparators are modeled with the ABM1 block using an If() statement. The corresponding state-transition diagram is illustrated in Figure 7.12. Starting from state 01 1 (S 3 S 2 Si), a condition where i 2 > '3 + Az" forces the change to the next state 110. The converter remains in this state until the condition, i 3 > z'i + Az', causes the transition to state 101 . The converter will stay in this state until the condition, U >i 2 + Az", is met and a transition to the initial state, Oil is made, starting the cycle all over again. The switching frequency, f s , is inversely proportional to the hysteresis width, fs D L (N-l) Ai V e N-l 1 L N (N - 1) Az" (7.17) 1 L NAi' where V g is the input voltage, D is the steady-state duty cycle, and L is the inductance value of each converter. 7.4.1 Ripple Calculations One of the main features of interleaved converters is the ripple reduction. In this case, the focus is on the input current ripple, which becomes consider- ably reduced. Figure 7.13 illustrates the steady-state waveforms of the capacitor current, output voltage, and the different inductor currents for Hi>% .*J&> % > f| + Ai Figure 7.12 Control state diagram. Interleaved Converters 500 mA 0A -500 mA 28.0 V 27.9 V 333 - '(C,) _^ 1 ^ ^ | SEL» 408 mV 9.700 9-720 • V\h) -W2I ' V(i 3 ) 9.740 9-760 Time (msec) 9.780 9.800 Figure 7.13 Voltage and current waveforms of the interleaved boost converter with CMM. N = 3. As shown in this figure, the ripple in each inductor current, A//, is exactly two times (N - 1) the hysteresis width of the controller. The expression of the output voltage ripple is given by 1 lA/jDT Av ° = C2TT : (N - 1) MPT %C (7.18) which depends on the current ripple in one of the inductors. Thus, reducing A/i also reduces the output voltage ripple at the expense of an increased switching frequency. Alternatively, Av can also be reduced by increasing the value of C. Taking into account that D' = 1/iV and T = \lf s , then Av = UN - l)Ai 2 8CK E (7-19) It can be seen that there is also an improvement in the output voltage ripple if I- is reduced. Considering a constant current ripple, Av„ will increase if the number of converters is increased. The amplitude of the input current ripple is given by 2 ., 2 Av c A/s= 97|-r ht = 2 A/i 36yft LC {pT? = 1 A/i ©■ (7.20) 334 2.0 A 1.5A 1.0 A 0.5 A Power-Switching Converters 0A Os 1 2 4 5 6 Time (msec) Figure 7.14 Comparison of the input current and the inductor current. Thus, increasing N reduces the input current ripple. The reduction in the input current ripple achieved by this topology is shown in Figure 7.14, where a comparison of the input current and the current flowing through one of the inductors are illustrated. Figure 7.15 shows an expanded view. The ripple in the input current is 460 uA, while the ripple in each inductor current is 280 mA; this is a 1/600-reduction ratio. This example reveals the main advantage of this topology, which is the possibility of an almost ripple-free input current. 7.4.2 Number of Converters Although the input and output ripples can be very small, it is not possible to regulate the average values of both input current and output voltage inde- pendently. The first criterion to choose N will be derived from the output voltage or input current specifications. Since D = N/(N - 1), increasing N makes the duty cycle closer to its upper bound of 100%. Experimental limits, however, establish Ana* = 0.9, which corresponds to iV max = 10. 7.5 POWER FACTOR CORRECTION Nonlinear loads in electronic systems degrade the quality of the utility system by reducing its power factor and injecting unwanted frequencies. As such, electric appliances or electronic systems drawing a sinusoidal current at a Interleaved Converters 1.6775 A 1.6770 A 335 SEL>> 1.6765 A - -'(V,) 9.86 ■ K.L-,) 9.88 9.90 9.92 9-94 Time (msec) 9.96 9.98 10.00 Figure 7.15 Comparison of the input current ripple and the inductor current ripple. unity power factor, ideally behaving as a resistive load, are desired. Most electric appliances or electronic systems are designed to accept the full range of Japanese, North American, and European utility voltages, which span approximately from 93 to 264 V(AQ. Moreover, a typical universal-input topology for power factor correction must satisfy both the IEC 555-2 line harmonic standard and VDE 087 IB conducted EMI emissions standard. A typical input converter topology that satisfies all the above requirements is based on the boost converter. The most common topology for single-phase utility interfaces is covered in Mohan et al. [8] where a hysteresis current control forces the input inductor current to follow a full-wave rectified sinusoidal reference current. Miwa et al. [9] proposes the use of interleaving techniques to reduce the switching frequency and associated losses. An example of such a universal-input AC-DC power supply using interleaving techniques is shown in Figure 7.16. A two-stage interleaved boost converter that outputs twice the input voltage serves as the AC interface. The reference current, 7 ren , is proportional to the required input current. The input inductor current, I Ll , is forced to follow / re n with a hysteresis control, as shown in Figure 7.17. The current flowing Plough the other input inductor, J Li , is just a delayed version of //.,, with a 2irlN phase shift. . Figure 7.16 shows the input voltage waveform, K(AC), and the result- ing total input current, 7(/? s ). Notice that the input current looks like a i 336 Power-Switching Converters 3 a. a 3 O o. U Q < 3 O. c 'S to o w 3 O) E 337 Interleaved Converters full-wave rectified sinusoidal current in phase with the input voltage. Thus, this makes the converter behave like a resistive load, with a very low harmonic current distortion. The bottom half of Figure 7.18 displays the output voltage of the boost front-end, K(outl), and the DC output voltage, 3.20msec d Vt/ reI1 ) 3.60msec 4.00msec 4.40msec Time Figure 7.17 Reference and input inductor currents. 100- 4.80msec 5.1 1 msec 0s 10msec 20msec + V^out) x V(out1) 30msec Time 40msec 50msec 60msec Figure 7.18 Input and output waveforms for the interleaved universal-input AC-DC converter. 338 Power-Switching Converters F(out). Notice that K(outl) is close to 200 V (twice the input voltage) with a large ripple of 60 V. The second stage is the interleaved buck converter analyzed previously. The reference voltage is set to operate near a zero- ripple operating point (D = 0.5 in this case). This guarantees a DC output voltage with a reduced voltage ripple, using a small output capacitor. PROBLEMS 7.1. Show that the expression of the state-space averaged model of the interleaved buck converter of Figure 7.1 is: 7.2. 7.3. 7.4. ° ' ifl A = i i -i -C C RC. , B = C = [ 1], £> u = 0. 2d, -1- d 2 L, 2d\ + <h L 2 Consider the interleaved buck converter of Figure 7.1. Design a voltage regulator that would output 3 V from a 10-V input source. Measure the simulated output voltage ripple. Consider the interleaved buck converter of Figure 7.1 operating with a fixed duty cycle D = 0.5. Design a switching converter to be connected between the unregulated DC input voltage and the interleaved converter. This converter should act as a preregulator to develop the necessary input voltage for the interleaved converter to maintain a constant 3-V output. Compare the output voltage ripple of the regulator with (prob- lem 7.3) and without (problem 7.2) the switching preregulator. Modify the universal-input AC-DC power supply shown in Figure 7.16 to accept AC input voltages from 94 to 264 V. Hint: the load connected to this utility interface absorbs a constant power. You will have to apply feedback to recalculate a different reference current for each input voltage level. REFERENCES 1. R. Miftakhutdinov. Optimal design of interleaved synchronous buck converter at high slew-rate load current transients, Vol. 3, IEEE Power Electronics Specialists Conference, June 2001, pp 1714-1718. Interleaved Converters ^39 2. International Technology Roadmap for Semiconductors, 1999 Edition. http://public.itrs.net/ 3. F. V. P. Robinson. The interleaved operation of power amplifiers, University of Bath, U.K. Proc. IEEE Power Electronics and Variable Speed Drives Conference, pp. 606-609, 1998. 4. C. Chang and M. A. Knights. Interleaving technique in distributed power conversion systems, IEEE Trans. Circuits Syst. I: Fundamental Theory and Applications, 42 (Suppl 5), 245-251 , May 1995. 5. B. A. Miwa. Interleaved Conversion Techniques for High Density Power Supplies, Ph.D. Dissertation, Department of Electrical Engineer- ing and Computer Science, Massachusetts Institute of Technology, June 1992. 6. B. A. Miwa and M. F. Schlecht. High efficiency power factor correction using interleaving techniques, APEC 1992, pp 557-568. 7. R. Giral, L. Martinez-Salamero, and S. Singer. Interleaved converters operation based on CMC, IEEE Trans. Power Electron. 14 (Suppl 4), 643-652, July 1999. 8. N. Mohan, T. Undeland, and W. Robbins. Power Electronics: Con- verters, Applications, and Design. John Wiley and Sons, New York, 1989. 9. B. A. Miwa, D. M. Otten, and M. E. Schlecht. High efficiency power factor correction using interleaving techniques, Applied Power Electron- ics Conference and Exposition, February 1992, pp 557-568. n Switched Capacitor Converters 8.1 INTRODUCTION Switched capacitor converters (SCCs) are implemented by a combination of switches and capacitors. The switches are controlled in such a way that the capacitors are charged and discharged through different paths; producing an output voltage that is ^proportional to the input voltage. The different combinations of capacitors and switches result in SCC topologies able to produce an output voltage that may be higher or lower than the input voltage as well as polarity reversal. The main advantage of the SCC is the absence of inductors and transformers, making possible a complete integration of the switching con- verter using integrated circuit technology. Also, they are easier to control than the magnetic-based switched-mode converters: The main disadvantage of SCC is that they require more switches than the magnetic-based switching converters. The switching currents in these SCC are also high, and thus, EMI is a major concern. However, SCCs are useful for small output power applications that do notrrequire isolation between the input and output. 341 342 Power-Switching Converters 8.2 UNIDIRECTIONAL POWER FLOW SCO Three basic SCC topologies are first discussed to introduce the mechanism of : SCC. These converters do not regulate the output voltage satisfactorily, be- cause the output voltage cannot be changed by controlling the duty cycle or the switching frequency [1]. Since the capacitors are charged and discharged through the switches, the output voltage depends on the impedances of the switches. 8.2.1 Basic Step-Up Converter A basic step-up SCC is displayed in Figure 8.1. The gate signals, g, and g 2 , of the MOSFETs, M x and M 2 , are complementary signals and require a dead time to avoid short-circuiting the input voltage source, V u during switching transient. When Mj is off and M 2 is on, capacitor C\ is charged to F, through £>, (see Figure 8.2(a)). When M x is on and M 2 is off, capacitor C 2 is charged to V x + V Ci = 2K, through D 2 , according to the equivalent circuit of Figure 8.2(b). Therefore, the output voltage of the basic step-up SCC of Figure 8.1 is ideally twice the input voltage. As such, this circuit is also known as a voltage doubler. However, the output voltage is usually smaller than twice the input voltage due to losses. Note that the energy transfer capacitor, C u is charged in parallel with the voltage source and discharged in series with it. Figure 8.3 and Figure 8.4 show the steady-state voltage and current waveforms of the basic step-up SCC shown in Figure 8.1 for a 25% duty cycle on Af,. Notice how the output voltage increases as C 2 is charged through Mi. When M 2 is on, C 2 discharges through the load resistor and the output voltage decreases. The average output voltage is smaller than 20 V due to the voltage drop across the nonideal-switches. 3 , a P * out -w 1 w- M, b C, — li- ft » iov dc -=- v, &» 9z \tt 10 u 1 k°2 10 u "1 ~0 Figure 8.1 Step-up converter. Switched Capacitor Converters 343 out * ^ b D, I Mz C, IpCz ^Hi VitX. M, C, V 1 + out 2^ ±°2 ~0 -o (a) equivalent circuit while M^ is on. (b) equivalent circuit while M, is on. Figure 8.2 Equivalent circuits for the basic step-up SCC. 4.0 V, 2.0 V SEL» OV 16.8878 V \ _L -V(g,)V{g z ) 16.8840 V 16.8800 V 198.00 usee • Vfcut) 198.40 usee 198.80 usee Time 1 99.20 usee 1 99.60 usee Figure 8.3 Steady-state waveforms of the basic step-up SCC for D = 25%. For an average load current, /(/*,), close to 1 7 mA, the currents through the switches, 7(Z>,) and 7(D 2 ), increase up to 45 and 135 mA, respectively. Since the charging and discharging currents are only limited by the circuit losses, they may become very large, degrading the efficiency and aggravating EMI emission. 344 Power-Switching Converters 50 mA- 0A =50 mA 200 mA n • /(Pi) LtULJLJLJLIL OA -200 mA 16.900 mA 16.875 mA SEL» 16.850 mA 190 usee 192 usee 194 usee 196 usee 198 usee 200psec Figure 8.4 Steady-state waveforms of the basic step-up SCC. Figure 8.5 shows the steady-state waveforms of the basic step-up SCC for D = 50% Note that even when the duty cycle has changed considerably (i.e., from 25 to 5ff%) the output voltage has barely changed. This proves the poor output voltage regulation that can be achieved by changing the duty cycle in this topology. 832 Basic Step-Down Converter The basic step-down SCC shown in Figure 8.6 has two modes of operation, depending on the two complementary switches M, and M 2 . In the steady state, V c > V c > 0. 1 When M, is on (V(g x ) = hi), C, and C 2 are connected in series through D 2 , as shown in Figure 8.7(a). C, is charged from the voltage source, V,. The corresponding steady-state waveforms are shown m Figure 8.8. « tne charging current/ c , </*, (see Figure 8.9), then C 2 hasto provide the rest of the load current; thus, /<- is negative when C, is charging (i.e., l Cl 7 'c, - Jr, )■ When M 2 is on, the two capacitors are connected in parallel, as displayed in Figure 8.7(b). Since V C> >V C2 , the capacitor C, provides enough current to charge C 2 and supply the load. Figure 8.9 shows the current waveforms through the two capacitors and the load. While C, is charged, C 2 discharges through the load. On the 1 "With idea) switches, V c , = Vc, = v v VJ2. Switched Capacitor Converters 345 4.0 V 2.0 V 0V F . ....j ' 16.92926 V 16.92750 V 16.92500 V SEL» 16.92347 V ■vig,) ♦ AoJ 197.11 usee 197.50 usee 198.00 (isec 198.50 (isec 199.00 usee 199.50 jisec 200.00 ^sec - V(out) Time Figure 8.5 Steady-state waveforms of the basic step-up SCC for D = 50%. ^0 Figure 8.6 Basic step-down SCC. other hand, when C, discharges, its current is large enough to charge C 2 and supply the load current. 8.2.3 Basic Inverting Converter The output voltage of the basic polarity inverting SCC as shown in Figure 8.10 is ideally at -K,. However, smaller magnitude is usually obtained due to the voltage drop across the switches. There are two modes of operation for this circuit. Capacitor C, is charged to K, when M, is on, with the polarity indicated in the equivalent circuit of Figure 8.11(a). 346 Power-Switching Converters out h^ rr-n . out : C, :Cz T * (a) equivalent circuit while M, is on. (b) equivalent circuit while A^ is on. Figure 8.7 Equivalent circuits for the basic step-down SCC. 4.0 V 2.0 V 0V 3.62060 V ,' V(Gl) 3.62055 V 3.62050 VjOUT) 2.0 mA 4 0A -3.0 mA n — ., — u f — . i 2.88475 msec 2.88500 msec 2.88550 msec 2.88600 msec 2.88650 msec 2.88700 msec ' V*) T,me Figure 8.8 Steady-state output capacitor waveforms for the basic step-down SCC. When M 2 is switched on, C\ is connected to the output capacitor, C 2 , through D 2 , transferring a negative voltage. The equivalent circuit for this mode of operation is shown in Figure 8.11(b). Switched Capacitor Converters 347 2.5 mA- OA -2.5 mA- -5.0 mA 4.0 mA OA -4.0 mA 5.0 mA 2.5 mA- OA . ■ AC,) ./(cy -3.6 mA 1.9955 1.9960 1.9965 1.9970 1.9975 1.9980 1.9985 1.9990 1.9995 • l[R-i) Time (msec) Figure 8.9 Steady-state current waveforms for the basic step-down SCC. M 1 b °i D 1 out 1k - Figure 8.10 Voltage polarity inverting converter. 8.3 ALTERNATIVE SWITCHED CAPACITOR CONVERTER TOPOLOGIES The output voltage of the basic SCC analyzed in Section 8.2 depends on the circuit topology. As such, this lack of flexibility limits their uses. Many alternative topologies have been proposed to overcome this limitation [2,3], providing a flexible conversion ratio governed by the duty cycle. This section analyzes some of these circuits. 348 Power-Switching Converters Wit /W, C, ■gp-T> + ||~ V,== V;f^ (a) equivalent circuit while M, is on. (b) equivalent circuit while A^ is oa Figure 8.1 1 Equivalent circuits for the basic polarity inverting SCC. V, :=: t 0„ t<* Figure 8.12 step-down SCC. 8.3.1 Step-Down Converter The conversion ratio of the step-down SCC proposed in Cheong et al. [2] can be fixed by choosing an appropriate steady-state value of the duty ratio. The circuit shown in Figure 8.12 has four controlled switches, M x -Ma, two energy transfer capacitors, C, and C 2 , an output capacitor, C„ and an input capacitor, Q. R^ is the load resistance. The converter has four modes of operation. The gate signals, gi-g* corresponding to the switches Mi-M 4 , are shown in Figure 8.13. The timing diagram of Figure 8.13 corresponds to a conversion ratio of 0.5. g 2 and g 3 are complementary signals with a 50% duty cycle. The gate signals g x and g 4 Switched Capacitor Converters 349 Si I 9i 93 9a s "L in IV III 1 .0 usee Time Figure 8.13 Time diagram of the gate signals. *1 \ 3 M i 3^ 'l* ■o m E/C, out J. ;Cy Co IRL "h. 4=qj V-A: ^c* il IV 1 2.0 usee ■i «* out 40) -.-.Cj, (a) equivalent circuit during mode 1. -VA- (b) equivalent circuit during mode 2. f?32 M 2 Viif ^ lie, out (c) equivalent circuit during mode 3. (d) equivalent circuit during mode 4. Figure 8.1 4 Equivalent circuits during the operating modes. are synchronously turned on at nT s and (n + 0.5)T S , respectively, g. and g 4 have the same pulse width, r on . Mode 1 is determined by M t and M 3 being both turned on; the equivalent circuit for this mode of operation is shown in Figure" 8.14(a). C\ is charged slightly higher than V X I2. The charging time, T oa , must be suffi- cient to cover the losses in the parasitic resistances and transfer a voltage V\l 2 to the output in mode 2. During mode 1, C 2 discharges into the load. 350 Power-Switching Converters Throughout mode 2, C 2 continues to discharge into the load; and Q is disconnected. In mode 3, C 2 is charged slightly higher than JV2, while the energy transfer capacitor, C\, discharges into the load. In mode 4, C 2 is disconnected and C t continues to supply the load current. The discharging times for C\ and Ci are calculated so that their respective voltages at the end of modes 4 and 2 are slightly less than V\I2. This condition is required to support a constant average output voltage with a small ripple. The duty cycle is determined by the on time of switches M x and M 3 , and defined as d='f, (8.1) where d is always less than 0.5. For other conversion ratios, the duration of modes 1 and 3 have to be adjusted in order to charge capacitors C\ and C 2 to a voltage level slightly higher than the desired output voltage. Regulation of the output voltage can be achieved by applying a negative feedback on the PWM controller. 8.4 STATE-SPACE AVERAGING MODEL In state-space averaging [4], the weighted average of the state-space descrip- tions of the switched topologies is taken to be the overall state-space description of the converter over each switching period. For a converter that commutates between two topologies during each switching cycle, the state— space equations for each topology are combined to form the over- all state-space description. Let the circuit description during the time interval AT be: x = A d x + B d u, y = Cjx + Dju. Let the circuit description during the time interval (1 - d)T be: x = >4(i_ d) x+B ( i_ d) M, y = C (I _^x + £>(i_</)W. The average state-space equations are then x=^x + Bu, y=Cx + Du, ■■M Switched Capacitor Converters where A=dA d + {\- d)A(^^, B = dB d + (l-d)B il _ d) , C=rfQ + (l-rf)C ( ,_ l0 , D = dD d + {\-d)D( X „ d) . 351 (8.5) By applying the state-space averaging method, the average state equation is obtained: x = Ax + BV u x = [V C i Vc2 Vco] y=v 2 = Vco. (8.6) Neglecting the input capacitor and the effective series resistance of the output capacitor, the state matrices are: A = B = 0/2) + d 1 CtlRs + rc,) 2C,CR 5 + r c ,) o (1/2) + d C 2 {R S + r Cl ) 1 2C 2 CR, + r c ,) 1 1 - 1 ( ! 1 ' +i)l 2C (/{ s + r Cl ) 2CotR s + r C2 ) 2CoV^ + '-c 1 ^s + <-c 2 d/C.ORs + rc,)- d/C 2 (/? s + r C2 ) , C = [0 1], y =C{-A~ l B). (8.7) Solving (8.7) for the conversion ratio gives V 2 K, 1 + ((/Js + r)/ROd + 0/2</)) ' (8.8) where R s = R sl = . . . = J?^ is the MOSFETs on resistance, r cl is the capacitor's, effective series resistance and J?l is the output resistance. Equa- tion (8.8) was simulated for different values of the load resistance and the result is plotted in Figure 8.15, which shows the conversion ratio versus the duty cycle for this converter. 352 Power-Switching Converters ill 'o 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Figure 8.15 Conversion ratio versus duty cycle. Figure 8.16 shows the voltages across the capacitors (points a, b, and out). Notice how the voltages at points a and b converge to the same value very rapidly, while the output voltage settles to 6.2 V. Figure 8.17 shows the gate signals switching at 1 MHz, and the output voltage ripple for a i? L = 20 a, resulting in a voltage ripple of 18 p,V at a load current of 300 mA. 8.4.1 Step-Up Converter The step-up SCC of Figure 8.18 is composed of the basic cell (C,, C 2 , S 2 , S 3 , and S 4 ), the voltage source V u the input switch Si, the output switch S 5 , the output capacitor C Q , and the load resistance, R L . This circuit has two modes of operation, namely the charging and the discharging modes. The equivalent circuits for the charging and discharging modes are shown in Figure 8.19(a) and (b), respectively. During the charging mode, the energy-transfer capacitors, C x and C 2 , are charged in parallel; switches 5,, S* and S 3 are switched on. Duringthe discharging mode, the capacitors C, and C 2 are connected in series by S 4 and discharged to the load through S 5 . Therefore, the voltage levels obtained by the two capacitors during the charging mode are Switched Capacitor Converters 353 ov OS « V(a) • V(b) ' V(out) 4.0 ms Time Figure 8.1 6 Voltage waveforms of the step-down SCC. 6.262120 V YYYYYVYYYVYYYYYY^ 6.26201 4 V -I -< 9.47472 msec 9.48305 msec » V(out) Time Figure 8.17 Gate signals and output voltage ripple. added during the discharging mode to boost the output voltage up to V Cl + V Cl . The maximum output voltage supplied by this circuit is 2V X . 8.4.2 n-Stage Step-Down SCC The /i-stage step-down SCC shown in Figure 8.20 provides a good regulation of the output voltage [3]. N stages are stacked on top of the output capacitor, C . Each stage is composed by a capacitorC,- and three switches, S h S is , and S lo . The energy-transfer capacitors are charged in series by closing all the 354 Power-Switching Converters + Si :^ ' -Co Figure 8.18 Step-up SCC. s, nr-n V 13 ^ S3 n—n + Q> /= -= (b) Discharging mode. Figure 8.19 Equivalent circuits for the charging and discharging modes. -8 t v . — 1__>_ S ~. ± Cn k s .* \ s 1 ■20- *". ^ ft 3 <V» 3 s - ¥ v . :^ (a) n-stage SCC topology. (b) Step down charging mode. (c) Step down dischaigingnmodo. Figure 8.20 w-Stage step-down switching capacitor converter. Switched Capacitor Converters 355 switches 5, (5, to S„), as shown in Figure 8.20(b). The voltage level at the end of the charging mode is determined by the current supplied by the charging current source provided by the switch S M functioning in the saturation region. Since the switches S, are operated at a 50% duty cycle; the voltage at the energy-transfer capacitors is controlled by the gate to source voltage of the switch S M , according to: *d = *(vgs - K T ) 2 . (8-9) This is the basic principle of current control scheme of SCC [5]. During the discharging mode, S iB and 5 fo are switched on; all the other switches are open, giving the equivalent circuit of Figure 8.20(c). The energy-transfer capacitors are discharged in parallel, adding their respective currents. The resulting voltage can be stepped down to a maximum voltage The steady-state output voltage is given by: Vo = dI m R L . (810) 8.4.3 n-Stage Step-Up SCC When it is necessary to obtain an output voltage higher than 2V\, the SCC circuit of Figure 8.18 is inadequate. The n-stage step-up SCC shown in Figure 8.21 is a good alternative, n Stages are stacked on top of the output capacitor C„. Each stage is comprised of a capacitor C, and three switches, S,-, 5 Ig , and 5 IO - The energy-transfer capacitors are charged in parallel, by closing the switches S ig and S io , as shown in Figure 8.21(b). The voltage level at the end of the charging mode is determined by the current provided by the charging current source when the switch S M is operating in the saturation region. Since the switches, S h S, B , and S IO are operated at a 50% duty cycle; the voltage at the energy-transfer capacitors is controlled by the gate to source voltage of the switch S M , according to: id = *(v GS - V r ) 2 . (8.") During the discharging mode S h S,„, and S are closed; all the other switches are open, giving the equivalent circuit of Figure 8.21(c). The energy-transfer capacitors are connected in series, adding their respective voltages. The resulting voltage can add up to nV x . This voltage is then transferred to Co, stepping up the input voltage to a higher level. With proper control, this circuit is capable of providing the step-up and the step-down functions. Other boost converter topologies and control strategies are discussed in Chung and Mok [6J. 356 Power-Switching Converters (a) oslage SCC topology. b) Step-up charging mode. (c) Step-up dischaiging mode. Figure 8.21 /i-Stage step-up switching capacitor converter. 8.5 BI-DIRECTIONAL POWER FLOW SCC The SCCs presented in Sections 8.4.1 to 8.4.3 are only capable of transfer- ring power from the source to the load. For applications like DC motor control or battery charging it may be necessary to permit the power flow in both directions. This section presents various topologies of SCC with bi- directional power flow. 8.5.1 Step-Up Step-Down Converter Chung and Chow [7] presented a SCC with bi-directional power flow based on a single structure that can provide the step-down and step-up functions. The basic bi-directional cell is shown in Figure 8.22. The cell converts electric power from the high-voltage side (HV) to the low-voltage side (LV). The switches S, are operated in switched mode, while Q s is either in cutoff, saturation, or the triode region. Q s is used in the saturation region to control the charging current of the energy-transfer capacitor, C, thus, linearly increasing the capacitor's voltage. The drain current of Q s is given by the MOSFETs equation in the saturation region: f D = a:(v gs - V-xf (8-12) Switched Capacitor Converters 357 >HV > High-voltage side (HV) Vhv < tv Low-voltage side (LV) "LV Figure 8.22 Basic bi-directional converter cell. The cell can function either in the step-down or in the step-up modes. When the step-down operation is performed, energy is transferred from HV to LV. During the step-up operation, the power flow is from LV to HV. 8.5. 1. 1 Step-Down Operation Figure 8.23 represents the two equivalent circuits for the step-down operation. Two modes of operation can be identified. During mode 1, Si is closed, Q s is in saturation, and C is linearly charged with a current Z^c for a duration r on = TJ2. At T = t on , C will be charged to a voltage that is slightly higher than the voltage at LV, in order to compensate for parasitic resistances and diode voltage drops. During mode 2 (TJ2 < t < T s ), S 2 and D 3 conduct. All other switches are open. C is then disconnected from HV and it transfers its stored energy to LV. K- -&- High voltage side (HV) JlX ■-C C )lsdch Low voltage side (LV) (a) Mode 1 W. High voltage side (HV) 1v 4=C Low voltage side (LV) *tv JOS (b) Mode 2 Figure 8.23 Equivalent circuits during the step-down operation. 358 Power-Switching Converters 8.5.1.2 Step-Up Operation Figure 8.24 shows the two equivalent circuits for the step-up operation. During mode 1, D 2 is closed and Q, is in saturation mode. All other switches are open. C is linearly charged from the LV side through D 2 and Q s with a current 7 npch for a duration TJ2. At TJ2, the capacitor is charged to a voltage level that is slightly higher than the voltage difference between the voltages at HV and LV; i.e., V c = V HV — K LV , in order to compensate for the component losses. Mode 2 extends from TJ1 to T s ; during this mode D, and S 3 conduct, while all the other switches are open. C is then connected in series with the LV side to supply energy to the HV side. The voltage at HV is then higher than at LV. The complete bi-directional converter is shown in Figure 8.25, where two basic cells are connected in parallel. The input and output capacitors are needed to smooth the two terminal voltages. The two cells are operated in antiphase, that is, if the converter operates in the step-down mode, then both cells operate in the step-down mode. However, when cell 1 is in mode 1 , cell 2 hw\ J-— L tv High voltage side(HV) Low voltage side (LV) hn\ High voltage side (HV) ? r <= C _k Low voltage side (LV) Olupch J_ (a) Mode 1 (b) Mode 2 Figure 8.24 Equivalent circuits during the step-up operation. CelM + o - C^y : C — o Cell 2 Figure 8.25 Bi-directional converter. Switched Capacitor Converters 359 js in mode 2, and vice versa. For the step-down mode, the HV side is connected to a voltage source and the LV side is connected to a load, then /HV = /sdch- < 8 - 13 ) For the step-up mode, the HV side is connected to a load resistance while the LV side is connected to a voltage source. Thus, /LV = -l'HV + /„pch- < 814 > Since I^ch, / up ch, and i H v are constants, the input current at both sides is also constant and continuous, introducing only low-level EMI. The HV and the LV voltage levels for the steady-state operation can be found by applying the state-space averaging technique, resulting in v L v = /Ach *lv = K{ K cont - V r ?R LV ( 8 - } 5 > and v H v = /Bch*Hv = K(V conl - ^t) 2 *hv. ( 816 > It is obvious that the output voltage in both directions can be controlled by •com- . . . A typical application for a bi-directional converter is shown in higure 8.26, where the HV side is connected to a rechargeable battery and the LV side is connected to the supply rail. In normal operation, the battery is charged from the supply rail through the converter. When an outage in the supply rail occurs, the converter will transfer the stored energy in the battery back to the supply rail. 8.5.2 Luo Converter Luo et al. [8] introduced a switched capacitor four-quadrant DC-DC converter, namely the Luo converter. It can perform step-up or step-down DC-DC voltage conversion in all the four quadrants using a low switching frequency. Since the frequency is low compared to the classical converters, the EMI is very weak. It has been proven to provide high efficiency and high power. It is also potentially capable of achieving a high-output current that is needed to charge the modern automobile power supply systems. The Luo converter is shown in Figure 8.27. It consists of eight switches, two capaci- tors, the source voltage V u and the load voltage V 2 (e.g., a battery or DC motor back EMF). The energy-transfer capacitors, C, and C 2 , have the same value. There are four modes of operation for this converter. 360 Power-Switching Converters .'-> K? , rfe High voltage side (HV) : :C "Lv Low vollage side (LV) ^hQ I 7 irr- High voltage skte (HV) ::C ^v Low vollage side (LV) v.- Supply rail Figure 8.26 Bi-directional converter application. S, _=_Redlan)eable IfH -*■ baiter, y|l£ Figure 8.27 Switched capacitor Luo converter. Switched Capacitor Converters 361 First quadrant operation: the energy is transferred from the source to the positive voltage load. This mode is also called the forward motoring operation. V x , V 2 , I x , and / 2 are all positive. Second quadrant operation: the energy is transferred from the positive voltage load to the source. The second quadrant is also called the forward regenerative braking operation. V x and V 2 are positive, while /j-and I 2 are negative. Third quadrant operation: the energy is transferred from the source to the negative voltage load. This mode is also called the reverse motoring operation. V x and I x are positive, while V 2 and I 2 are negative. Fourth quadrant operation: the energy is transferred from the negative voltage load to the source. The fourth quadrant is also called the reverse regenerative braking operation. V x and I 2 are positive, while I x and V 2 are negative. Each mode of operation has two possible operating conditions, depending on the magnitudes of the input and output voltages; that is, V\ > I ^l and V x < I V 2 \. Therefore, there is a step-down mode and a step- up mode for the operation in each quadrant. Each condition has two states: ON and OFF. Usually, each state has a different duty cycle. First quadrant operation. In this mode of operation, the capacitors C x and C 2 transfer the energy from the source to the load. The output voltage is positive. The equivalent circuits for the step-down mode (V x > V 2 ) are shown in Figure 8.28. Since V x > V 2y the two capacitors C x and C 2 are charged and discharged in parallel. During the ON state, the switches S x , S 4 , S 6 , and S s are closed, while all the other switches are open. The two capacitors C x and C 2 are charged in parallel via the circuit V x -S x — C x //C 2 — S 4 , and the voltage across the capacitors C x and C 2 increases according to the indicated polarity in Figure 8.28(a). During the OFF state, switches S 2 , S 4 , 5 fo and S 8 are closedwhile all the other switches are open, resulting in the equivalent circuit of Figure 8.28(b). In this case, the capacitors C X IIC 2 are discharged via the circuit S 2 — V 2 —S 4 — C X IIC 2 , and the voltage across the capacitors C x and C 2 decreases. "1* Jk. Se Sb T S> S 4 *" 2 V* "(a) First quadrant, step-down, ON state. (b) First quadrant, step-down, OFF state. Figure 8.28 Equivalent circuits for the first quadrant step-down operation. 362 Power-Switching Converters The equivalent circuits for the step-up mode (F, < V£ are shown in Figure 8.29. Since K, < V 2 , the two capacitors C x and C 2 are charged in parallel and discharged in series. 2 During the ON state (Figure 8 -29(a)), switches S,, S4, S 6 , and S 8 are closed and all the other switches are open . In this case, capacitors C]//C 2 are charged via the circuit V l -S l -Ci//C 2 -S A , and the voltage across the capacitors d and C 2 increases. During the OFF state (Figure 8.29(b)), switch S 2 , S 4 , and S 7 are closed and all the other switches are open. In this case, capacitors C, and C 2 are discharged via the circuit S 2 — V A —S A —C X —S 1 ~C 2 , and the voltages across the capacitors C t and C 2 decrease. Second quadrant operation. In this mode of operation, capacitors Q and C 2 transfer the energy from the load to the source. The output voltage is positive. The equivalent circuits for the step-up mode ( K, > V 2 ) are shown in Figure 8.30. Since V x > V 2 , the voltage at the load has to be stepped-up to the source level; therefore, the two capacitors C\ and C 2 are charged in parallel during the ON state and discharged in series during the OFF state. During the ON state (Figure 8.30(a)), the switches S 2 , S 4 , S 6 , and S 8 are closed. In this case, the capacitors C\IIC 2 are charged via the circuit V 2 —S 2 —Ci/K: 2 —S4, and the voltage across the capacitors C\ and C 2 in- creases. During the OFF state, the switches Si, 5 4 , and S 7 are closed, as shown in Figure 8.30(b). In this case, the capacitors C\ and C 2 are dis- *& =f c i 2 S 4 %Wi (a) First quadrant, step-up, ON state. a* (b) First quadrant, step-up, OFF state. Figure 8.29 Equivalent circuits for the first quadrant step-up operation. v* T Ci Cz IS. ±v 2 4 *v* (a) Second quadrant, step-up, ON state. (b) Second quadrant, step-up, OFF state. Figure 8.30 Equivalent circuits for the second quadrant step-up operation. This is the so-called voltage lift technique. Switched Capacitor Converters 363 charged via the circuit Si-V l -S 4 -C 2 -S 7 -C 1 , thus, the voltages across the capacitors C\ and C 2 decrease. The equivalent circuits for the step-down mode (V x < V 2 ) axe shown in Figure 8.31. Since V y < V 2 , the two capacitors C x and C 2 are charged and discharged in parallel. During the ON state, the switches S 2 , S 4 , S 6 , and S 8 are closed. In this case, the capacitors C X IIC 2 are charged via the circuit V 2 -S 2 -C X IIC 2 -S 4 ; thus, the voltage across the capacitors C, and C 2 increases. During the OFF state, the switches S,, S 4 , S 6 , and 5 8 are closed. In this case, the capacitors C t //C 2 are discharged via the circuit S, — K, - S 4 - C\tl C 2 , and the voltage across the capacitors C\ and C 2 decreases. Third quadrant operation. In this mode of operation, the capacitors Ci and C 2 transfer the energy from the source to the load. The output voltage, V 2 , is negative. The equivalent circuits for the inverting step-down mode (Vi >\V 2 \) are shown in Figure 8.32. Since V x > \V 2 \, the two capacitors C, and C 2 are charged in parallel. During the ON state (Figure 8.32(a)), the switches Si, S 4 , S fo and S 8 are closed. In this case, the capacitors C X IIC 2 are charged via the circuit V 1 -S 1 -C l /JC 2 -S 4 , and the voltage across the capacitors C x and C 2 increases. During the OFF state (Figure 8.32(b)), the switches S 3 , S5, S 6 , and S 8 are closed. The capacitors d and C 2 are discharged via the circuit 5 3 _ v 2 -Ss-C\HC 2 and the voltage across them decreases. The equivalent circuits for the inverting step-up mode (V s < \V 2 \) are shown in Figure 8.33. Since F, < \V 2 \, the two capacitors C, and C 2 are v& Bo— iQ> fc. %v z vA ^v, (a) Second quadrant, step-down, ON state, (b) Second quadrant, step-down, OFF state. Figure 8.31 Equivalent circuits for the second quadrant step-down operation. «4 Jk. + 1T"%_ **4 V1* ]^- Ss C, Sb 3Ss (a) Third quadrant, step-down, ON state. (b) Third quadrant, step-down, OFF state. Figure 8.32 Equivalent circuits for the third quadrant step-down operation. 364 Power-Switching Converters charged in parallel during the ON state and discharged in series during the OFF state. During the ON state (Figure 8.33(a)), the switches Si, S 4 , Se, and S 8 are closed. The capacitors C\ and C 2 are charged via the circuit V\— Si— C\IIC 2 — S 4 , increasing the voltage across the capacitors. During the OFF state (Figure 8.33(b)), the switches S 3 , S 5 , and S 7 are closed. The capacitors d and C 2 are discharged via the circuit S 3 -K 2 -S5-C|-S 7 -C 2 , decreasing their voltages. Fourth quadrant operation. In this mode of operation, capacitors Q and C 2 transfer the energy from the load to the source. The output voltage, V 2 , is negative. The equivalent circuits For the inverting step-up mode (V x > | K 2 |) are shown in Figure 8.34. Since V x > | V 2 \, the two capacitors C, and C 2 are charged in parallel during the ON state and discharged in series during the OFF state. During the ON state (Figure 8.34(a)), the switches S,, S s , S 6 , and S 8 are closed. In this case, the capacitors C\IIC 2 are charged via the circuit V 2 —S 3 —Ci//C 2 —S 5 , and the voltage across the capacitors Q and C 2 increases. During the OFF state (Figure 8.34(b)), the switches Si, S 4 , and S 7 are closed. The capacitors C\ and C 2 are discharged via the circuit Si— V\— S 4 — C 2 — S7— Ci and the voltage across the capacitors decreases. The equivalent circuits for the inverting step-down mode (V x < \V 2 \) are shown in Figure 8.35. Since V t < | V 2 \, the two capacitors C x and C 2 are charged and discharged in parallel. During the ON state (Figure 8.35(a)), the switches S 3 , S 5 , S fo and S 8 are closed. In this case, the capacitors Ci//C 2 v& Ss i m v & K C, Sj ¥*% (a) Third quadrant, step-up, ON state. (b) Third quadrant, step-up, OFF state. Figure 8.33 Equivalent circuits for the third quadrant step-up operation. "i* K-r Si 4C2 piv^v-t. |s 4 i %v 2 (a) Fourth quadrant, step-up, ON state. (b) Fourth quadrant, step-up, OFF state. Figure 8.34 Equivalent circuits for the fourth quadrant step-up operation. Switched Capacitor Converters 365 V& I s * -1 C, fk^p *^2 (a) Fourth quadrant, step-down, ON state, (b) Fourth quadrant, step-down, OFF state. Figure 8.35 Equivalent circuits for the fourth quadrant step-down operation. are charged via the circuit V 2 — S 3 — Cx//C 2 —Ss, and the voltage across them increases. During the OFF state (Figure 8.35(b)), the switches S u S 4 , S 6 , and S 8 are closed. The capacitors C x and C 2 are discharged via the circuit S\—Vi—S4—Ci//C 2 , and the voltage across them decreases. 8.6 RESONANT CONVERTERS Hard switching SCCs have the disadvantages of high switching current that induces EMI and exposes the switches to high stresses. Also, the regulation of the output voltage is poor. Soft-switching SCC can alleviate some of these problems. In 1998, Cheng [9,10] presented a new topology of switched capacitor converters, which can operate at a high switching frequency with reduced EMI. The new circuit utilizes smaller numbers of switches, which switch at zero-current. Thus, the circuit can operate at a high switching frequency with a high efficiency. However, a small inductor is needed in this type of resonant SCC. 8.6.1 Zero-Current Switching A family of zero-current switching switched capacitor converters, consisting of double mode, inverting mode, and half mode functions are proposed by Cheng [4]. These circuits use smaller number of active switches and diodes than the classical switched capacitor converter topologies. All the devices are zero-current switched; therefore it is suitable for the operation at high switching frequencies. The characteristic of zero-current switching minim- izes the losses and the EMI, and hence, the switching frequency can be further increased, resulting in smaller capacitor sizes. This circuit uses two controlled switching devices, two diodes, one resonant inductor, one energy-transfer capacitor, and one output filter capacitor. One switch is used to charge the energy-transfer capacitor and the other one is used to discharge it. The resonant inductor is usually very small, and hence, it can still be integrated. 366 Power-Switching Converters Wm Figure 8.36 shows a family of zero-current switching SCC [9]. Each circuit uses two controlled switches and a small resonant inductor. The resonant inductor, L T , is connected in series with the energy-transfer capaci- tor to create a resonance cycle when each of the switches Q\ or Q 2 is switched on. The switches are connected in series with the resonant inductor, creating a zero-current turn-on mechanism. Once the resonant current reaches the peak value, it decreases to zero; after that, it cannot reverse polarity because the diodes stop the current from reversing. Figure 8.37 shows the simulated waveforms of the double-mode top- ology under steady-state conditions. The circuit parameters used in the simulation are:/ s = 200 kHz, dead time = 50 ns, V s = 50 V, C, = 2.2 jif, C 2 = 2.7 M-f, L T = 0.1 w.Hy, and R^ = 50«. The operation of the circuit can be described by four states of oper- ation. The currents of the switches start resonating from zero and the conduction stops when the currents return to zero. This creates the zero- current turn-on and turn-off condition for the two switches. The duty-cycle of the two complementary switches is about 50% and can be varied to less than 50% if output voltage regulation is required. State 1 (Figure 8.38(a)) [f - f i]. When Q 2 is turned on at t = to, Q x is turned off; £ r and C\ start to resonate. Due to l^, Q 2 is turned on with zero current. C 2 is discharged to the load /? L - This state is represented by 02 Dt H i M 9 « + ^j J Cz: 9 -^l Qz flLVVj (a) Double mode ZCS SCC. (b) Inverting mode ZCS SCC. (c) Half mode ZCS SCC. Figure 8.36 Family of the zero-current switching SCC. Switched Capacitor Converters 367 215.0 216.0 . wort) Figure 8.37 Simulated waveforms of the ZCS SCC. ir-o 1 + L ' + r *?- 1 -Cz : So 2 1 - Fk V *W -« — (a) State I. (b) State II. V.# °i i^ \cg m v *^ (c) State III. (d) State IV. §1 Figure 8.38 Equivalent circuits of the double-mode SCC. »£,= V — V s c, ° sin(a>,0, V C) = V s + (K Cl0 - V s ) cos (*>,<), f^ jCz ; :« t (8.17) 368 Power-Switching Converters where V c>o is the initial voltage of C\ at t = t and o> t = \/y/L r C\. L T and C, resonate for half a cycle and the resonance stops because D\ and D 2 , become reverse-biased. State 2 (Figure 8.38(b)) [t , — /J- In this mode, the currents through the inductor and the switches are zero. C 2 is still discharging to the load. Q 2 is switched off at zero current at t = t 2 . State 3 (Figure 8.38(c)) [t 2 — f 3 ]. <2i is turned on with zero-current at t = t 2 . L T , Q, and C 2 start to resonate. i L ^ begins increasing from zero towards the negative cycle. The resonance equations of the inductor and capacitors depend on the size of the load. Their equations for a large R L can be approximated as: sm (a>„i), L T (o„ V d Vc ' = C7T^ (1 ~ cos ( w "0)+ K m , (8.18) V d Vci = C 2 L I a^ (1 ~ COS ^"'^ + Kca " where « n = l/yi^, Cp=C,//C 2 and K rf = (K s - K Cl0 - V C J. (8.19) This state terminates after i Lr resonates back to zero, and D t and D 2 are reverse-biased. State 4 (Figure 8.38(d)) [f 3 — f 4 ]. i ir is zero and C 2 is discharged to the load. Q, is turned off at zero current when t = t 4 . i 8.6. 1. 1 Condition of Zero-Current Switching If the duty cycles of Q\ and~Q 2 are d\ and d 2 , respectively, the condition for zero-current switching of Q\ is rf,r s > — . (8.20) On The condition for zero-current switching of Q 2 is d 2 T s > — , (8.21) where T s is the switching period. Switched Capacitor Converters 369 8.7 LOSSES ON SWITCHED-CAPACITOR POWER CONVERTERS [11] One important fact, which many designers may tend to overlook, is the presence of losses in SCC. Consider the circuit of Figure 8.39, representing the series connection of a voltage source, an ideal switch, and a capacitor. Assume that the initial voltage on the capacitor is v c (0~) = 0, the voltage at the source is V > 0, and that the switch is closed at f = 0. The Laplace transform of the current is given by I(s) = sCV e (s) for an input voltage step (8.22) (8.23) in that case, I(s) = CV (8.24) by applying the inverse Laplace transform; the temporal response is obtained as i(0 = CVd(i). (8.25) The amount of lost energy during the charging process can be calculated by comparing the energy delivered by the source and the energy stored in the capacitor. The energy delivered by the source is [ Vi(t) dt = [ CV 2 d(i) dt = CV 2 . o o- (8.26) Sw, _+ =? c Figure 8.39 Evaluating SCC losses. '^SH 370 Power-Switching Converters The energy stored in the capacitor is E c =jCV 2 . (8.27) Therefore, the energy lost in the charging process is £v-jET c =icK 2 . (8.28) There are no lossy components in the circuit. Where did the energy go? If a resistance R is connected in series with the capacitor, then the loss can be calculated by oo \[V-v c {t)]i(t)dt. (8.29) Irrespective of the value of the resistor, the final energy in the capacitor remains the same, given by Equation (8.27). If we make the resistor smaller, in the limit when R — » 0, the current amplitude tends to oo and the loss still takes a finite value. Therefore, if a capacitor is charged by a voltage source whose magnitude differs from the initial voltage of the capacitor, then a fixed amount of energy is lost, equal to i c {AVf (8.30) will always accompany the charging process, where AKis the step change in the capacitor voltage. PROBLEMS 8.1. Find the state-space average model for the step-up converter of Figure 8.1. 8.2. Find the voltage conversion ratio of the converter in problem 8.1. 8.3. Find the state-space average model for the step-up converter of Figure 8.18. 8.4. Find the voltage conversion ratio of the converter in problem 8.3. 8.5. Use Ref. [3] to determine Equation (8.10). 8.6. Calculate the efficiency of the step-up SCC of Figure 8.1: (a) consider ideal components, (b) consider the losses in the MOSFETS and diodes. Switched Capacitor Converters 371 8.7. Obtain the state-space averaged model for the double mode ZCS SCC of Figure 8.36(a). 8.8. Analyze the inverting mode ZCS SCC of Figure 8.36(b) and derive the equations describing each operating mode. 8.9. Obtain the state-space averaged model for the inverting mode ZCS SCC of Figure 8.36(b). 8.10. Analyze the half mode ZCS SCC of Figure 8.36(c) and derive the equations describing each operating mode. 8.1 1 - Obtain the state-space averaged model for the half mode ZCS SCC of Figure 8.36(c). REFERENCES 1. K. Kuwabara and E. Miyachika. Switched-capacitor DC-DC con- verters, Telecommunications Energy Conference, INTELEC '88, 1988, pp. 213-218. 2. S.V. Cheong, S.H. Chung, and A. Ioinovichi. Development of power electronic converters based on switched-capacitor circuits, Vol. 4, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS '92, 1992, pp. 1907-1910. 3. K.D.T. Ngo and R. Webster. Steady-state analysis and design of a switched-capacitor dc-dc converter, Record of the 23rd Annual IEEE Power Electronics Specialists Conference, Vol. 1, PESC '92, 1992, pp. 378-385. 4. R.D. Middlebrook and S. Cuk. A general unified approach to modeling switching-converter power stages, IEEE Power Electronics Specialists Conference Record, 1976, pp. 18-34. 5. H.S.H. Chung, S.Y.R. Hui, S.C. Tang, and A. Wu. On the use of current control scheme for switched-capacitor dc-dc converters. IEEE Trans. Industrial Electron., 47(2), 238-244, 2000. 6. H. Chung and Y.K. Mok. Inductorless dc-dc boost converter using switched-capacitor circuit, IEEE International Symposium of Circuits and Systems, 1997, pp. 925-928. 7. H.S.H. Chung and W.C. Chow. Development of a switched-capacitor- based dc-dc converter with bi-directional power flow, IEEE Trans. Circuits Syst. I: Fundamental Theory and Applications, 47(9), 1383- 1389, 2000. 8. F.L. Luo, H.Y. Muhammad, and M.H. Rashid. Switched capacitor four-quadrant dc/dc luo-converter, Record of the IEEE Thirty-Fourth IAS Annual Meeting Conference on Industry Applications, Vol. 3, 1999, pp. 1653-1660. ■31 372 Power-Switching Converters fl ^* 9. K.W.E. Cheng. New generation of switched capacitor converters &> Record of the 29th Annual IEEE Power Electronics Specialists Confer- S ence, Vol. 2, PESC 98, 1998, pp 1529-1535. M 10. Y.C. Lin and D.C. Liaw. Parametric study of a resonant switched capacitor dc-dc converter, Proceedings of IEEE Region 10 Inter- national Conference on Electrical and Electronic Technology, Vol 2 TENCON, 2001, pp. 710-716. ' ' 1 1 . C.K. Tse, S.C. Wong, and M.H.L. Chow, On lossless switched-capaci- tor power converters. IEEE Trans. Power Electron., 10(3), 286-291 1995. i. ■ Simulation of Switching Converters 9.1 INTRODUCTION As the complexity of the power electronic circuits and systems increases^ simulation has replaced breadboarding as a means of verifying and analyz- ing these complex circuits or systems. It has become a cost-efficient way to design many complex power electronic circuits or systems. Both large- and small-signal simulations can be performed on switching converters. Large- signal simulations yield the circuit behaviors such as the bias points for the switching converters. On the other hand, small-signal simulations usually require the knowledge of small-signal behaviors of switching converters through analytical models. It should be noted that small-signal simulations do not provide the normal electronic circuit behaviors as in actual switching converters. Both large- and small-signal simulations should be performed to better predict and verify the design for the switching converters. In this chapter, several simulation tools such as SPICE, MATLAB, and Simulink are discussed. Some prior elementary knowledge in SPICE, MATLAB, and Simulink are assumed. The averaged state-space and transfer 373 374 Power-Switching Converters function models for switching converters will be illustrated. Examples on the calculations of system poles, feedback gains, closed-loop system matrix, frequency, and transient responses will be discussed. 9.2 PSP1CE CIRCUIT REPRESENTATION SPICE is a general-purpose circuit analysis program widely used in the simulation of electronic circuits. SPICE is an acronym for Simulation Pro- gram with Integrated Circuit Emphasis. It was developed by the Integrated Circuit Group of the Electronic Research Laboratory at the University of California, Berkeley, California in the late 1960s and was released to the public in 1972 [1]. Over the years, SPICE has gone through many upgrades. The most recent version, SPICE3, is written in C language for easier port- ability. SPICE became popular when MicroSim, in 1984, introduced a personal-computer (PC) version of SPICE known as PSpice. The availability of the student-version of PSpice has revolutionized many electrical engin- eering curriculums. This is evident by the addition of PSpice utilizations to many popular electrical engineering textbooks. MicroSim was acquired by OrCad, and the latter was acquired by Cadence. At the time this book is written, the Cadence Suite 2002 Lite version of PSpice is available free for users. There are other free evaluation versions of SPICE-based circuit simu- lators from other vendors as well, such as the Electronics Workbench and Intusoft SPICE ICAP/4. The use of SPICE is increasing among the electrical engineering professionals, at the point that it is becoming an industrial standard. Most electronic component vendors now provide Spice model for their products. As in many other circuit simulation programs, PSpice requires accur- ate circuit element models in order to faithfully simulate the operation of the switching converter. PSpice remains a viable simulation tool for the switch- ing converter despite its many limitations. Difficulties in PSpice simulation of switching converters arise from the fact that practical switching converters are switching systems with feedback. Switching converters with multiple feedback paths sometimes fail to con- verge or take considerable time to do so using the PSpice default conditions. Performing transient analysis on switching converter circuit often takes a considerable execution time, since the internal time step must be short compared to the switching period. In general, simulations of switching converters must extend over a few switching cycles to reach their steady- state conditions. Many of the PSpice simulations of the switching converters presented in this chapter can be performed using the student or the Lite versions of PSpice, which are limited versions of the full simulation tool. Simulation of Switching Converters 375 Four different methods of representing a switching converter in PSpice are discussed. The classical text file input in a .CIR file is replaced by graphical input files in the latter versions of PSpice. Based on the student version of OrCad PSpice 9.2, a switching converter is represented by control blocks and behavioral models, which permits a rapid implementation to check its functionality. A more accurate simulation, using vendor-provided controller models, can be performed later. Two examples showing how to evaluate an open-loop and a closed-leop switching converters will be illus- trated. Some guidelines to solve the common convergence problems in PSpice are discussed. 9.3 PSPICE SIMULATIONS USING .CIR The first versions of Spice used a text file with a .CIR extension containing the circuit description as the circuit input file. The actual versions of Spice support a graphical input interface that automatically generates the .CIR file. We do not recommend the use of the text file input method since the graphical input is more easily interpreted, unless you need to write your own subcircuit or modify an existing one. Nevertheless, for the sake of complete- ness, we dedicate this subsection to an example of the circuit file description. Vendor models (subcircuits or macromodels) are often provided as a text file according to the .CIR syntax. 9.3.1 An Ideal Open-Loop Buck Converter An ideal buck converter can be simulated using a pulse voltage source to replace the switching transistor as shown in Figure 9.1. The input voltage source is a pulse train having an amplitude equal to the DC input voltage and a duty cycle identical to the steady-state duty cycle of the switching con- verter. This is evident from the nonlinear continuous equivalent circuit of the ideal buck converter shown in Figure 6.47. Assuming a switching frequency © io © 10 mH p : Co < 100 jiF >50 ® Figure 9.1 An ideal buck converter with a pulse voltage source. 3 76 Power-Switching Converters of 1 kHz and a steady-state duty cycle of 50%, the program listing is as follows: Open-loop buck converter simulation 'SWITCHING FREQUENCY = 1 KHZ; DUTY CYCLE = 50% VPWM 1 PULSE(0 10 1US 1US 0.5MS 1 MS) *PULSE PWM SOURCE: PULSED VOLTAGE = 10 V, RISE TIME = 1 US, *FALLTIME = 1 US, PULSE WIDTH = 500 US, PERIOD = 1 MS. L0 1 2 10m C0 2 0100U RL2 05 -TRAN 50US 20MS -OPTION ITL5 = -PROBE -END The probe statement is to activate the PSpice graphic postprocessor that calculates and displays the waveforms. The 50 us transient step yields 200 switching cycles for a total of 400 iterations. Since PSpice continuously adjusts the time step for the transient analysis, it actually takes more than 400 iterations to complete the simulation. The ITL5 = on the option statement resets the transient analysis iteration limit to enable PSpice to execute more than 5000 transient analysis iterations. PSpice calculates the DC bias points before the execution of the transi- ent analysis. Figure 9.2 shows the output voltage, the inductor current, and the capacitor current waveforms of the simulated converter. The output voltage reaches its steady-state value of 5 V at about 5 ms, which corresponds to five switching cycles. As shown, the inductor and capacitor currents are in phase with each other, but they lead the output voltage by 90°. The output ripple voltage and the inductor ripple current are 300 mV and 0.4 A, respect- ively, as shown in Figure 9.2. The capacitor ripple current is 235 mA. The average capacitor currentis initially positive since it does not store any energy at the beginning of the singulation. However, the average capacitor current is zero during the steady-state operation, as shown in Figure 9.2. The theoretical output ripple voltage according to Equation (2.20) is %J?LC 8(1000) 2 10x 10-MOOx lO" 6 = 0.3125 V (9.1) in comparison to the simulated value of 0.3 V. The theoretical inductor ripple current from Equation (2.14) is Simulation of Switching Converters 8.0 377 -4.0 s 5 ms 10 ms • V,(RL) o /(CO) ♦ /(LO) Time 15 ms 20 ms Figure 9.2 Output voltage (K,(RL)), inductor current (/(LO)) and capacitor current (/(CO)) waveforms of the simulated buck converter with an output induct- ance of lOmH. A/ = DV^l-D) 0.5(10)(1 - 0.5) AL 1000 x 10 x 10- 3 = 0.25 A, (9.2) which is in good agreement with the simulated inductor ripple current of 0.25 A. The inductor ripple current is approximately equal to the capacitor ripple current, because there is no load modulation. Increasing the output inductance of the buck converter to 50 mH reduces the output ripple voltage and the inductor ripple current to 60 mV and 50 mA, respectively, as shown in Figure 9.3. The capacitor ripple current also reduces to 47 mA. These reductions are expected in accordance with Equations (2.20) and (2.14). However, the output voltage response is more sluggish compared with the buck converter with a 10-mH output inductor. It reaches its steady-state value at about 50 ms or 50 switching cycles. Decreasing the output inductance to 5 mH increases its output ripple voltage and inductor ripple current to 0.6 V and 0.5 A, respectively, as shown in Figure 9.4. The capacitor ripple current also increases to 479 mA; however, the output voltage response depicts an underdamped characteris- tic. It reaches its steady-state value at about 4 ms. The onset of the discon- tinuous mode of operation for a constant load current occurs at about 1.25 mH, as predicted from Equation (2.31). Figure 9.5 shows the waveforms of the simulated converter with an output inductance of 1.25 mH. Although the average output voltage remains at about 5 V, the ripple voltage increases -m Power-Switching Conveners 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms 45ms 50ms . ((CO)- /(LO)» V(2) Time Figure 9.3 Output voltage ( K(2)), inductor current (/(LO)), and capacitor current (/(CO)) waveforms of the simulated buck converter with an output inductance of 50 mH. a/vvwwwvn AAAAAA/V 4.0- J M[C2) 2.0 / HLO) k/VV\/\A/V\/VVV\ /WWVW 0- ^XA^N/v^/vv^v^yvx AAWVVVA -1.0- /(CO) 0s 5 ms « V(2) - «LO) - «CO) 10ms Time 15 ms 20 ms Figure 9.4 Output voltage ( K(2)), inductor current (/(LO)), and capacitor current (/(CO)) waveforms of the simulated buck converter with an output inductance of 5mH. to 2.3 V. In addition, the steady-state inductor current begins to show discon- tinuities and reaches a peak value of 1.96 A. The simulated output capacitor ripple current is 1 .9 A. Increasing the output capacitance from 100 to 500 u,F, while keeping the output inductance at 10 mH, yields an underdamped output Simulation of Switching Converters 379 Os 5 ms - V*2) -JOO)- ICO) 10 ms Time Figure 9.5 Output voltage ( K(2)), inductor current (/(LO)), and capacitor current (/(CO)) waveforms of the simulated buck converter with an output inductance of 1.25 mH. voltage response, as shown in Figure 9.6. The output voltage overshoots to 6 V and reaches its steady-state value at about 25 ms or 25 switching cycles. The output ripple voltage as well as the inductor ripple cun-ent, decrease to 60 mV and 0.25 A, respectively. The capacitor ripple, current is approximately 0.25 A. Increasing the output capacitance to IOOJjlF, while keeping the same inductance of 1.25 mH yields an output ripple voltage of 0.57 V, an inductor ripple current of 1.96 A and a capacitor ripple current of about 1.96 A, as 0s 5ms »- V(2) • J(LO) - /(CO) 10ms Time 15 ms Figure 9.6 Output voltage (K(2)), inductor current (/(LO)), and capacitor current (/(CO» waveforms of the simulated buck converter with an output capacitance of 500 u.F and output inductance of 10 mH. Power-Switching Converters Os 5 ms - Vp) - HLO) - «CO) 10ms Time 20 ms Figure 9.7 Output voltage ( K(2)), inductor current (/(LO)), and capacitor current (/(CO)) waveforms of the simulated buck converter with an output capacitance of 500 jiF and output inductance of 1.25 mH. shown in Figure 9.7. It can be seen that the increase in output capacitance only reduces the output ripple voltage according to Equation (2.20). The inductor and capacitor ripple current waveforms are similar to the case of a 100-p.F- output capacitor since the ripple components of the signal are inversely pro- portional to the output inductance and not the output capacitance. The harmonic contents of the output voltage and input current can be obtained by performing a Fourier analysis using PSpice with the addition of the following statement to the 1 previous program listing: -FOUR 1 khz v(2) , Note that Fourier analysis must be performed in conjunction with transient analysis. Table 9.1 shows the Fourier analysis results for the output voltage and input current of the simulated buck converter with an output inductance of lOmH and an output capacitance of 100 pF. As can be seen, only the odd harmonics of the output voltage and the input currents are significant. The fundamental harmonic components of the output voltage and input current are 0.14 V and 0.1 A, respectively. The third and higher harmonic compon- ents are progressively smaller. The output inductance and capacitance were increased to 50 mH and 500 pF, respectively, and the Fourier analysis was obtained. Increasing the output inductance and output capacitance reduces the harmonic content of the converter as can been inferred by comparison of the values in Table 9-1 to Table 9.4. Simulation of Switching Converters 381 Table 9.1 Fourier Components of the Output Voltage of the Simulated Buck Converter with L = lOmH and C — 100 p.F I •**• FOURIER ANALYSIS FOURIER COMPONENTS OF TRANSIENT RESPONSE V(2) DC COMPONENT = 5.000999E+00 HARMONIC FREQUENCY FOURIER NORMALIZED PHASE NORMALIZED NO. (H2) COMPONENT COMPONENT (DEG) PHASE (DEG) 1 1.000E+03 1.435E-01 1.000E+00 -1.585E+02 0.000E+0O 2 2.0O0E+03 1.327E-05 9.252E-05 -1.266E+02 1.904E+02 3 3.000E+03 2.902E-03 2.023E-02 9.671 E+01 5.723E+02 4 4.000E+03 5.810E-06 4.050E-05 -8.770E+01 5.464E+02 5 5.000E+03 4.695E-03 3.273E-02 1.289E+02 9.216E+02 6 6.0O0E+03 5.248E-06 3.658E-05 1.499E+02 1.101E+03 7 7.000E+03 1.368E-03 9.538E-03 -2.745E+01 1.082E+03 8 8.000E+03 4.318E-06 3.010E-05 -6.585E+01 1.202E+03 9 9.000E+03 1.799E-03 1.254E-02 1.437E+02 1.571E+03 Table 9.2 Fourier Components of the Input Current of the Simulated Buck Con- verterwithZ. = lOmH and C = 100 u.F **** FOURIER ANALYSIS FOURIER COMPONENTS OF TRANSIENT RESPONSE /(LO) DC COMPONENT = 1.000200E+00 HARMONK 3 FREQUENCY FOURIER NORMALIZED PHASE NORMALIZED NO. (HZ) COMPONENT COMPONENT (DEG) PHASE (DEG) 1 1.000E+03 1.034E-01 1.000E+00 -8.972E+01 0.0OOE+OO 2 2.000E+03 1.559E-05 1.508E-04 -1.986E+01 1.596E+02 3 3.0O0E+03 1.154E-02 1.116E-01 -9.151 E+01 1.776E+02 4 4.000E+03 5.996E-06 5.798E-05 -2.582E+01 3.331 E+02 5 5.000E+03 4.179E-03 4.041 E-02 -9.160E+01 3.570E+02 6 6.000E+03 3.884E-06 3.755E-05 -1.957E+01 5.187E+02 7 7.000E+03 2.101E-03 2.032E-02 -9.289E+01 5.351 E+02 8 8.000E+03 3.625E-06 3.506E-05 -2.004E+01 6.977E+02 9 9.000E+03 1.300E-03 1.257E-02 -9.085E+01 7.166E+02 9.3.2 Buck Converter with an Ideal Switch An ideal switch is often used to model the switching transistor in the initial simulation of a switching converter. The use of ideal switch can reduce the frequent convergence problems, which occur in PSpice due to discontinuities in the device equations of the switching transistors. It can also eliminate - : m 382 Power-Switching Converters Table 9.3 Fourier Components of the Output Voltage of the Simulated Buck Converter with L = 50 mH and C = 500 jiF FOURIER ANALYSIS FOURIER COMPONENTS OF TRANSIENT RESPONSE W[2) •• ****** ********** A>1 DC COMPONENT = 5.001000E+00 HARMONIC FREQUENCY FOURIER NO. (HZ) NORMALIZED COMPONENT COMPONENT PHASE NORMALIZED (DEG) PHASE (DEG) 1 1.000E+O3 5.763E-03 1.000E+00 -1.714E+02 0.O0OE+00 2 2.000E+03 6.290E-07 1.091E-04 -1.641E+02 1.787E+02 3 3.000E+03 2.280E-04 3.955E-02 6.387E+01 5.780E+02 4 4.000E+03 1.681E-07 2.917E-05 -3.370E+01 6.518E+02 5 5.000E+03 2.217E-04 3.847E-02 1.228E+02 9.797E+02 6 6.000E+03 2.839E-07 4.927E-05 1.272E+02 1.155E+03 7 7.000E+03 7.123E-05 1.236E-02 -1.278E+01 1.187E+03 8 8.000E+03 1.692E-07 2.935E-05 -3.977E+01 1.331E+03 9 9.000E+03 7.993E-05 1.387E-02 1.354E+02 1.678E+03 Table 9.4 Fourier Components of the Input Current of the Simulated Buck Converter with L = 50 mH and C = 500 pF **** FOURIER ANALYSIS ********************* A*****************************************' FOURIER COMPONENTS OF TRANSIENT RESPONSE /(LO) DC COMPONENT = 1.000200E+00 HARMONIC FREQUENCY FOURIER NORMALIZED NO. (HZ) COMPONENT COMPONENT ■ ***************************** PHASE NORMAUZED (DEG) PHASE (DEG) 1 1.000E+03 2.032E-02 1.000E+00 -9.006E+01 0.000E+00 2 2.000E+03 3.053E-06 1.502E-04 -1.984E+01 1.603E+02 3 3.000E+03 2.282E-03 1.123E-01 -9.071 E+01 1.795E+02 4 4.000E+03 1.204E-06 5.922E-05 -2.555E+01 3.347E+02 5 5.000E+03 8.251 E-04 4.060E-02 -9.183E+01 3.585E+02 6 6.000E+03 7.589E-07 3.734E-05 -1.917E+01 5.212E+02 7 7.000E+03 4.1 81 E-04 2.057E-02 -9.226E+01 5.381 E+02 8 8.000E+03 7.256E-07 3.570E-05 -1.999E+01 7.005E+02 9 9.000E+03 2.565E-04 1.262E-02 -9.109E+01 7.194E+02 problems introduced by the driver circuitry. There are two types of ideal switches in PSpice: voltage-controlled switch and current-controlled switch. Figure 9.8 shows the circuit symbol for a voltage-controlled switch. The designation for the voltage-controlled switch PSpice is S. The general statement for this type of switch is Simulation of Switching Converters 383 A£°- Ato- N* \ A N- Figure 9.8 Symbol of a voltage-controlled switch. s<name> n+ n- nc+ nc— sname .MODEL SNAME VSWITCH (RON = 0.01 ROFF = 1 E + 7 VON = 0.7 VOFF = 0) where N+ and N- are the two nodes of the switch. nc+ and nc- are the positive and negative nodes of the controlling voltage source, respectively. The current is assumed to flow from the N+ node through the switch to the N- node. The on-resistance of the switch is 0.01 O when the voltage across the switch is equal to or greater than 0.7 V. The off-resistance is 1 MO when the voltage across the switch is V. A rather complex relationship exits between the controlling voltage and the resistance when the controlling voltage is between and 0.7 V. In this voltage range, the resistance is a function of the voltage. The off-resistance, ROFF, should be less than 1/gmin [1] or 10 ,2 n, since the default value of GMIN is 10~ 12 S. The on-resistance, ron, should be greater than zero. Thus, the ratio of roff to RON should be less than 10 12 . Figure 9.9 shows the circuit symbol for a current-controlled switch. The PSpice designation for a current-controlled switch is W. The general statement for this type of switch is w<name> n+ n— vn wname .MODEL WNAME ISWITCH (RON = 0.01 ROFF = IE + 7 ION = 0.1 |OFF = 0) where N+ and N- are the two nodes of the switch, vn is an independent voltage source from which the controlling current flows. The on-resistance of the switch is 0.01 SI when a current of 0.1 A or greater flows through the controlling source VN. The off-resistance is equal to 10 Mfl when the 384 Power-Switching Converters W Figure 9.9 Symbol of a current-controlled switch. controlling current is zero and the switch is open. In the simulation of a switching converter using an ideal switch, an infinitely high off-resistance or zero on-state resistance often results in convergence problems during tran- sient analysis due to infinitely large current or voltage associated with storage elements. Therefore, the off-state or on-state resistance of an ideal switch should be limited to practically acceptable values. Figure 9.10 shows the circuit schematic of an open-loop buck converter with an ideal voltage- controlled switch replacing the switching transistor. Assuming a switching frequency of 1 kHz and a steady-state duty cycle, D of 50%, the program listing for the ideal buck converter is given below: OPEN-LOOP BUCK CONVERTER WTTH AN IDEAL SWITCH * SWITCHING FREQUENCY = 1 KHZ; DUTY CYCLE = 50% VS QlOV :RSX VPWM Figure 9.10 Circuit schematic of an open-loop buck converter with a voltage- controlled switch replacing the switching transistor. Simulation of Switching Converters 385 VS 1 10.0 VPWM 100 101 PULSE(0 1 1us 1us 500us 1ms) S1 1 2 100 101 sx RSX100 10G DFW 2 D1 lO 2 3 10m CO 3 100u RL305 .MODEL SX VSVOTTCH (RON = 0.01 ROFF = 1 E+7 VON = 1 VOFF = 0) :modeld1 D -TRAN 0.05MS 20MS .PROBE .END The resistor rsx is necessary to satisfy the PSpice requirement of having at least two circuit elements connected to a node. Its 10-GO resistance is essentially an open circuit. Figure 9.11 shows the output voltage, the inductor current, and the capacitor current waveforms of the simulated buck converter. These wave- forms are similar to those shown in Figure 9.2. Figure 9.12 shows the steady- state waveform for the current flowing through and the voltage across the output capacitor. In this case, the capacitor ripple voltage lags the current ripple by 90°. In some simulations, it is desirable to define the initial conditions of the switching converter. This is essentially true for switching converters with a large output capacitance and a large output inductance. Otherwise, it may 0s 5ms . V13) • /(LO) • «CO) 10 ms Time Figure 9.1 1 Output voltage (K(3)), inductor current (/(LO)), and capacitor cur- rent (/(CO)) waveforms of the simulated buck converter with an ideal switch. Power-Switching Converters -3.0 15.0 15.5 . V|3) • 20- /(CO) 16.0 165 17.0 Time (msec) 17.5 18.0 Figure 9.12 Steady-state waveforms of the current flowing through the output capacitor (/(CO)) and the voltage across the output capacitor ( V(5)) of the simulated buck converter with an ideal switch. take a considerable long execution time to perform a steady-state analysis on these switching converters. Performing transient analysis with initial condi- tions can be accomplished by inserting the initial conditions at the end of the statements and modifying the tran statement as follows: L0 2 3 100U1C = 1 CO 3 IC = 5 .TRAN 2NS 200NS UIC The initial inductor current is 1 A, while the initial voltage across the output capacitor CO is 5 V. PSpice does not calculate the transient analysis bias point before the beginning of the transient analysis if the uic is inserted at the end of the tran statement, as done here. Figure 9.13 shows the output voltage, inductor current, and capacitor currents waveforms of the simu- lated buck converter using initial conditions. With the initial energy stored in the output capacitor, the average current-time product of the output cap- acitor over a switching cycle for the entire simulation is zero. The output voltage overshoots initially, but reaches its steady-state value in about 4 ms or four switching cycles. It should be noted that the time it takes for the converter to achieve a steady-state voltage of 5 V is less than the previous case without the use of initial conditions. 9.4 PSPICE SIMULATIONS USING SCHEMATICS ENTRY The graphicjnput interface for the latest versions of PSpice (Capture in OrCad) permits rapid input, interpreting, documenting, and debugging of Simulation of Switching Converters 387 Os 5 ms • W[3) ./(LO)W(CO) 10 ms Time 15 ms 20 ms Figure 9.13 Output voltage (V{3)), inductor current (/(LO)), and capacitor cur- rent (/(CO)) of the simulated buck converter with an ideal switch using initial conditions. PSpice input files. We encourage the use of the graphic input interface instead of the text input file. An example of schematic entry follows. 9.4.1 Boost Converter The PSpice schematic of a boost converter with a voltage-controlled switch replacing the switching transistor is shown in Figure 9.14. The switching frequency is set to 1 kHz by PER = 1 ms, the duty cycle is 50%, since the PW is set to 0.5 ms. Figure 9.15 shows the output voltage of the simulated boost converter. As can be seen, the response is underdamped and reaches its steady-state + ^-10Vh, - 10 mH pwm V, = V 2 =1 TD = TR = 1n TF = 1n PW = 0.5m PER = 1 m @V 2 ~*t" VOFF = 0.0V VON = 1.0 V ROFF = 1eB RON = 1.0 20O Figure 9.14 Circuit schematic of a boost converter with a voltage-controlled switch replacing the switching transistor. Power-Switching Converters 10V s 5 ms - V(out) 10 ms 15 ms Time 20 ms 25 ms 30 ms Figure 9.15 Output voltage waveform of the simulated boost converter. voltage of 16 V in about 15 ms or 15 switching cycles. The simulated output ripple voltage is 4.7 V, in good agreement with the theoretical value: 0.5 Vc Cf s (100 x 10- 6 )1000 5V. (9.3) Figure 9.16 shows the input inductor current and output capacitor current waveforms of the simulated boost converter. The input inductor cur- rent is underdamped with a ripple current of 0.5 A. The theoretical value is given by A7 = VJ) 10(0.5) Lf s (10 x 1 0- 3 )1000 = 0.5 A. (9.4) 9.4.2 PSpice Simulations Using Behavioral Modeling Analog behavioral modeling is a time-saving tool that can be used to design systems at an abstract level to test if the concepts are correct, before proceeding with the detailed circuit-level design. In PSpice, the ABM.OLB part library contains the ABM components. This library contains two sections. The first section includes parts that can be used to represent control-system-type of circuits. Some of these components are: sum, gain, laplace, and hipass. The second section contains controlled-source parts, like evalue and gfreq that are based on extensions to traditional PSpice E and G device types. A detailed description of these components can be found in PSpice User's Guide [2]. Simulation of Switching Converters 389 3.0 A 2-0 A - 1.0A 0A -1.0 A -2.0 A Os 5 ms - /(/.,) * /(C,) Figure 9.16 Input inductor current and output capacitor current waveforms of the simulated boost converter. 9.4.2. 1 Control System Parts Control system parts have one input and one output. The reference for the input and output voltages is the analog ground (node 0). These compon- ents can be connected together with no need for dummy loads or input resistors. Table 9.5 lists the control system parts, grouped by function. The fourth column displays the characteristic properties that differentiate each specific application. 9.4.2.2 PSpice-Equivalent Parts PSpice-equivalent parts have a differential input and a double-ended output. They can be classified as either E or G device types. The E part type yields a voltage output, while the G device type yields a current output. Their transfer functions can contain any combination of voltages and currents as inputs. Hence, there is no division between voltage-controlled and current- controlled parts. Instead, the part type is defined merely by the output requirements. If a voltage output is required, use an E part type. If a current output is needed, use a G part type. Table 9.6 summarizes the PSpice- equivalent parts available in the ABM part library. Logical and arithmetic operators, as well as math functions, can be used in the expression field of all ABM parts. Table 9.7 and Table 9.8 summarize the operators and functions available in PSpice. IP 390 Table 9.5 Control System Parts [2] Power-Switching Converters Category Part Description Properties Icon Basic CONST components SUM MULT VALUE Limiters Chebyshev filters GAIN D1FF LIMIT GL1MIT GAIN Constant Adder Multiplier Gain block Subtraction Hard limiter LO, HI Limiter with LO, HI, GAIN gain 1.000[-D o-^(x)-a tJlK>-a a-o&^Y-a H3F JO 1 SOFTLIM Soft (tanh) limiter LO, HI, GAIN :°ji LOPASS HlPASS Low pass filter High pass filter FP, FS, RIPPLE, o- STOP Orr 100Hz r\, iohz 1dB 50dB BANDPASS Band pass filter FP, FS, RIPPLE, STOP F0, Fl, F2, F3, i RIPPLE, STOP f\, 100Hz Otr iohz 1dB 50dB idBsndBlOHz| BANDREJ Band reject F0, Fl, F2, F3, i (notch) filter RIPPLE, STOP w C& 100Hz IdBROriBlOHz Integrator and INTEG differentiator Integrator GAIN, IC 4E^" Simulation of Switching Converters Table 9.5 Control System Parts — Continued 391 Category Part Description Properties Icon DIFFER Differentiator GAIN d/dt 1.0 Table look-ups TABLE Lookup table ROW1... ROWS p- ItableL q In Out Ov Ov 2v gv 4v 16v o- FTABLE -o Freq dB deg FTABLE LAPLACE ABS SQRT PWR PWRS LOG LOG10 EXP SIN COS TAN ATAN frequency lookup table Laplace expression M W EXP ln(x) log(x) e* sin(x) cos(jc) tan(jc) Tan-'(Jc) ROW1... ROWS NUM, DENOM EXP EXP OHz 10Hz -3 20Hz -6 30Hz -10 40Hz -15 -3 -90 -120 -150 1 Laplace transform 1 +S H -a Math functions V is the input ABS \ o- SQRT -a D- PWR 1.0 -a n- PWRS 1.0 -a D- LOG -a D- LOG 10 -a D- EXP -a D- D- \ SIN -o \ COS -0 D- - TAN -D P- -j ATAN |-o (Q mlinues) 392 Power-Switching Converters Table 9.5 Control System Parts — Continued Category Part Description Properties Icon ARCTAN Tan _, (x) Expression ABM functions ABM1 ABM2 ABM 3 No inputs, Vout 1 Input, V out 2 Inputs, Vout 3 Inputs, V out EXP1 • --EXP4 EXP1 - EXP4 EXP1 EXP4 O-JAi iRCTAN -n 3.14159265 (v(%IN)* 100)/ 1000 (v(%IN1)+ 2| v(%IN2))/ 2.0 (v(%IN1) + EXP1 • • • EXP4 ~ V (%IN2) ) / Er 1 o n 2.0 3 -a ABM/I No input, lout EXP1 - EXP4 1.4142136 c ABM1/I 1 Input, I out ABM2/I 2 Inputs, I out ABM3/I 3 Inputs, I out EXP1 - - - EXP4 o- + EXP1 • • EXP4 EXP1 - -EXP4 (v)%IN) 100)/ ® innn "° 1000 lV)%IN1) + ,_-*i V(%IN2)) A$» (V)%IN1) + V(%1N2) + v(%IN3))/3. i- 9.4.3 Examples of ABM Blocks Use We included a selection of simple examples that the reader may find handy when designing switching converter simulations, such as parameter defin- ition, triangular waveform generator, PWM modulator, and a VCO for the control of resonant converters. PARAM is a component in the Special library, which can be used to define global parameters that can be accessed from ABM blocks. In Figure 9.17, two parameters are defined: PI and freq. Both parameters are used in the ABM block to implement a sine wave generator of frequency freq. time is an internal global parameter that keeps track of the simulation time. Simulation of Switching Converters Table 9.6 PSpice-Equivalent Parts 393 Category Part Description Properties Icon Mathematical EVALUE General purpose EXPR expression GVALUE ESUM GSUM EMULT GMULT Special purpose (None) E1 IN+ OUT-tfa IN- OUT- EVALUE V(%IN+. %IN-) 61 IN+ OUT-bg -*» IN- OUTV* -a GVALUE V(%IN+, %IN-) E2 IN1+ IN1-OUT-tf-o ESUM IN2+OUT- IN2- G2 GSUM® E3 IN1 + IN1-OUT4J-a EMULT IN2+OUT- IN2- Table look-up ETABLE General purpose EXPR GTABLE TABLE i E4 IN+ OUT+-Q IN- OUT- -° ETABLE V(%IN+, %IN-) G4 IN+ OUT-bg -° IN- OUT-^-n GLAPLACE V(%IN+, %IN-) (Continues) 394 Power-Switching Converters Table 9.6 PSpice-Equivalent Parts — Continued Category Part Description Properties Icon Frequency table EFREQ look-up GFREQ General purpose EXPR E5 in+ our4o IN- OUT- EFREQ V(%IN+,%IN-) G5 TABLE in+out in- our- GFREQ V(%IN+.%1N-) E6 Laplace transform ELAPLACE General purpose EXPR a-IN+ OUT p-IN- OUT- ELAPLACE V(%IN+,%IN-) G4 GLAPLACE XFORM IN+OUT IN- OUT- GLAPLACE V(%IN+.%IN-) Table 9.7 Operators in ABM Expressions Operator class Operators Description Arithmetic Logical 3 Relational 3 / & > > < Addition or string concatenation Subtraction Multiplication Division Exponentiation Unary NOT Boolean OR Boolean XOR Boolean AND Equality test Nonequality test Greater than test Greater than or equal to test Less than test Less than or equal to test "Logical and relational operators are used within the-lF() function. Simulation of Switching Converters 395 Table 9.8 Functions in Arithmetic Expressions Function Description ABS(x) SQRT(x) EXP(x) LOG(x) LOG,o« PWRCxjO PWRS(x,x) SIN(x) ASlN(x) SlNH(x) COS(x) ACOS(x) COSH(x) TAN(x) ATAN(x) = ARCTAN(x) ATAN2(y,x) TANH(x) MW PW RW IMG(x) DDT(x) SDT(x) TABLE(x, x u y u --) MlN(x,x) MAX(xj) LI M IT(x,min,max) SGN(x) STP(x) IF(r,xjO M x ,/2 ln(x) which is log base e Log(x) which is log base 10 w +IXP - (if x > 0); -|x|- v (if .x < 0) sin(x), where x is in radians sin~'(x), where the result is in radians sinh(x), where x is in radians cos(x), where x is in radians cos _1 (x), where the result is in radians cosh(x), where x is in radians tan(x), where x is in radians tan _, (x), where the result is in radians tan _I (y/x), where the result is in radians tanh(x), where x is in radians Magnitude of x a which is the same as ABS(x) Phase of x" in degrees; returns 0.0 for real numbers Real part of x a Imaginary part of x a which is applicable to AC analysis only Time derivative of x which is applicable to transient analysis only Time integral of x which is applicable to transient analysis only y Value as a function of where x n , y n point pairs are plotted and connected by straight lines Minimum of x and y Maximum of x and y min if x < min; max if x > max else x +1 if x > 0; if x = 0; -1 if x < 1 if x > 0; otherwise which is used to suppress a value until a given amount of time has passed x if t is true y otherwise where l is a relational expression using the relational operators shown in Table 9 a M(.x), P(x), R(.x), and IMG(x) apply to Laplace expressions only. The node voltages can be accessed from any ABM block; this is the case of the output voltage of the previous example, which is multiplied by 3 to produce the control output, as shown in Figure 9.18. An ABM1 block has one input, 396 Power-Switching Converters PARAMETERS: PI = 3.141592654 freq= 1fc 3*sin (2*PI*freq*TIME) sine Figure 9.17 ABM and PARAM. 3-V (sine) control J Figure 9.18 Node voltages can be accessed from ABM blocks. If (TIME<=0,0,SQRT(SDT(PWR(V(%IN),2))/riME)) Figure 9.19 RMS meter. F(%IN), and one output. A true rms meter can be implemented using the PARAM, as shown in Figure 9.19. The input voltage is squared, then inte- grated and divided by the elapsed time, and finally the square root is calculated. The if statement is used to avoid the division by zero at time = 0. The syntax for an if then statement is as follows: IF(ARGUMENT,THEN,ELSE) The argument, then, and else statements can contain references to node voltages, currents through voltage sources, arithmetic symbols, logical sym- bols, and relational symbols. For example, if (time<0, 0, SQRt(sdt(pwr(v(%in),2))/time)) At time = the output is set to 0; otherwise the rms expression is evaluated. Another example of the use of the if statement is if (v(in)>3,12,v(in)*4) This statement evaluates if the input voltage is greater than 3 V; in that case, the output signal saturates to 12 V. Otherwise, the input signal is amplified by 4. This can be used to simulate a linear amplifier with a 12-V power supply. Simulation of Switching Converters 397 A PWM modulator can be easily implemented with ABM blocks, as shown in Figure 9.20. V 4 is a vpulse source whose parameters are set to simulate a triangular waveform generator. An ABM2 block is used in this case. It has two inputs, v(%in1) and v(%in2). The if statement programmed into this block is an ideal comparator; if the control signal is greater than the triangular signal, then the PWM output is 1; otherwise is 0. A common error message obtained while using ABMx parts is "part not annotated." Somehow, Capture does not automatically assign a part reference to these components and the error message is generated. Remem- ber to manually assign a part reference; e.g., ABM2a. An implementation of a VCO is illustrated in Figure 9.21, where a sine wave generator is modeled with an ABM 1 block. The frequency is proportional to the input voltage; thus, changing v(%in) changes the VCO output frequency. 9.4.4 PSpice Simulations Using Control Blocks A model of a PWM modulator using control blocks is shown in Figure 9.22. A DIFF part is used to subtract the control and the triangular signals. The result of this operation is passed through a high-gain GLIMIT that acts as a comparator. The PWM output is either at or 10 V. Figure 9.23 represents a simplified model for an operational amplifier. The finite input impedance is modeled by R t and R 2 . The DIFF component subtracts the signal at the inverting input pin, In-, from the signal at the noninverting input pin, In+. The large open-loop gain of the operational If (V(%IN1) > V(%IN2),1,0) control triangular <■ 1 | V, = -10 I V 2 = 10 JL TD = Qyv A TR = 1u TF=1u * PW=1n PER = 2u ~0 Jpwm Figure 9.20 PWM modulator. Sin (2*PI*100k*ABS(V(%IN)) * TIME) triangular VCO Figure 9.21 VCO implementation with ABM1. ^p 398 Power-Switching Converters control V 2 = 10 TD = TR = 0.5 mVy TF = 0.5 m PW=1n PER = 1m^ pwm Figure 9.22 PWM modulator with control blocks. < JOpAmp Figure 9.23 Model of an operational amplifier. amplifier (i.e., 100 k) is represented by a GAIN block. The Laplace block models the open-loop frequency response, including only the low frequency pole. The LIMIT block limits the output voltage swing to the values set by the PARAMETERS V cc and F EE , emulating the saturation of the amplifier due to the output voltage swing reaching the power supply limits. The open-loop frequency response for the operational amplifier is shown in Figure 9.24. Simulation of Switching Converters 399 00 50- 0- . DB(V(OPAMP)) -50d -100d 1.0mHz10mHz . P(V(OPAMP)) 100 MHz Figure 9.24 Open-loop frequency response. A closed-loop amplifier with a gain of 1 1 V/V implemented with the above operational amplifier is shown in Figure 9.25 with its frequency response shown in Figure 9.26. Notice how the gain decreases while the bandwidth increases in the same proportion (i.e., (1 + &A)), according to feedback theory [3]. 9.4.4. 1 Voltage-Mode PWM Boost Converter The same boost converter of Figure 9. 14 is simulated in Figure 9.27 with a closed-loop control to obtain a regulated output voltage of 20 V and a critically damped transient response. Recall from Figure 9.15 that the output voltage of the open-loop converter settles to 1 7 V at 1 5 ms, after overshooting up to 22 V. The components of the feedback loop are modeled with ABM parts to speed up the design process. The voltage-controlled voltage-source EX is used to sample the output voltage. The sensed voltage, F(sense) = F(out)*0.25; where 0.25 is the voltage gain of EX. This part can be physically replaced by a resistive voltage divider using the same ratio. The dashed box delimits the model for the error amplifier. The subtraction is followed by the gain block, representing the closed-loop gain of the error amplifier. The Laplace part models the closed-loop frequency response and the limiter represents the saturation of the supply voltage. The inputs to the error 400 Power-Switching Converters 1 v. ov, < |OpAmp Figure 9.25 Closed-loop amplifier. amplifier are the reference and the sensed voltages. As such, the error signal is then proportional to the difference of these two voltages. The PWM modu- lator is implemented using an ABM2 part, as discussed above. The inputs to the modulator are the control and the sawtooth signals. The sawtooth is generated using vpulse, V4. The control signal is the result of adding the error voltage to the reference voltage. The use of the adder at that point is very convenient, since it enables the closed-loop response to be evaluated without modifying the circuit. The open-loop response can be evaluated by discon- necting the output of the error amplifier from the adder and grounding the unconnected adder input. In this case, the reference voltage can still be connected to the modulator with the switching converter in an open-loop configuration. It should be noted that the error signal still reflects the differ- ence between the open-loop output voltage and the reference voltage. Figure 9.28 shows the control, error, and output voltages for the closed-loop boost converter, together with their respective average values. Simulation of Switching Converters 401 50- "Sn. ■ DB(V(OPAMP)) 0d- EL» I.OmHz 10mHz • P(V(OPAMP)) Frequency Figure 9.26 Closed-loop frequency response. 10mH pwm v,imv 1 7ES -w— VOFF=0.0V VON=1.0V ROFF=1e6 RON = 0.05 100(iF GAIN = 0.25 II (ITX JN1) > V(%IN 2),1.0) control pvvm„oiit PWM modulator vr v, = o V 2 = 10 I TD=0 OV TR = 999uT TF = 1n _L PW = 1n — PER=1 m L© 1Meg IMeg+s -<^-<> Error amplifier ■S Figure 9.27 Closed-loop boost converter. The error amplifier gain has been adjusted to give a critically damped transi- ent response. Notice how the output voltage settles to its final value of 20 "V in less than 4 ms and without overshooting. At the same time, the error ap- proaches zero and the control voltage approaches 5 V (i.e.; 20 K/gain(isi)). 402 Power-Switching Converters Vleontrol) o Vleontrol) • AVG (V(conlrol)) 20 V Figure 9.28 Voltage waveforms of the closed-loop boost converter. 9.4.5 PSpice Simulations Using Vendor Models The last step before building a prototype is to simulate the circuit using the vendor models for the circuit components. In this simulation, it is recom- mended to include realistic circuit and element parasitics. .model statements should not be used to model the effect of package parasitics. This is because these .model statements cannot be used to model the transient response-of most power semiconductor devices due to the extreme nonlinear character- istics of these power devices. Therefore, model statement is seldom used in the transient analysis of switching devices. Instead, a SUBCIRCUIT repre- sentation for power MOSFET should be used in transient analysis. Example 9.1. Continuing with the design of the boost converter of Figure 9.27, the ABM parts were replaced by vendor models. The inductor and capacitor parasitics are included, resulting in the circuit shown in Figure 9.29. The initial current flowing through the inductor -L\ is set to zero; otherwise, the simulation may yield an erroneous answer. The simulation options listed below can be used to improve convergence. .tran 30 m 0.1 u .OPTIONS STEPGMIN -OPTIONS ABSTOL = 10p Simulation of Switching Converters 403 10 V* -wv- 10 mH IC=0 -vw- -*l£ 100 MTP15N05E/MC =F C - 20 300k pwm„out control -W* P. 1* CD Error amplifier PWM modulator Figure 9.29 Closed-loop boost converter with vendor models. .OPTIONS m_1 =400 .options m_4 = 500 .OPTIONS RELTOL = 0.01 .OPTIONS vntol = 1 Ou Figure 9.30 shows the inductor current, control voltage, and output voltage waveforms of the simulated converter. I(Li) starts from due to the initial current of IC = 0. The control voltage settles to an average value slightly larger than 5 V to offset the losses due to nonideal circuit components. It is important to avoid saturation of the control signal in order to be able to control the converter at all time. The steady-state average output voltage of the boost converter is smaller than 20 V. A PI controller should be used to achieve a zero steady-state error of its output voltage. Nevertheless, F(out) settles to its final value with almost no overshoot. This simulation requires twice the simulation time compared to the simulation using ABM parts; also, the output data files are much larger. 9.5 SMALL-SIGNAL ANALYSIS OF SWITCHING CONVERTERS As discussed in Chapter 6, many linear small-signal models for switching converters have been developed. Oread PSpice includes a library with linear components based on the Vorperian model [4]. The components of this library, named SWITJRAV.LIB, are listed in Table 9.9, 404 Power-Switching Converters 4.0 A 2.0 A 0A 5.2 V 5.0 V 4.8 V V(conlrol) Os 5ms . V(oul) 25 ms 30 ms Figure 9.30 Waveforms of the simulated closed-loop converter. Table 9.9 Vorperian models for PSpice [2] SWIT_RAV.LIB components Component Description CMLSCCM CMSSCCM QRLSZCS Current-mode large-signal continuous_eonduction mode Current-mode small-signal continuous conduction mode Quasi-resonant large-signal zero-current-switching Parameters Se: External ramp slope (vis) FS: Operating frequency Lfil: Filter inductance Ri: Current feedback coefficient Se: External ramp slope (vis) Sn: Current semse ramp slope (vis) FS: Operating frequency D: Duty cycle Lfil: Filter inductance Ic: Current from terminal C Vap: Voltage across terminals a and p Ri: Current feedback coefficient VCOCOEFF: Coefficient for voltage to frequency conversion Fsoffset: Frequency from Vco at zero Vc Simulation of Switching Converters 405 Table 9.9 Vorperian models for PSpice [2]— Continued SWIT_RAV.LIB components Component Description VMCCMDCM VMLSCCM VMLSDCM VMSSCCM Voltage-mode continuous- conduction-mode and discontinuous-conduction- mode Voltage-mode large-signal continuous-conduction-mode Voltage-mode large-signal discontinuous-conduction- mode Voltage-mode large-signal continuous-conduction-mode Parameters Lo: Resonant filter value Co: Resonant capacitor value N: full wave N = 2; half wave N = 1 RMPH1TE: External ramp height VALLEYV: Valley voltage of ex- ternal ramp LFIL: Filter inductance FS: Operating frequency START: Setup time necessary for the model to set itself up RMPHITE: External ramp height VALLEYV: Valley voltage of external ramp RMPHITE: External ramp height VALLEYV: Valley voltage of external ramp LFIL: Filter inductance FS: Operating frequency RMPHITE: External ramp height D: Duty cycle Ic: Current flowing from terminal C Vap: Voltage across terminals a and b Rsw: Switch on resistance Rd: Diode on resistance Rm: Models the base storage effects Re: Capacitor ESR The PSpice model for the voltage-mode small-signal continuous-con- duction-mode (VMSSCCM) part is listed below. The parameters match with those in the model published by Vorperian [4]; a description is also found in Chapter 6. These parameters have to be specifically set for each circuit. Note that the default ramp height is 2 V. 406 Power-Switching Converters ""vmssccm * Small signal continuous conduction voltage mode model * Params: rmphite — * External ramp height * D — » Duty cycle * Ic -* Current flowing from terminal C See diagrams: but for buck it is VJr, for boost it is lin * Vap — ► Voltage across terminal A P See diagrams: but for buck it is Vin * Rsw — ► Switch on resistance * Rd — » diode on resistance * Rm — » which models the base storage effects * Re -* models ripple across ESR of cap * Pins control voltage * common 1 * passive | | * ACTIVE - | | | MM . subckt vmssccm a p c vc Params: RMPHrre = 2 D = 0.4 IC = 1 VAP = 20 + Rsw=1E-6 Rd = 1E-6 Re = 1E-6 Rm = 1E-6 efm 4 value = {v(Vc)/rmphite} e2 A 6 value = {v(0,4)*Vap/d} g1 APvalue = {v(4)*IC} gxfr 6 p value = {l(vms)*D} exfr 9 p value = {V(6,P)*D} vms 9 8 rd 8 C {d*rd+(1-d)*rsw+d*(1-d)*re+rm} rope 4 1g rgnd P 1g .ends A small-signal model for the boost converter of Figure 9.14, including circuit losses is shown in Figure 9.31. A small-signal AC analysis will be performed to study the frequency dependence of the averaged parameters with respect to small-signal changes in the duty cycle, d. In this figure, notice how the voltage-mode small-signal continuous-conduction-mode (VMSSCCM) component is connected. The common terminal (Q is con- nected to the common point where the switch and the diode are connected; the active terminal (A) is connected to the other end of the switch; the passive terminal (P) is connected to the other terminal of the diode; and the Simulation of Switching Converters 407 10 v^-s- a t, U7 out '300* = v, 1 w ra IC=0 1 O A P O > 2 -n D = 0.5 IOOuF 3 IC = " - "-, * 10m :fl -20 IC=-1.84 J RMPHITE = 10 = RD = 1e-6 sense RE = 10m : 1v „«>li/ RSW=10m OV^W' 4 VAP = -17.6 "100k Figure 9.31 Small-signal AC analysis. control terminal (VC) is connected to the duty cycle generator. The param- eters of the VMSSCCM part are found from the average values of the parameters in Figure 9.14 as follows: D = 0.5 is the average duty cycle IC = -1.84 A is the average current flowing out of the common terminal, in this circuit is equal to — / L , RD = le-6 is the dynamic resistance of the diode RE = 10 m is the capacitor's ESR RM = le-6 models the base storage effects RMPHITE = 10 sets a ramp of 10 V, this parameter is used for the small-signal gain RSW = 10 m is the switch on resistance V ap = -17.6 V is the average voltage between terminals (A) and (P); for this circuit is equal to — K out . The average current flowing through the inductor, I Li , and the average output voltage, K om , are plotted in Figure 9.32. These waveforms follow the average trend of the waveform shown in Figure 9.15, without the switching ripple. It should be noted that this model accurately predicts the DC com- ponent, as well as the small-signal AC components up to half the switching frequency. 9.5.1 Open-Loop Transfer Function Figure 9.33 shows the bode plot of the output-to-control transfer function for the boost switching converter. It represents the frequency dependence of the output voltage to small-signal variations in the duty cycle. It can be observed that these Bode plots correspond to an underdamped second- order system with a right-half-plane (RHP) zero. According to the equa- tions listed in Table 6.3, the complex- conjug ate poles due to the output filter are located at / = (1 - D)/2tt ^LC^t = 25 Hz; the left-half-plane Power-Switching Converters HOUT) Figure 9.32 Small-signal analysis average waveforms. 40- SEL» ■ DB(V(OUT)) 1.0 Hz 10 Hz . pmouD) 100 KHz 1.0 MHz Figure 9.33 Output-to-control frequency response. zero due to the output capacitor's ESR is located at / ZESR = l/2irR esr C ut= 159 kHz and the RHP zero is located at /zrhp = (1 - DfR\ *d/2irL = 79.6Hz. The zero due to the ESR is located Simulation of Switching Converters 409 at a very high frequency (more than 10 times the switching frequency), thus it produces no influence on the frequency response for frequencies below fj 2. The RHP zero is located at low frequency, close to the corner frequency of the output filter. Due to the combined effect of the two poles and the RHP zero, the magnitude rolls down with a -20 dB/dec slope and the phase reaches —270° above 1 kHz. 9.5.2 Input Impedance The input impedance can be evaluated by connecting a small-signal AC source in series with the DC voltage source as shown in Figure 9.34. After an AC analysis is performed, the input impedance can be plotted as the ratio of the voltage of the AC source to its current, as shown in Figure 9.35. 9.5.3 Output Impedance To plot the output impedance, an AC source is connected in parallel with the output terminals, as shown in Figure 9.36. After performing an AC analysis, the output impedance can be plotted as the ratio of the voltage of the AC source to its current, as shown in Figure 9.37. As can be seen, the output impedance peaks at the frequency of 100 Hz. 9.5.4 Small-Signal Transient Analysis The average models can also be used to simulate small-signal transient analy- sis. This is useful to predict the behavior of the switching converter due to changes in the circuit parameters, such as duty cycle, input voltage, load current, etc. Figure 9.38 shows the schematic diagram to simulate a step change in the duty cycle at 20 ms. The amplitude of the duty cycle step is IV. Figure 9.39 shows the input inductor current and output voltage waveforms before and after the step change in duty cycle. These waveforms show the average 1 v «(~) v. Figure 9.34 Simulation setup to plot the input impedance. 410 Power-Switching Converters uu- // 20 . 1.0 Hz 10 Hz . DB(M(\/4:+)/l(V4)) 100 Hz 1.0 KHz Frequency 10 KHz 100 KHz 1.0 MH Figure 9.35 Input impedance. n>v^-=- V, Figure 9.36 Simulation setup to plot the output impedance. dynamic response of the switching converter to a step change in the duty cycle. The current waveform instantaneously increases, following the increase in the duty cycle. On the other hand, the voltage waveform shows the typical char- acteristic of a nonminimum-phase system, since the output voltage initially decreases prior to the increase corresponding to a larger duty cycle. Other average models are available for free download from Basso's book [5] at its web page http://perso.wanadoo.fr/cbasso/Spice.htm. One of the models offered in the SMPSRECIPES.LIB is the average model devel- oped by Ridley [6], which models both the voltage and current mode control schemes. Since this model includes the inductor, several components are provided to model the different switching converter topologies. That is the Simulation of Switching Converters 40 411 1.0 Hz 10 Hz = DB<VlV4:+)/l(V4)) 100 KHz 1.0 MHz Figure 9.37 Output impedance. -Wr- 10 mH IC = U7 VMSSCCM > V, = 1.2 V 2 =1.5 TD = 20m TR = 1n TF=1n PW=50m PER = 50 n ^ D=0.5 IC=-1.84 RMPHITE=10 BD=1e-6 RM=1e-6 RE = 10 m RSW=10m VAP = -17.6 100 uF <f? IC = Figure 9.38 Simulation setup for the small-signal transient analysis. case for all the average components based on the averaged-inductor model, such as the BOOSTVM component developed by Yaakov [7], as shown in Figure 9.40. As can be seen, one of the parameters for the component is the inductance, L. The average output voltage waveform obtained using this model is shown in Figure 9.41. 9.5.5 Measuring the Loop Gain The circuit shown in Figure 9.42 is a method for measuring the loop gain. The diode is not necessary because no switching action takes place in the averaged model. However, it may be included, if desired, to add its dynamics 412 Power-Switching Converters 1.0 A 25 ms- 30 ms Figure 9.39 Small-signal transient analysis. |-V\Ar- 1 v.-^i 10 U7 BOOSTVM IN OUT DON GND fls = 1 FS=1fr i.= 10m 10m C, 100u IC = Figure 9.40 Averaged-inductor model for a voltage-mode boost converter. such as diode voltage drop, capacitance, and dynamic resistance to the simulations. To measure the loop gain (i.e. j3 ^4)), we can measure the gain along the path through V x to V ( . 9.5.6 Frequency Compensation For this circuit, we choose /i = 100 Hz for a switching frequency of 1 kHz. The Bode plot of the loop gain reveals that phase compensation is necessary Simulation of Switching Converters 30 V 25 V 20 V- 1SV 413 10V HOUT) Figure 9.41 Output voltage obtained with the averaged-inductor model. - J Wv- 1 10 mH IC = _L U7 o] VMSSCCM > cy, D=0.5 IC = -1.84 RMPHITE = 10 BD = 1e-S RM=1e-6 RE = 10m RSW=10m VAP = -17.6 100 uF< R IC = GAIN =0.25 E,_ V, w~ Figure 9.42 Circuit setup to measure the loop gain. (Figure 9.43). Since the zero due to the ESR of the output capacitor is located at a relatively high frequency beyond/, (100 kHz), a 2-zero 3-pole (PID) compensation network is chosen to achieve the desired phase margin. 9.5.6.1 PID Compensation The phase of the compensation network (2-zero and 3-pole) at /, is given by 0comp(/.) = -9O + 2tan- GD-*-GD (9.5) 414 Power-Switching Converters 90 -904 -ISO -270 SEL» . DB(HV!=)) ,.(100.000.-163.029) I.OmHz lOmHz lOOmHz 1.0Hz 10H2 100Hz 1.0KHZ 10KHZ 100KHZ 1.0MHz 10MH; • »™ VF » Frequency Figure 9.43 Bode plot of the loop gain, and the magnitude is M comp (/,) = -201og I0 (2,r/,) + 401og I0 [yi+(-|) J (9.6) -401og 10 l Wl + From Equation (9.5), f A t /Qcomp + 90 + 2 tan- ' C/i /f p y \ /lz = _ = tan ^ _ y Substituting Equation (9.7) into Equation (9.6), Mcon.pC/",) = -201og 10 (2ir/,) + 40 log l0 \J\ +/? Z J - 4oiog > o (fHF)- (9.7) (9.8) Simulation of Switching Converters 415 Once the location of the double poles and double zeros have been chosen, we can calculate the value of the components of the compensation network: , i , = {c 1 ±£A f ! - 2irR 3 C 3 ,Jpz 2irR 2 C x C 2 ' J " 2irR 2 C i 1 _Ri K _ R 2 (.Ri + *3) M ~ 2ir(R, + R 3 )C 3 ' ' ~ R t ' 2 *i *3 ' ^C- C ' C2 (9-9) 7? 2 C,+C 2 " The following MATLAB program solves Equation (9.8) and calculates the network components according to Equation (9.9). % iteratively solve for pole location on a % 3-pole 2-zeros compensation network clear all PhaseBoost = 32; % needed phase boost at f1 (comp network phase at f1) GainBoost = -7; % needed gain boost at f1 in dB f1 = 100; % defined by designer, has to be <(fs/2) in Hz d2r = pi/180; % degree to radian conversion fpd= 7.5*f1; % initial guess m = 1; % keeps the while going while(m), f 1 z = tan( (PhaseBoost*d2r+90*d2r+2*atan(f1/fpd) )/2); %f1/fz f1z = abs(f1z); fzd=f1/abs(f1z); % Mag_comp_f 1 is the Magnitude of the comp. network at f 1 Mag_comp_f 1 = -20*log1 0(2*pi*f 1 )+20*log1 0(1 +(f 1 zf 2)-20* Iog10 (1 +(f1/fpd)*2) Ph_comp = -90 + 2*atan(f1/fzd)/d2r -2*atan(f1/fpd)/d2r if ( (Mag_comp_f1 -GainBoost) >1) df =2;% frequency resolution fpd=fpd+df; elseif ( (Mag_comp_f 1 -GainBoost) >0.1) df = 0.01; fpd=fpd+df; elseif ( (Mag_comp_f 1 -GainBoost) <- 1 ) df = 2; fpd = fpd-df; 416 Power-Switching Converters elseif ((Mag_comp_f1-GainBoost) <-0.1) df=0.01; fpd = fpd-df; else m=0; % stop the while end end % check phase Ph_comp = -90 + 2*atan(f1/fzd)/d2r - 2*atan(f1/fpd)/d2r, % Claculate k1 and k2 % k1 is the gain of the comp network at fzd k1_db = -20*log10(2*pi*fzd)+20*Iog10(1+(fzd/fzd) A 2)-20*log10 (1 +(fzd/fpd) A 2) k1 =power(10, k1_db/20) % k2 is the gain of the comp network at fpd k2_db = -20*log10(2*pi*fpd) + 20*log10(1 +(fpd/fzd)*2)-20*log10 (1 +(fpd/fpd) A 2) k2= power(10, k2_db/20) % calculate components R1 =10e3; % selected by designer R2=k1*R1 R3=R1/((fpd/fzd)-1) C1=1/(2*pi*R2*fzd) C2 = C1/((fpd/fzd)-1) C3 = 1/(2*pi*R3*fpd) The result of the calculation is: Mag_comp_f1 = -7.0985 Ph_comp = 32 k1_db= -24.6094 k1 =0.0588 k2_db = -5.0259 k2 = 0.5607 R2 = 588.2076 R3 = 269.7258 C1=5.0034e-005 C2=1.3496e-006 C3 = 2.8658e-006 The components of the compensation network may be optimized by per- forming small-signal AC simulations and adjusting their values to obtain the desired phase margin. Once final values of the components of the compen- sation network have been calculated, we are ready to evaluate the transient Simulation of Switching Converters closed-loop response of the switching converter. Due to unmodeled dynam- ics, the phase and gain contributions of the compensation network were changed to obtain a PhaseBoost = 52; GainBoost = -8db; leading to the component values shown in Figure 9.44. The output voltage is shown m Figure 9.45 for a switching frequency / s = 1 kHz. lOV^V, Error amplifier Figure 9-44 Boost switching converter with PID compensator. V^control) 20V v ^^^^^/^JS/s^/^JSJ^^^^J^ l J^J^^iS^^^ fr^^ l^oul) 15ms Time Figure 9.45 Simulation results with a PID compensator. 418 Power-Switching Converters 9.5.6.2 PI Compensation Another compensation frequently used in voltage-mode boost con- verters is the PI compensation. The PI compensator is easier to calculate and requires fewer components, but it leads to smaller bandwidths and slower transient responses. The small-signal model for a PI compensator is shown in Figure 9.46. The transfer function of the compensation network is TF sC t R, + 1 sCiR 2 (9.10) Therefore, it has a pole at s = and a zero at s = - l/Ri C, . The phase of this compensation network starts at -90° due to the pole at the origin and adds positive phase according to the location of the zero. From the Bode plots of Figure 9.47, we measured the frequency at which the uncompensated loop response reaches 90°, i.e., 53 Hz and we set/i at this point, thus f x = 53 Hz. Then we calculated J?, and C x to set the zero at the same frequency. In this way, the phase of the loop gain at/, is: -180° (inversion) -90° (pole at the -*- i _/"vw-\_ 10 mH IC = _T "51 , o A P O U7 VMSSCCM D=0.S IC = -1.84 RMPHtTE=10 RD=1e-6 RM = 1e-6 RE = 10m nsw=iom VAP = -17.6 iC„ 200 uF S- R IC = GAIN = 0.25 E, S^ EAO I |10 10 -WV- 10* 1 — VW- <^p 22 K3 Figure 9.46 Small-signal model of the boost converter with PI compensation. Simulation of Switching Converters 419 SEL» -200 180 90 -90 -180 -270 -360 Compensated loop gain Uncompensated loop gain • DB(V(VF)) - DB(VlEAO)) .Compensated loop gain Uncompensated loop gain LOmHz 10mHz 100mHz 1.0Hz 10Hz 100Hz I.OKHz 10KHZ lOOKHz 1.0MHz . f\WVFJl - F(HEAO)) Frequency Figure 9.47 Bode plots of the uncompensated and compensated loop gains. origin) -90° (loop phase) +45°(zero) = -135°, or a phase margin of 45°. The magnitude of the compensation network at frequencies higher than f\ is given by Ri/R 2 . The magnitude of the uncompensated loop gain at f x j s _ 1.45 dB. Therefore, to force the magnitude of the compensated loop gain to Odb at /,, we set R X IR 2 = 1-45 dB or 1.18 (V/V). Choosing /? 2 = 1 kft, results in i?, = 1 1 .8 kfi and C= 254 nf. These are starting values; the final values are obtained from the simulation results. Figure 9.48 shows the schematic diagram of the boost converter with a PI compensator using ABM blocks. C 2 and R 3 were added to improve convergence. The sawtooth generator was adjusted for a 10-kHz switching frequency. The corresponding inductor current, output voltage, and control waveforms are shown in Figure 9.49. Notice that after an initial perturbation applied at t = 0, the waveforms slowly reach the steady-state value at the end of the simulation at t = 30 ms. The PI controller was simulated using vendor models, as shown in Figure 9.50. The simulation results, shown in Figure 9.51, are very similar to those obtained using ABM blocks. Transient simulations using vendor models require longer execution time and generate much larger output files. They also present more convergence problems; therefore, they should be used only when they are strictly necessary. The OPTIONS used in this simulation, as extracted from the output file are: 'Analysis directives: .tran 30m 10 n skipbp 420 Power-Switching Converters iov^v, '- pwm 10 mH IC=1.8 gate c 2 — II- -vA- -W xS* Tioou ? B iic=2o : T flOm 4^ "0 VOFF = 0.0V VON -1.0 V il( V(%IN1) < V(%1N2),1,0) 2 control v, = o V 2 =10 TO = TR = 99.9 u TF = O.OS u PW=0.05u — PER = 100 u -WSr- -HI— V Z -wv- 00*^1 -CD Figure 9.48 PI compensation using ABM blocks. 4.0 A- 2.0 A- • 1^) 10V SEL» « V(OUT) 5V C s 5ms « W[CONTROL) 10 ms 15ms Time 20 ms 25 ms 30 m s Figure 9.49 Simulation results of the PI compensation using ABM blocks. .OPTIONS STEPGMIN .OPTIONS PREORDER .OPTIONS ABSTOL= 10.0p .OPTIONS CHGTOL= 0.1 p .OPTIONS ITL2 = 200 Simulation of Switching Converters *!k 1 Ti_ 2 pvvfn *..J 421 10 V, «s!_rT] Figure 9.50 PI compensation using vendor models. 2.0 A «t,) » V(OUT) 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms « VJOONTROL) Time Figure 9.51 Simulation results of the PI compensation using vendor models. .OPTIONS m.4 = 400 .OPTIONS RELTOL= 0.01 .OPTIONS VNTOL= 10.0u 422 Power-Switching Converters This simulation ended before the reaching the final time because the data file became larger than the program can handle, giving he following error message: i/o error - Probe file size exceeds 2000000000 JOB ABORTED TOTAL JOB TIME 912.11 The reader must note the large amount of data generated by this simulation and the long execution time required. If just a transient stability check was needed, a small-signal simulation using an average model or switching simulations with ABM blocks would have been sufficient. 9.6 CREATING CAPTURE SYMBOLS FOR PSPICE SIMULATION Vendors often provide PSpice models for their circuit components. They are normally provided in a text file with extension -LIB; if the file has a different extension, it should be changed to .LIB. A good practice is to save the model libraries in a personal folder to avoid losing them. Start the PSpice Model Editor and from the File menu, choose Create Parts. Browse to find the input model library (.LIB file) and click OK to start. The message log should show errors. This step creates an .OBL file with a schematic symbol linked to your model. The created symbol will have a meaningful shape if the model was provided with a .MODEL statement; in case of a .SUBCIRCUIT (sometimes called a macromodel) representation, the symbol will be a square box. To place the new part into the schematic,_open Capture, and from the Place menu choose Part. Click Add library,-then find and add the new ".OLB" file. The simulator should be linked to the model library. Before running the simulation, the model library (.LIB file) is to be added into the simulation profile. In Capture from the PSpice menu, choose Edit Simula- tion Profile. Click the Libraries tab. Use the Browse button to find and then add the vendor ".LIB" file. The library can be added for the current design only or it can be made available for all designs. If you do not like the square box symbol created from the .SUBCIRCUIT model, you may create your own symbol. For more information, please refer to the PSpice A/D User's Guide (pspicead.pdf), in the chapter "Creating Parts for Models" [2]. 9.7 SOLVING CONVERGENCE PROBLEMS [8] This section gives a brief overview of the convergence problems com- monly encountered in PSpice simulations ^und tips on how to solve Simulation of Switching Converters 423 them. For a more detailed explanation, refer to PSpice User's Guide [2] and Rashid [3]. Convergence problems may arise in PSpice when solving for the bias point, DC sweep, and transient analysis of analog devices. PSpice uses the Newton-Raphson algorithm to solve the nonlinear equations in these ana- lyses. The algorithm is guaranteed to converge only if the analysis is started close to the solution. If the initial guess is far away from the solution, it may cause a convergence failure or even a false convergence. When PSpice cannot find a solution to the nonlinear circuit equations, it gives a "convergence problem" message. The message gives a clue to which part of the circuit is causing the problem. Looking at these devices or nodes, or both, is a good starting point to solve the problems. The AC and noise analyses are linear and do not use an iterative algorithm, digital devices are evaluated using Boolean algebra^ so the following discussion does not apply to both of them. PSpice solves the nonlinear equations using an iterative algorithm. Starting from the initial guess, the algorithm calculates the node voltages and the mesh currents. The currents are then used to recalculate the node voltages and the algorithm keeps repeating until the entire node voltages settle to within certain tolerance limits set by various .options parameters. If the node voltages do not settle down within a certain number of iterations, an error message will be issued. The error message will depend on the type of analysis performed. 9.7.1 DC Analysis Error Messages The DC analysis calculates the small-signal bias points before starting the AC analysis or the initial transient solution for the transient analysis. Solu- tions to the DC analysis may fail to converge because of incorrect initial voltage guesses, model discontinuities, unstable or bistable operation, or unrealistic circuit impedances. The DC analysis will then issue an error message, such as "No convergence in DC analysis," "pivtol Error," "Sin- gular Matrix," or "Gmin/Source Stepping Failed." When an error is found during the DC analysis, SPICE will then terminate the run because both the AC and transient analyses require an initial stable operating point in order to start. The DC SWEEP analysis may give "No Convergence in DC analysis at Step = ###" error message. 9.7.2 Transient Analysis Error Messages During the transient analysis, the iterative process is repeated for each individual time step. If the node voltages do not settle down, the time step is reduced and SPICE tries again to determine the node voltages. If the time 424 Power-Switching Converters step is reduced beyond a certain fraction of the total analysis time, the transient analysis will issue an error message "Time step too small" and the analysis will be halted. Transient analysis failures are usually due to model discontinuities or unrealistic circuit, source, or parasitic modeling. 9.7.3 Solutions to Convergence Problems There are two ways to solve convergence problems; the first only tries to fix the symptoms by adjusting the simulator options; while the other attacks the root cause of the convergence problems. Invariably, the user will find that once the circuit is properly modeled, many of the modifications of the options parameters will no longer be required. It should be noted that solutions involving simulation options may simply mask the underlying circuit instabilities. The following techniques can be used to solve most convergence problems. When a convergence problem is encountered, the reader should follow the indications in the given order until convergence is achieved. 9.7.4 Bias Point (DC) Convergence In case the calculation of the bias point fails to converge, the circuit topology and connectivity should first be checked, followed by modeling of circuit components. The PSpice options are checked to ensure that they are prop- erly defined. 9.7.5 Checking Circuit Topology and Connectivity . Make sure that all of the circuit connections are valid, o Check for incorrect node numbering or dangling nodes. • Verify component polarity. • Check for syntax mistakes. • Make sure that the correct PSpice units (i.e., MEG for 1E6, not M, which means mili in simulations) are used. . Make sure that there is a DC path from every node to ground. . Make sure that there are at least two connections at every node. • Make sure that capacitors and/or current sources are not connected in series. • Make sure that no (groups of) nodes are isolated from ground by current sources and/or capacitors. . Make sure that there are no loops of inductors and/or voltage sources only. • Place the ground (node 0) somewhere in the circuit. Simulation of Switching Converters . Be careful when floating grounds (e.g., chassis ground) are used; a large resistor should be connected from the floating node to ground. All nodes will be reported as floating if "0 ground" is not used. . Make sure that voltage-current generators use realistic values, and verify that the syntax is correct. . Make sure that dependent source gains are correct, and that E/G element expressions are reasonable. Verify that division by zero or LOG(0) cannot occur. 10 . Voltages and currents in PSpice are limited to the range ±1x10 . Care must be taken that the output of behavioral modeling expres- sions falls within this range. . Make sure that there are no unrealistic model parameters, especially if the models are manually entered into the netlist. . Avoid using digital components unless really necessary. . Initialize the digital nodes with valid digital values to ensure the state is not ambiguous. . Avoid situations where an ideal current source delivers current into a reverse-biased p-n junction without a shunt resistance. This is be- cause p-n junctions in PSpice have no leakage resistance. As such, the junction voltage would go beyond 1 x 10 V. 9. 7.5. 1 Setting up the Options for the Analog Simulation Since Spice was originally designed for integrated circuits simulation, the default values of some overall parameters are not optimal for power electronic circuits. Some of the simulation parameters may have to be changed using the following guidelines. . Increase ITL1 to 400. This increases the number of DC iterations that PSpice will perform before it gives up. In all, but the most complex circuits, further increases in ITL1 will not typically aid convergence. . Use nodesets to set node voltages to the nearest reasonable guess at their DC values, particularly at nodes that are isolated by high impedances, and at nodes that are inputs to high-gain devices, node- sets hold these voltages at the specified value while the rest of the circuit converges to a reasonably stable point, and then "releases these voltages for a few more iterations to find the final, complete solution. . Enable the gmin stepping algorithm [9] to aid with the bias point convergence. 426 Power-Switching Converters o Set freorder in Simulation Profiles options. This is more important while editing schematic for marginally convergent circuits. o Power electronic circuits may not require tight current-voltage toler- ances. Setting the value of abstol to 1 p. will help in the case of circuits that have currents which are larger than several amperes to converge. • Unless the circuit conducts kiloamperes of current, however, setting abstol to a value -greater than 1 u. will cause more convergence problems than solving it. • PSpice does not always converge when relaxed tolerances are used. For example, setting the tolerance option, reltol, to a value, which is greater than 0.01 can actually cause convergence problems. • Setting gmin to a value between 1« and lOn will often solve conver- gence problems. • Setting gmin to a value greater than 10n may cause convergence problems. 9.7.6 Transient Convergence The transient analysis can fail to complete if the time step becomes too small. This can be due to either (a) the Newton-Raphson iterations would not converge even for the smallest time step size or (b) circuit paramaters are changing faster than can be accommodated by the minimum step size. The circuit topology and connectivity should first be checked, followed by the modeling of circuit components. Finally, the PSpice options should be checked to ensure that they are properly set. 9. 7.6. 1 Circuit Topology and Connectivity • Avoid using digital components unless really necessary. • Initialize the nodes with valid digital value to ensure that there are no ambiguous states. These can cause the time step to go unnecessarily too small, and hence, a transient convergence issue. • Use RC snubbers around diodes. • Add capacitance for all semiconductor junctions (if no specific value is known: CJO = 3pF for diodes, CJC and CJE = 5pF for BJTs, CGS and CGD = 5pF for JFETs and GaAsFETs, CGDO and CGSO = 5 pF for MOSFETs). • Add realistic circuit and element parasitics. » Parasitic capacitances: It is important that switching times be non- zero. This is assured if devices have parasitic capacitances. The semiconductor model libraries in PSpice have such capacitances. If Simulation of Switching Converters 427 switches or controlled sources, or both, are used, then care should be taken to ensure that no sections of circuitry could try to switch in zero time. . Inductors and transformers: It is recommended that all inductors have a parallel resistor (series resistance is good for modeling DC effects but does not limit the inductor's bandwidth). The parallel resistor gives a good model for eddy current loss and limits the bandwidth of the inductor. The size of resistor should be set to be equal to the inductor's impedance at the frequency at which its Q begins to roll off. . Look for waveforms that transition vertically (up or down) at the point during which the analysis halts. These are the key nodes, which should be examined for problems. o Increase the rise and fall times of the pulse sources. . Ensure that there is no unreasonably large capacitor or inductor. 9.7.6.2 PSpice Options Set reltol = 0.01. This option is encouraged for most simulations since the reduction of reltol can increase the simulation speed by 10% to 50%. Only a minor loss in accuracy usually results. A useful recommenda- tion is to set reltol to 0.01 for initial simulations, and then reset it to its default value of 0.001 when a more accurate answer is required. Setting reltol to a value less than 0.001 is generally not required. Reduce the accuracy of abstol/vntol if current/voltage levels allow it. abstol and vntol should be set to about eight orders of magnitude below the level of the maximum voltage and current. The default values are abstol = lpA and vntol =luV. These values are generally associated with IC designs. Increase ITL4, but not more than 100. This increases the number of transient iterations that PSpice will attempt at each time step before it gives up. This is particularly effective in solving convergence problems when the simulation needs to cover a long time period, and fast transitions occur within the circuit during that time. Values greater than 100 will not usually bring convergence. Skipping the bias point: The skipbp option for the transient analysis skips the bias point calculation. In this case the transient analysis has no known solution to start from and, therefore, is not assured of converging at the first time point. Because of this, its use is not recommended. Its inclusion in PSpice is to maintain compatibility with UC Berkeley SPICE. Any applicable .IC and IC = initial conditions statements should be added to assist in the initial stages of the transient analysis. The initial -mm ^m 428 Power-Switching Converters conditions should be chosen carefully because a poor setting may cause convergence difficulties. 9.8 SWITCHING CONVERTER SIMULATION USING MATLAB MATLAB [10] is a very convenient tool for the analysis of switching con- verters using the state-space averaging method and transfer functions. MATLAB can handle matrices and polynomials easily. This section intro- duces the use of MATLAB for switching converter analysis using an example. 9.8.1 Working with Transfer Functions Consider a buck converter designed to operate in the continuous conduction mode having the following parameters: R = 4 ft, L = 1 .330 mH, C= 94 n.f, V s = 42 V, K a = 1 2 V. The transfer function of a boost converter obtained using the averaged-switch model can be expressed as VoO) _ K (1 + (s/szQ){\ - 0Az2» (9 j n d{s) ~ d 1 + (*/«oG) + (* 2 /" 2 o) ' where K d = — V -^, (9-12) (l-D) 2 ' 1 Szl = ResrC (9.13) St2 S±-££(R-R„\\K)-*2±, (9-14) 1 Rm + '>£>(! - D) (9.15) VTCV ^esr + ^R and Simulation of Switching Converters n 2* . (9.17) ^ ~ «*i„d + Ted - D))/L) + (l/C(/?esr + *)) The listings for the MATLAB simulation are as follows: % this is a comment % parameters R = 4; L = 1.330 e-3; Rind = 100 e-3; C = 94 e-6; Resr = 10 e-3 Vs = 42; Va = 12; D = Va/Vs; Kd = Vs/(1-D)*2; Sz1 = 1/(Resr*C); Req = R-(Resr* R/(Resr+R)); Sz2 = (1/L)* (1^D) A 2* Req-Rind/L; Re = (Resr*R)/(Resr+R); Wo = (1/sqrt(L*C))*sqrt((Rind+re* D*(1-D))/(Resr+R)); Q = Wo/(((Rind+ re*(1-D))/ L)+(.1/(C*(Resr+R)))); The semicolon at the end of each line prevents the value to be displayed when the simulation is running. If the result of a calculation is desired, omit the semicolon. % define numerator -^ = K„ j + (5/ft , o0 + (j 2 /w 2) % polynomials are entered in descending order of S. n1 = [1/Sz1 1] n2 = [-1/Sz2 1] NUM = conv(n1,n2) % the convolution realizes the product of 2 polynomials % define denumerator DEN = [1/(Wo A 2) 1/(Wo*Q) 1] % create TF variable sysTF = Kd*tf(NUM,DEN) which returns Transfer function: 430 sysTF Power-Switching Converters - 5.3 1 7 e - 008 s A 2 - 0.05648 s + 82.32 4.913 e - 006 s A 2 + 0.01343 s + 1 The location of the poles can be found using poles = roots(DEN) and the frequency response can be plotted using bode(sysTF) resulting in the plot shown in Figure 9.52. The small signal transient step response can be plotted using Figure % this command opens a new figure window step(sysTF) This yields the plot of the step response shown in Figure 9.53. 40 Bode Diagram 1 ' ^— i 20 ^*** »%. m -o Q> 3 ■ c CD to > -20 ..■>> ■■■' » • « niiil 1 — i tint ilT"! I 1 10 1 102 10 3 10 4 10 5 Frequency (rad/sec) Figure 9.52 Bode plot of the system under study. 10 6 Simulation of Switching Converters 431 Step Response 0.01 0.02 0.03 0.04 0.05 Time (sec) Figure 9.53 Step response of the system under study. 0.06 0.07 0.08 9.8.2 Working with Matrices Consider a buck converter designed to operate in the continuous conduction mode having the following parameters: /? = 4 ft, L= 1.330 mH, C=94^.f, F S = 42V, K a = 12V. The model parameters can be defined by: % state-space averaged model of a Buck converter Rload = 4; % load resistance L = 1 .330E-3; % inductance cap = 94E-6; % capacitance Ts = 1 E-4; % switching period Vs = 42; % input DG voltage Vref = 12; % desired output voltage The average duty cycle is D = Vref/(Vs); % ideal duty cycle 432 Power-Switching Conveners From state-space analysis of a buck converter in Chapter 6, the small- signal averaged state-space equations are The matrices of the averaged state-space model A, B, and C are entered as follows: A = [0 -1/L 1/cap-1/(Rl0ad*cap)] B1 = [1/L 0]; % during Ton B2 = [0 0]; % during Toff B=B1*D+B2*(1-D) C = [0 1]; The open-loop poles of the Buck converter can be calculated by using the eig() function to evaluate the eigenvalues of the system matrix A. OLpoles = eig(A) The state-space open-loop model is defined as sysOL by the SS command. The step response of the open-loop converter can be plotted using the step() command: sysOL=ss(A,B,C,0) step(sysOL) A "help" statement can be used to learn more on any MATLAB command. For example, help step Figure 9.54 shows the transient response of the small-signal model of the converter for a step input at U| obtained using the step( ) command. The command line gamma =[Vs/L0]; defines the vector that reflects the changes in the duty cycle on the state variables. The feedback gains can be found in order to determine the closed-loop poles at any desired location. In this case, the closed-loop poles are arbitrar- ily chosen to be located at (-0.3298 ± j 0.1). Start by defining a vector containing the desired closed-loop_poles: P = 1e3* [-0.3298 + 0.10i -0.3298 -0.10i]'; Simulation of Switching Converters 433 Step Response From: U (1) 0.5 1 15 2 2-5 3 Time (sec.) 3.5 4 4.5 x10- 3 Figure 9.54 Step response of the linearized buck converter. Notice the notation for the complex numbers. The "i" is placed right after the imaginary part. The apostrophe represents the transpose operation. Now by using the placeQ command, the feedback gains can be defined as: Bf= gamma*(D/Vref); F = place(A,Bf,P) The place command computes a state-feedback matrix F such that the eigenvalues of A - Bf*F are those specified in vector P. No eigenvalue should have a multiplicity greater than the number of inputs. 434 Power-Switching Converters 9.9 SWITCHING CONVERTER SIMULATION USING SIMULINK Simulink [11] is a graphical input interface for MATLAB. This section introduces its use in the simulation of the switching converters by simulat- ing the previous transfer function and state-space examples worked using MATLAB. 9.9.1 Transfer Function Example Using Simulink There are two different ways to describe a transfer function in Simulink, as a ratio of polynomials and as a ratio of zeroes and poles. For the previous example, the transfer function is sysTF = -5.317e - 8 s A 2 - 0.05648s + 82.32 4.91 3e - 6s A 2 + 0.01343 s + 1 The numerator and denominator may be recovered from the transfer func- tion by [NUM.DEN] = TFDATA(sysTF.'v') The contents of the variables num and den are then used in the Transfer Fen block (Figure 9.55). To evaluate the step response of the system, connect a Step block from the source library and a Scope block from the sink library. Then setup the simulation parameters for a stop time of 50e-3 s and the step time at zero for the Step block. Save and run the simulation. Double-clicking on the Scope block will open the scope window and the trace of the step response will be displayed (Figure 9.56). The To Workspace blocks make the selected Simulink variables avail- able from the MATLAB command window. The step response can be plotted in a MATLAB figure by the plot(time, output) command. Step ©- Clock -5.31 7e-8s 2 -0.0565s+82.32 4.91 3e-6s 2 +0.01 34s+1 .0 Transfer Fen time i i Scope [_► output To Workspace To Workspacel Figure 9.55 Simulink polynomial representation of a transfer function. Simulation of Switching Converters 435 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 Time (sec) Figure 9.56 Step response. Step -0.01 0821 (s+1 .Q638e+006)(S-1 455) (s+2657)(s+76.6) Zero-Pole Scope 0- time output To Workspace Clock To workspacel Figure 9.57 Simulink ZPG representation of the transfer function. The zero-pole-gain form of the transfer function can be obtained using (Figure 9.57): sysZPK = zpk(sysTF) which yields: Zero/pole/gain: 436 sysZPK Power-Switching Converters -0.010821(s+ 1.064e006)(s - 1455) (s + 2657)(s + 76.6) Then, the parameters of the zero-pole block are entered as follows: zeroes: [-1.0638e+006 +1455} poles: [-2657 -76.6] gain: [-0.010821] 9.9.2 State-Space Example Using Simulink The switching converter of Equation (9.18) has the following state-space matrices: _ r 752 I = [10638 -2660 J 752 .10638 -2660 B =[214.82 0]' C=[0 1]' D = 0. (9.19) The averaged model of the switching converter using the state-space repre- sentation is shown in Figure 9.58. The parameters of the state-space block are entered as shown in Equation (9.19). PROBLEMS 9.1. Using PSpice simulation, determine the harmonic contents of a boost converter having the following parameters: F S = 9V, K a =12V, /? L = 120,1,= 1 mH,C = 100u.F,/s = 1 kHz. Use theTTP41BJT vendor model for the switching transistor. Comment on the harmonic contents when the switching frequency increases to 10 kHz. Step o- Clock x" = Ax+Bu y= Cx+Du State-Space □ Scope time output To Workspace To Workspacel Figure 9.58 State-space representation of the switching converter. Simulation of Switching Converters 9 2 The parameters for the flyback converter shown in Figure 4.10 are: L s =500m.H, N P = N„ A: ps = 0.999, V s = 100V, / s =5kHz, /? L =10n, and C„= 100 pF. Using PSpice, determine the duty cycle for the onset of the continuous mode of operation. 9.3. Using PSpice, simulate the Ciik converter shown in Figure 2.27 with the following parameters: Li=lmH, C, = 100mF, L o =10mH, C = 47 ix,F,f s = 10 kHz, D = 0.4, and R v = 10 SI. The switching transis- tor, g s , is a TIP41 bipolar transistor. Determine the input ripple cur- rent, voltage across the energy-transfer capacitor, and the output ripple voltage from PSpice simulations and compare these values to the cal- culated values. 9.4. The switching frequency of the voltage-mode PWM boost converter shown in. Figure 9.29 is 20 kHz. Determine the compensation network if the unity-gain crossover frequency is 4 kHz and a phase margin of 40° is desired. 9.5. The current-mode PWM quasi-resonant ZCS buck converter from Example 3.1 is designed to have an output voltage of 6Y. Compare the calculated switching frequency to that obtained from PSpice simu- lation. 9.6. (a) Design an ideal buck-boost converter that would operate with a duty cycle of 60%. Choose the circuit parameters to provide an output power of 10W. Show all the necessary calculations, (b) Simulate the circuit using ideal components and parts from the ABM library. Evalu- ate and plot the conversion ratio versus D. (c) Simulate the circuit including component losses and vendor models using the appropriate parts and data sheets. Evaluate and plot the conversion ratio versus D. (d) Evaluate the line and the load regulations by parametric simula- tions, (e) Design a closed-loop regulator for the circuit in c) using ABM parts for the control and feedback blocks. Evaluate the line and load regulations. Notice how the duty cycle varies to keep the output voltage constant. . 9.7. (a) If PSpice stops running due to convergence problems during a transient analysis, explain how you would modify the circuit and the simulation options to aid with convergence, (b) How do you improve the definition of the waveform obtained in a transient simulation? (c) How do you improve the definition of the waveform obtained in an AC simulation? 9.8. Draw a closed-loop synchronous buck converter showing a generic 3-pole 2-zero compensation network. Use components from the ABM library for the error amplifier, feedback network, and PWM modulator. Design the ramp generator to provide with a 100-kHz sawtooth wave- 438 Power-Switching Converters form swinging from to IV. Setup the reference voltage for a 50% nominal duty cycle. Calculate Beta. REFERENCES 1. U. C. Berkeley SPICE Version 2G User's Guide, August 1981. 2. PSpice User's Guide, Pspug.pdf, Oread Personal Productivity Solu- tions, Lite Edition, Cadence Design Systems, Inc., 2nd ed., May 31, 2000. 3. M. H. Rashid. Microelectronics Circuits: Analysis and Design, PWS Publishing Company, Boston, 1999. 4. V. Vorperian. Simplified analysis of PWM converters using the model of the PWM switch: Parts I and II, IEEE Trans. Aerosp. Electron. Syst., 26(2), March 1990. 5. C. P. Basso. Switch-Mode Power Supply SPICE Cookbook, ISBN: 0071375090, McGraw-Hill, New York, 2001. 6. R. B. Ridley. A new continuous-time model for current-mode control, IEEE Trans. Power Electron., 6(2), 271-280, 1991. 7. B. Yaakov. Average simulation of PWM converters by direct imple- mentation of behavioral relationships, IEEE Applied Power Electronics Conference, 1993, pp. 510-516. 8. T. S. Kukal and S. Sharma. Convergence Guide, Cadence Design Systems, Inc., July 2003. 9. T. L. Quaries. Analysis of Performance and Convergence Issues for Circuit Simulation, U.C. Berkeley, ERL Memo M89/42, April 1989. 10. Getting Started with MATLAB, The Math Works, Inc., Natick, MA, 2000. 11. Learning Simutink, The MathWorks, Inc., Natick, MA, 2000. 10 Switching Converter Design: Case Studies 10.1 INTRODUCTION Switching converters find their-major application in switching power supplies. The major feature of switching power supplies is their high power packing density resulting from their high conversion efficiency. In general, the power packing density Of a switching converter increases with its switching fre- quency. This is due to a reduction in size and weight of its storage elements as its switching frequency increases. Furthermore, the switching action of the transistor in a switching converter reduces unnecessary power losses. Switching converters are also used in direct-current (DC) motor drives. They are commonly known as choppers. DC motor drives are widely used in applications requiring adjustable speed control, good speed regulation, and frequent starting, braking, and reversing. Some important applications are rolling mills, paper mills, battery-operated forklift trucks, battery-operated trolleys, and machine tools. Recently, induction and synchronous motors are also becoming popular in. variable speed applications due to advances in their inverter speed drives. 439 440 Power-Switching Converters The other lesser known application of the switching converter is in the pulse-width modulator (PWM) switching audio amplifier. PWM switching audio amplifiers have been in existence for many years. The major advantage of the PWM switching audio amplifier is in the power conversion efficiency. Class AB amplifiers, commonly used in audio amp- lifiers, have a maximum theoretical power conversion efficiency of less than 78.5%. However, the practical power conversion efficiency of a typical class AB amplifier is between 35% and 40% [1]. On the other hand, practical PWM switching audio amplifier offers a power conversion efficiency higher than 80%. Even though dedicated integrated circuit controllers remain the work- horse of controllers for switching converters, microprocessor and digital- signal-processors are finding their niches as controllers for some switching converter applications. Digital-signal-processor (DSP) allows the implemen- tation of flexible digital control, monitoring, and communication functions required in the new generation of digital power supplies. By changing the controller algorithm, a totally digital power supply platform can be achieved without changing the switching converter topology. In addition, more effi- cient switching converter topologies, which take advantage of advanced nonlinear digital control techniques, may be used to obtain optimum per- formance over the complete operating range of the power supply. Further- more, current-mode control of switching converters can be enhanced by replacing the compensation ramp for state feedback control, thus simplify- ing the design of feedback gains for the desired transient response. The use of microprocessor or DSP adds signal processing capability and, therefore, makes such switching converter smarter and more versatile than those with conventional integrated-circuit controllers. Furthermore, the microproces- sor- or DSP-based controller can be easily adapted to changing requirements of the switching converter through software revision. In chopper applica- tions, microprocessor or DSP controllers allow the use of complex control algorithms to shape the responses of DC motors. Several design examples of switching converters are presented in this chapter. The design of a simple TL594-based buck converter is first dis- cussed. This is followed by a brief discussion on the design of a DSP-based synchronous buck converter. By changing the software, the same hardware can be re-configured to work in current-mode and in voltage-mode with the desired dynamics. This example shows the versatility of the digitally con- trolled switching converters. The design of a flyback converter using three different controllers is then presented. Finally, this chapter concludes with a discussion of the design and evaluation of a practical PWM switching audio amplifier. It should be noted that these designs do not include any system optimization. Switching Converter Design: Case Studies 10.2 VOLTAGE-MODE DISCONTINUOUS-CONDUCTJON- EUIODE BUCK CONVERTER DESIGN A voltage-mode, discontinuous-conduction-mode, buck converter using a TL594 pulse-width modulator [2] will be designed and evaluated. The nom- inal input voltage is 19V, but fluctuates between 17 and 21 V. The output voltage for this converter is specified to be 5 V ± 5%, the load current may change from 30 mA to 0.5 A. Thus, the power rating for this buck converter is 2 5 W. A linear voltage regulator such as the UA7805CKC can be used for this application, although the power loss would be higher than that of the buck converter. The switching frequency is chosen to be 10 kHz. A phase margin of 35° is selected as a compromise between the allowable overshoot and desired rise time. For an average output current of 265 mA, the average load resistance is L - 265 mA and the maximum load (or minimum load resistance) is Rl = 2* = ^= ion. O0-2> L ™ / a 0.5 A The inductor will next be determined to guarantee the discontinuous mode of operation. Its inductance should be smaller than the critical inductance at the highest load current: r rfe^L-^ 2 lOP-0-263) 2 Zj - 2/ s 2-10000 = 0.272 x 10- 3 H = 0.272mH, (10-3) where D is the duty cycle of the buck converter operating in the continuous conduction mode: •>= V t~Wv = ™- 00 ' 4) We choose a smaller inductance value of 0.2 mH. The peak-to-peak ideal inductor ripple current is A /_2i£ = 19(0-6) 57A . (10.5) al ~ f s L 10000(0.2 x 10- 3 ) 442 Power-Switching Converters The output capacitor should be calculated to satisfy the output voltage ripple requirements at full load, i.e., at 7 a = 0.5 A: 1?- 5% or 77^ £5% (106 > then ^jftm-**"*- (107) Experimentally, we choose: C= 3x470|iF. This output capacitance is much larger than the calculated value due to a large ESR on the capacitors. As such, the ripple has to be reduced by increasing the capacitance and parallel- ing three capacitors. The peak-to-peak ideal capacitor ripple voltage is Av c =H = 0-5x0.263 00093V (10 g) f s C 10000 x 1.41 x 10- 3 For a voltage-mode discontinuous-conduction-mode buck converter, the voltage conversion ratio, M, is defined as: M = ^ = . 2 , =0.263. (10.9) y% 1 + y/\ + {ZL/RTslP) With a nominal input voltage of 19 V and an average output voltage of 5 V, the nominal duty cycle for a load resistance of 10 O is D = \ 8i =0.194. (10.10) RT S (GSH'-0 10.2.1 Controller Design The switching frequency of the PWM is determined by C, and R t . For a C t of 0.01 u.F, the required R t for a switching frequency of 1 kHz is 1 kft . Due to the discontinuous-conduction-mode of operation, the buck converter yields a first-order response with a corner frequency at _ 2-M 2 - 0.263 Jp ~ 2-17(1 - M)RC ~ 2tt(1 - 0.263)10 x 3 x 470 x lO" 6 = 15.3 Hz. (10-11) Switching Converter Design: Case Studies 443 Assuming an effective R esT of lOOmfl, the output capacitors introduce a zero at f » 1 • /zESr ~ iTrKcsrC 2-ttIOO x 10- 3 x 3 x 470 x lO" 6 = 1129 Hz. 00.12) A reference voltage of 3 V is fed to the noninverting input of the error amplifier through a voltage divider from the on-chip 5-V reference voltage of the TL594. The sampled voltage from the output of the buck converter is fed to the inverting input of the error amplifier. Consequently, the sampling network contributes an attenuation of -4.43 dB to the open-loop magnitude response of the buck converter. Neglecting the open-loop gain of the com- parator, the PWM contributes a gain of 20 log, (VJV p ), where V p is the peak amplitude of the sawtooth voltage. Since the peak amplitude of the sawtooth voltage is 10 V, the pulse-width modulator contributes a gain of 201og 10 (^)=5.57dB. (10-13) Thus, the low-frequency gain of the open-loop buck converter is 1.14dB. Simulations of the voltage-mode discontinuous-conduction-mode buck con- verter were performed to verify the design. Figure 10.1 shows the schematic circuit of the open-loop buck converter using vendor models of the chosen components. The PWM modulator is modeled by ABM blocks. The series resistance of the inductor is i? s = 0.696 fl and the ESR of the capacitor is i? csr = 0.1 ft. The ABM2 block models an ideal PWM modulator that generates the 30% duty cycle by comparing the 10-V sawtooth signal provided by V p with the reference voltage, V ret , of 3 V. A larger duty cycle was used to compensate for the circuit losses. Figure 10.2 and Figure 10.3 show the simulated output voltage and the output voltage ripple waveforms. It can be seen that the output voltage is close to the desired value of 5 V and the ripple voltage is bounded within 0.25 V (5% of 5 V). The simulated inductor current waveform is plotted in Figure 10.4. The inductor current is zero for a certain amount of time in one switching cycle, thus verifying that the circuit is operating in the discontinuous- conduction mode. 10.2.2 Small-Signal Model The small-signal model of the switching converter is shown in Figure 10.5. The parameters of the error amplifier were found using the information 444 Power-Switching Converters M, IRF9Z30 L, 0.2 mH 19^-=- V, Ft, _W\r- il(V(%IN1)<Vt%IN2).5,0) Ka — dih- PER = 100 u Figure 10.1 Open-loop buck converter circuit. 6.0 V 5.0 V 2.5 V 1.41 mF 0.1 0s 5 10 » M[RL:1) 15 20 "25 30 35 40~ Time (msec) V 10 45 50 Figure 10.2 Output voltage of the open-loop buck converter. Switching Converter Design: Case Studies 5.140 Vi 445 (49.432m,5.1247) 5.000 V 4.961 V-lr (49.508m,4.9786) 49.20 49.30 - V(RL:1) 49.40 49.50 Time (msec) 49.60 49.70 Figure 10.3 Output voltage ripple. 1.48 A 1.00 A 0.50 A 0A 48.800 48.850 48.900 48.950 49.000 49.050 49.100 * KLi) Time (msec) Figure 10.4 Inductor current of the open-loop buck converter. 446 Power-Switching Converters BUCKVM 19 V, ~0 Figure 10.5 Averaged-inductor small-signal model for the loop gain. provided in the data sheet of the TL594 controller [2]. The Bode plot of the loop gain is given in Figure 10.6. 10.2.3 Design of the Compensation Network and Error Amplifier The unity-gain crossover frequency, f\, was chosen to be one-tenth of the switching frequency, / s , or 1 kHz. From the Bode plot of Figure 10.6, the magnitude of the loop gain at/i can be found to be — 13.8dB at a phase of -103°. Therefore, the compensation network should provide a gain of 13.8dB and a phase of -42 c at/, to yield a 35° phase margin. A 2-zero and 3-pole PID compensator, as shown in Figure 10.7, was chosen as the compensation network. The magnitude and phase of the compensation network are shown in Figure 10.8 and Figure 10.9, respectively. &i is the magnitude at the fre- quency of the double-zero (/ zd ) and k 2 is the magnitude at the frequency of the double-pole (/J,d). The phase required from the compensation network is -43° = 2 tan" (£)—-(£> (10.14) Switching Converter Design: Case Studies 447 20- -0- -20- -40- -60 -Otf -40d -60d SEL» -120d 1.0000k, -13.834) DB (V(VF)) 1.0 mHz 10mHz 100 mHz 1.0 Hz 10 Hz 100 Hz 1.0 kHz 10 kHz 100 kHz ■ F(V(VF)) Frequency Figure 10.6 Bode plot of the loop gain, magnitude, and phase. -II Wr - J WV- «1 - J VW Figure 10.7 Compensation network with two zeros and three poles. The frequency of the double pole can be written as From a circuit analysis of the error amplifier, we have ^1 = -^-> ■fo Ri fpd R 2 (Ri+R3) RtRs ' (C, + C 2 ) , /zd= (10.15) 2ttR 3 C 3 2irR 2 C^C 2 y 7zd 2ir7? 2 C| 2w(/?i +-Ry)C 3 448 Power-Switching Converters 10 4 10^ 1CT Z 10° 10 2 Frequency (Hz) Figure 10.8 Magnitude of the compensation network. The MATLAB program listed below calculates the pole and zero locations using a brute-force algorithm and returns the values of the network com- ponents using the following equations: #2 = ^1*1, *3 = 1 R, C,=- C 2 t/pd// Z d)-l' C, 2ir/ zd i? 2 ' ~ z (/pd/fzd)-!' where R\ is previously chosen as lOkfl. C 3 = 2u/pd/?3 (10.16) 10.2.3. 1 MATLAB Program to Calculate the Compensation Network % iteratively solve for pole location on a % 3-pole 2-zeros (PID) compensation network PhaseBoost = -42; %needed phase boost at 11 (comp network phase atfl) GainBoost = 13.8; %needed gain boost at t1 in dB f1 =1000; %defined by designer, has to be <(fs/2) in Hz Switching Converter Design: Case Studies 80 60 449 40 20 CD o> CD ■n CD CO CO .e D. -20 -40 -60 -80 -100 10^ 10- 2 10° Frequency (Hz) 10 2 10" Figure 10.9 Phase of the compensation network. d2r=pi/180; % degree to radian conversion fpd = 10*fl; %initial guess m = 1; %-keeps the while going while(m), f1z=tan((PhaseBoost* d2r+90*d2r+ 2*atan(f1/fpd))/2); f1/fz f1z=abs(flz); fzd=f1/abs(f1z); % Mag_comp_f1 is the Magnitude of the comp. network at f 1 Mag_comp_f1 =-20*log10(2* pi*f1)+20*log10 (1+(f1z) A 2)-20*log 10 (1 + <f1/fpd)*2) Ph_comp = -90 + 2*atan(f1/fzd)/d2r - 2*atan(f1/fpd)/d2r if ( (Mag_comp_f 1 -GainBoost) > 1 ) df = 2;% frequency resolution fpd=fpd+df; elseif ((Mag_comp_f1 -GainBoost) >0.1) df = 0LO1; fpd = fpd+df; 450 Power-Switching Converters elseif ((Mag_comp_f1-GainBoost) <-1) df=2; fpd=fpd-df; elseif ((Mag_comp_f1-GainBoost) <-0.1) df=0.01; fpd=fpd-df; else m=0; % stop the while end end % check phase Ph_comp = -90 + 2*atan(f1/fzd)/d2r - 2*atan(f1/fpd)/d2r; % calculate k1 and k2 % k1 is the gain of the comp net at fzd k1_db = -20*log1 0(2*pi*f zd)+20*log1 0(1 +(fzd/fzd)*2)-20*log1 (1 + (fzd/fpd)*2) k1 = power(1 0, k1_db/20) % k2 is the gain of the comp net at fpd k2_db = -20*log1 0(2*pi*fpd)+20*tog1 0(1 +(fpd/fzd)*2)- 20*log10(1 + (fpd/fpd) A 2) k2 = power(10, k2_db/20) % calculate components R1 =10e3; %selected by designer R2 = k1*R1 R3 = R1/((fpd/fzd)-1) C1 =1/(2*pi* R2*fzd) C2=C1/((fpd/fzd)-1) C3 = 1/(2*pi*R3*fpd) From the MATLAB simulation, the double zeros are located at 2.31 Hz with a gain of A:, = -17.24dB and double poles are locatecLat 448 Hz with a gain offc 2 =16.43dB. The components for the compensation network are: J^lOkft, R 2 =\31tel, Rj = 52Sl, C,=50ji.F, C 2 = 0^6p.F, and C 3 = 6.8n.F. The simulated magnitude and phase of the compensated loop gain are shown in Figure 10.10. The simulated results are slightly off from the design specifications. For example, the magnitude and phase are 4.3 dB and 139°, respectively, at 1 kHz. The zero crossing occurs at_/i = 1.25 kHz, with a phase of -147°; therefore, the phase margin is 33°, which is in good agree- ment with the design specifications. The small-signal model of the frequency compensated buck converter is shown in Figure 10.11. Switching Converter Design: Case Studies 451 100d P(V|VF)) SEL» -200 (1.0000M-3073) (1.2589fc276.519m) 1.0 mHz 10mHz 100 mHz 1.0 Hz 10 Hz 100 Hz 1.0 kHz 10 kHz 100 kHz 1.0 MHz 10 MHz • DB ' V(VF » Frequency Figure 1 0.1 Magnitude and phase of the loop gain of the compensated circuit. -Wr- U3 BUCKVM IN OUT] DON GNO RS = 0.696 L = 0.2m FS=10* 1.41 mF 0.1 ^ X 03V * 10 E, GAIN = 1 V, ?T q 260n IV 1.37A fl WV- 50u — WV— H 4 1 Meg H 3 52 HI Wv- C 3 B.82U .. . "'i Wr- "---.. 50 + 50 R,10k <^h^ Error ""*-... Amplifier Figure 10.11 Small-signal model of the frequency-compensated buck converter. 452 Power-Switching Converters 10.2.4 The Closed-Loop Buck Converter Figure 10.12 shows the circuit schematic of the closed-loop buck converter. Components with the closest commercially available values were used. This section presents the simulation and experimental results obtained using this circuit, including line regulation, load regulation, and the characteristics of output voltage and output current versus the duty cycle. 10.2.5 Simulation Results Simulations were performed on the closed-loop buck converter using vendor models to validate the design. Figure 10.13 shows the inductor current and output voltage waveforms. As can be seen, the inductor current is discon- tinuous, having an average output current of 0.5 A. The average output voltage is 5.05 V, which is in good agreement with the specifications. As shown in Figure 10.14, the line regulation of the closed-loop converter is very good. The input voltage can change from 12 to 30 V and still can achieve the desired output voltage regulation of 5 V ± 5%. Figure 10.15 predicts that the load regulation of the closed-loop converter will degrade at a light loading, below 50 mA. 10.2.6- Experimental Results This section summarizes the open-loop and closed-loop measurements taken on a laboratory prototype. Open-loop measurements such as the voltage M, IRF9Z30 TiJ - 82 8.2* ^TIP41 0.2 mH IC = 0.5 D1N5401 it (V(%IN1) < V(%IN2),5,0) 2 ©V, V, = V 2 =10 TD = "FR = 99u TF = 1n J_ PW=1n PER = 100 u -Vtr- ~ 1.41 mF lC=-5 0.1 10 GAIN = 0.6 El. V, -H% ¥T 0.26 u C, R, 50 u 1.4* 1 Meg ■0 II VA-i 8u 52 1 ■^W ' <hH Error ***** Amplifier ~0 Figure 1 0.1 2 Closed-loop buck converter. Switching Converter Design: Case Studies 453 5.05 V 5.00 V 28.49 28.60 28.80 29.00 • V(E1:1)« AVG (HRL:1)) 29.20 29.40 Time (msec) 29.60 29.80 30.00 Figure 10.13 Current and voltage waveforms of the closed-loop buck converter. 5.5- Input voltage (V) Figure 1 0.1 4 Line regulation of the closed-loop buck converter. conversion ratio versus the duty cycle and the duty cycle versus the control voltage are important indications for the range of performance of the converter. The open-loop line and load regulations can be used to determine the performance of the converter by comparing them to their closed-loop counterparts. 454 Power-Switching Converters § 3 -§&»**=♦=»♦- 0.1 0.2 0.3 0.4 Load current (A) 0.5 0.6 Figure 10.15 Load regulation of the closed-loop buck converter. 10.2.6. 1 Open-Loop Experimental Data The switching transistor was switched on and off by a variable duty cycle 5 V voltage pulse from a pulse generator. The measured duty cycle versus voltage conversion ratio of the open-loop converter is shown in Figure 10.16. The conversion ratio increases almost linearly with the duty cycle up to 31%. Due to circuit losses, the conversion ratio flattens for a duty cycle range between 31% and 37%; beyond this point, the conversion ratio decreases with an increasing duty cycle. From this plot, the usable range for the duty cycle is between 10% and 31%. Thus, the maximum closed-loop duty cycle should be limited to 31% to achieve good regulation. The nominal duty cycle (Z>= 19.4%) is in the middle of the operating range. 10.2.6.2 Open-Loop Load Regulation The load regulation for the open-loop buck converter under nominal duty cycle and constant average input voltage is shown in Figure 10.17. The output voltage changes almost linearly with the applied load, varying from 5 to 5.5 V for a load variation of 10 to 40 ft. The open-loop line regulation, shown in Figure 10.18, reveals a linear variation of the output voltage with the input voltage, V s . The linearity of the TL594 FWM modulator was tested by injecting a variable DC voltage at the feedback input, using the test circuit given for parameter measurement in the TL594 data sheets [2]. The control voltage was varied and the duty cycle was measured at the output of the controller, yielding the PWM modulator gain plot of Figure 10.19. The duty cycle changes almost linearly with the input voltage. Switching Converter Design: Case Studies 455 10 20 30 Duty cycle (%) Figure 10.16 Voltage conversion ratio versus duty cycle of the open-loop buck converter at full load (K S =19V, / a = 0.5 A). 5.6 10 20 30 Load resistance (%) Figure 10.17 Open loop load regulation at duty cycle 26% and K s = 19 V. 10.2.6.3 Bode Plot of the Loop Gain The loop gain was measured by injecting a sine wave into the PWM modulator, in addition to the DC reference voltage, V ret . The amplitude of the sine wave was kept small to satisfy the small signal variations in the duty cycle. A passive low-pass filter was connected at the output of the buck converter to filter out the high-frequency ripple from the output voltage. The experimental data corresponding to the loop gain using the low-pass filter is shown in Figure 10.20. To obtain the loop gain of the converter, the transfer function of the added low-pass filter (Figure 10.21) needs to be subtracted 456 Power-Switching Converters ■ ~» — i — ' — ' — ' — ' — r 12 13 14 15 16 17 18 19 20 21 22 23 Input voltage (V) Figure 1 0.1 8 Open loop line regulation at duty cycle 26%. 1.0 -I 1 1 r 1.4 1.6 2.0 2.4 3.0 Reference voltage (V) Figure 1 0.1 9 PWM modulator gain of the TL594 controller. from the total response. Subtracting the low-pass filter response from the total response, the loop gain was obtained, as shown in Figure 10.22, which is very similar to the simulated data. 10.2. 6.4 Closed-Loop Experimental Results Figure 10.23 shows the output voltage, inductor current, and duty cycle waveforms of the TL594-based buck converter with a nominal input voltage of 19 V and a load current of 0.5 A, captured using a digital storage oscillo- scope. Channel 3 displays the output voltage waveform. The average output voltage is 5 V with an output ripple voltage of 0.5 V. This is most likely due to Switching Converter Design: Case Studies 457 Figure 10.20 Bode plot of the loop gain including the low-pass filter, (a) ampli- tude of the loop-gain with low-pass filter; (b) phase response of the loop-gain with low-pass filter. Ot I | -20 1 m -30 \ o -40' \ a. \ <* \- ^"**>«^ 1 -D -90 1 2 3 Frequency (kHz) 4 5 Figure 1 0.21 Frequency response of the low-passiilten (a) amplitude of the low- pass filter, (b) phase response of the low-pass filter. the equivalent series resistance associated with the output capacitor. Channel 2 displays the inductor current. It is obvious that the buck converter is operating in the discontinuous mode. Channel 1 shows the duty cycle output of the TL594 that drives the base of the switching transistor, TIP41. The switching frequency is measured to be 10 kHz with a duty cycle of 30%. 1 0.2. 6.5 Closed-Loop Line and the Load Regulations The line and load regulations were measured by sweeping the input voltage and output current, respectively. From Figure 10.24, it is clear that the closed-loop converter has a much better line regulation than its open- loop counterpart. For an input voltage range of 13.5 up to 30 V, the output voltage is between 4.77 and 5.15 V, which is within the 5% line regulation. 458 Power-Switching Converters Figure 10.22 Bode plots of the loop-gain: (a) amplitude of the loop-gain without low-pass filter; (b) phase response of the loop-gain without low-pass filter. 3311.00MS/S 1298 Acqs Ch1 10.0V 2.00V Ch2 500mV M 50.0|1S Ch1J" 6.8 V Figure 10.23 Output voltage, inductor current, and duty cycle from TL594. The load regulation measured on the closed-loop buck converter, shown in Figure 10.25, is quite good. With output load current changes from 0.4 to 3 A, output voltages from 5.2 to 4.76 V were measured. Figure 10.26 shows the circuit schematic of the TL594-based buck converter. The internal 5-V reference voltage is used to obtain the 3-V reference, +3V_K re r, in combination with the resistor divider, R al - R b \- Only error amplifier 1 is Switching Converter Design: Case Studies 459 ft— - ft - 10 15 20 Vi„(V) 25 30 Figure 10.24 Experimental line regulation data. 5.5 1 I i 1 r- 0.5 1 1.5 2 2.5 3 3.5 Load current (A) Figure 10.25 Experimental load regulation data. used. The output of error amplifier 2 is saturated to a low voltage by connecting pin 15 to V s and pin 16 to ground. This forces the internal diode connected in series with the output of error amplifier 2 to be re- versed-biased; therefore, the control signal depends only on the output of the active error amplifier. If the two diodes at the outputs of the error amplifiers are reversed-biased by saturating both error amplifiers to a low "level, pin 3 can be used to have a direct control of the duty cycle. This -technique was used to measure some of the open-loop parameters, like the IPWM modulator linearity, for instance. 460 Power-Switching Converters v, 19 V* M, IRF9Z30 — ni 430ft "I, 680M rfl^100k -»+3V_V„, Figure 1 0.26 Schematic diagram of the TL594-based buck converter. Figure 10.27 shows the output voltage and load current waveforms for the TL595-based buck converter during a load transient. The output current and output voltage of the buck converter change in response to a load variation. The current increases from 0.5 to 1 A, when the load resistor is decreased from 20 to 10ft. As can be seen, the output voltage drops to a lower steady-state level, according to the-load regulation shown in Figure 10.25. The output ripple voltage does not show a significant change. The switching converter takes 4ms to complete the transition. 1 0.3 DIGITAL CONTROL OF A VOLTAGE-MODE SYNCHRONOUS BUCK CONVERTER This section discusses the design, simulations, and experimental results of a digital voltage-mode controller for a synchronous buck converter. First, the discrete-time model of the converter is derived from its continuous-time model. Additional dynamics are then added to achieve a zero steady-state output voltage error. Then, the closed-loop poles of the switching converter are chosen to satisfy a desired transient response using a state feedback technique. A synchronous buck converter was constructed to test the control algorithm. The feedback-gain vector L was calculated using MATLAB, and Switching Converter Design: Case Studies 461 1-* 2-»F,., r i.. CH1 1 .00 V CH2 2.00 V M 1 .00 ms Figure 10.27 Output voltage and load current waveforms during a load transient. Spice simulations were performed to verify the design. Finally, the control algorithm was programmed into a Texas Instruments' TI320F240 DSP that was used to drive the switching converter. It was found that the simulations and experimental results closely matched those from the experiments. 10.3.1 Circuit Parameters The synchronous buck converter comprises of an output inductor of L= 1.33mH, an output capacitor of C=94|i.F, a load resistor of R = 4£l, and two MOSFETS, with an ON resistance of R on = 0.8 ft. The combined resistance of the winding of the inductor and the current-sensing resistor is R L = 1.34ft. The unregulated input DC voltage is K d = 7V, and the regu- lated output voltage is K C = 3.3V. The switching period was chosen as r s =100us for a switching frequency f s = 10 kHz. The amplitude of the sawtooth is set to 10 V. A steady-state duty cycle of D = 12% for the synchronous buck converter was found by open-loop measurements to yield a nominal output voltage of F = 3.3V. The steady-state duty cycle is larger than the ideal duty cycle of A = (33V/7V)100 = 47% due to circuit losses. The continuous-time model was calculated using the above circuit parameters, resulting in: ■[ -(* 1/C -ml i r -i/(jrc>] L -1609 10638 -752 1 -2660 J' (10.17) ■•-■m 462 Power-Switching Converters *-m-m- *-[:i (10.18) 10.3.2 Closed-Loop Pole Selection One way of choosing the closed-loop poles is to select the transfer function an nth-order low-pass Bessel filter, where n is the order of the system that is designed. In the present case, n = 3 because an extended model with add- itional dynamics is used, the order of the system is increased from 2 to 3. The step response of a Bessel filter has no overshoot, thus it is suitable for a voltage regulator. The desired filter can then be selected for a step response that meets a specified settling time. The limit for the minimum settling time is that the control variable does not saturate. The closed-loop poles were chosen by using the following criteria: n-3, settling time <0.5ms. Figure 10.28 shows the transient response of the low-pass Bessel filter. The settling time is nearly 0.4 ms without overshooting. The magnitude component of the frequency response is displayed in Figure 10.29, where the corner frequency is 3 kHz. The S-plane location of the poles of the selected third-order Bessel filter is P S ={-2.449E3 + 72.337E3, -3.093E3}. The desired closed-loop poles were mapped onto the Z plane by Pl = er' T ; resulting in P z = {0.7615 + ./0.1813, 0.7340}. 1.2- 1.0- -0.2 — i i i i i i i ■ ' — 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time (X1e-3 sec) Figure 1028 Step response of the third-order Bessel filter. Switching Converter Design: Case Studies 10- 463 ta ■a -10- -30 1E2 2E2 3E2 4E3 5E3 6E3 7E4 Frequency (Hz) Figure 10.29 Frequency response of the third-order Bessel filter. 10.3.3 Discrete-Time Model A small-signal discrete-time model for the voltage-mode synchronous buck converter was introduced in Chapter 6. The discrete-time model equation for a voltage-mode synchronous buck converter was found to be: x[{n + l)Ts] = VvMxfrTs] + r— - Vref. ' ref The numerical expressions for the model components are: 4>vm = e" _ at _ [0-8187 -0.0600] -" '~ 8484 0.7349 J' roj [OJ K = (Bi - B 2 )U = 5263.2, I _e AV S - ^ 01475 J» (10.19) (10.20) (10.21) (10.22) J^ = _^ = 0.1818l. F ref 3.3 V V (10.23) "■•1 464 Power-Switching Converters Then, the numerical expression for Equation (10.19) becomes .8187 -0.06001,, ^, . ("0.1094 "I,, *[(n+l)r s ] -ft 8484 (K7349 J i[ " rsl+ [a0322j Vref - (10.24) If full-state feedback is applied and the system is controllable, then the closed-loop poles can be arbitrarily placed to obtain a desired transient response. The voltage regulator should have the ability to track the reference voltage even under load variations. Thus, additional dynamics are added. The additional dynamics, represented by <J> a , T a , L 2 , can be obtained by defining a composite state vector: x 6 [k] = idk] x a [k] (10.25) where x a is the state vector of the added dynamics. Then, using the formula for the cascade connection of two state-space systems, the state-space description of the design plant is 4>d = T a c *.]' r ' = [o]' (10.26) where c relates the output to the states through v= ex. A regulator for (4> d , T d ) can be designed and the vector of feedback gains can be partitioned as L = [L 1 L 2 ], (10.27) where L, consists of the first n elements of L, n being the order of the system to be controlled (for a synchronous buck converter n = 2). Z- 2 >s the remain- der of L that relates the output to the states through v a = L 2 x a . L can be found by pole placement of the desired closed-loop poles of the regulator. The main advantage of this configuration is that if the actual closed-loop system is stable, the actual system will track the reference input with a zero steady-state error. For the present case, c = [0 1] (10.28) and *a = i, r a = i. (10.29) 465 Switching Converter Design: Case Studies Refer to Vaccaro [3] for a detailed explanation on how to calculate <J> a and T a . 4> d and r d can be found to be: *d = 0.8187 -0.0600 0.8484 0.7349 1 1 (10.30) r„ = 0.1094 0.0322 (10.31) 10.3.4 Feedback Gains The values for the elements of the feedback vector L were obtained by pole placement, for the desired transient response. The resultant gain vector is: L = [2.5925, 0.4027, 0.2420]. (10.32) The following MATLAB program was used to design the controller: % Continuous time model for the synchronous buck converter clear all R = 4; L=1.33e-3; C = 94e-6; Ron = 0.8; RL=1.34; Ts=1.e-4; Vg=7; Vref = 3.3; A = [-(Ron+RL)/L-1/L 1/C -1/(R*C)] B1=[1/L ]%during Ton B2 = [0 0]%during Toff % Discrete time model for the synchronous buck converter fiVM = expm(A*Ts) pol = eig(fiVM) Un=Vg; K=(B1-B2)*Un D=0.72; 466 Power-Switching Converters fiB=expm(A*(1-D)*Ts);% transition matrix for GamaA GamaA = fiB*K*Ts GamaB = GamaA*D/Vref %tracking regulator % fiComp = 1 ; GamaComp=1; c = [01]; fiDesign = [fiVM[0 0]' GamaComp*c fiComp] GamaDesign = [GamaB 0] % continuous-time closed-loop poles Ps = [-2.449E3+2.337E3J-2.449E3-2.337E3J-3.093E3] % discrete-time closed-loop poles Pz = (exp(Ps*Ts)) % Calculate the Feedback gains L=place(fiDesign,GamaDesign,Pz) The program first calculates the continuous-time state-space matrices of the switching converter (i.e., A, Bi, and B£. The discrete model is then calcu- lated, based on the continuous model, yielding the discrete-time model matrices given in Equations (10.20) and (10.22). The extended model from Equation (10.26) is calculated after the comment %tracking regulator, yield- ing the numerical results shown in Equations (10.30) and (10.31). The desired continuous-time poles are loaded into the variable P s and then mapped into the Z plane, obtaining P z . Finally, the feedback gain vector is calculated by pole placement. 10.3.5 Control Strategy The control variable, v ref , comprises of a steady-state term and a perturb- ation term: Vref = V K{ + V ref , (10.33) where v ref is calculated at the beginning of the kth switching cycle as: M (*) = V ie[ (k) - £,*(*) + y*(k), 00-34) where y,(k) = L 2 x m (k), (10-35) Switching Converter Design: Case Studies 467 x a (k) = <t> a x a (k - 1) + I> a (*), (10.36) u a (k)=V n:t -x 2 (k). (10-37) 10.3.6 Analog Model for PSpice Simulations An interesting by-product of this digital control method is the analog implementation used in SPICE to test the algorithm. This analog version, shown in Figure 10.30, could be built into an integrated circuit to yield a very accurate regulator. The main drawback of the analog implementation is the need for sample and hold circuits. The inductor current, 1 L , is sensed by the Fl block (a current to voltage converter), that produces an output voltage proportional to the inductor current, J L . This current is sampled at r on , the sampled value is held during one switching period at the output of the sample and hold circuit. The nominal value of the minimum value of the current through the inductor is subtracted from the sampled current to produce the state variable x u i.e., the small-signal perturbation of the inductor current at the sampling time. Then, *i is multiplied by the corre- sponding feedback gain, L\. The output voltage is also sampled at / on , and the sample is held at the output of the sample and for an entire switching period. The reference voltage is subtracted from the voltage sample to produce the state variable x 2 , i.e., the small-signal perturbation of the capacitor voltage at the sampling time. Then, x 2 is multiplied by the corresponding feedback gain, L 2 . x 2 is also connected to the discrete compensator that produces the variable y a . The state variables are added to ,y a and the result of this operation is added to the nominal value of the controtvoltage, to determine the variations of the duty cycle. The PSpice model for the sample and hold circuit is shown in Figure 10.31. Ci is charged to the input voltage when the switch closes. When the switch opens, the voltage across the capacitor is held until the next sampling time. The E block acts as a voltage follower, providing impedance trans- formation. The discrete compensator, shown in Figure 10.32, calculates y. a according to Equations (10.29) to (10.35). The MOSFET driver was designed as shown in Figure 10.33. A dead time of 100 ns is modeled with a delay block and logic gates. The E blocks provide the necessary voltage gain to boost the voltage of the 5-V logic to 15 V in order to drive the MOSFETs. El is the upper MOSFET driver that develops a differential output voltage. "outHi" connects to the gate and "outHiL" connects to the source, while "outLo" connects to the gate of the lower MOSFET. 468 Power-Switching Converters {> -^ -w- ■wv- 03 — Ih- -|i° i5 d>Mi-' 4= -o »^ > J ^ to -tor? IV •©- K)3 -©-F — VA— "LIT K- ^® I !Hino •5 O c CO o i — II-' 3" Switching Converter Design: Case Studies 469 cU X -^ Sbreak -0 -AW- 1 m E3 10n Hi 1/c - Figure 10.31 Sample and hold. u a [k)=V m ,-x 2 M "a cBI — >- m cutfl 4> a =i; r a =i X a (/c-1) xa ant *a *a( k - 1 ) +r a U a (k) out ctl l=>— ^K >cf* 1 40 ns I SH SH "o y.W ya L3 0.2408 Figure 10.32 Discrete compensator. "3 ^ J 1 "« AND- \_ DELAY 100ns y^ > ~N GAIN = 4 GAIN = 4 outHi outHiL outLo - Figure 10.33 MOSFET driver. 470 Power-Switching Converters 10.3.7 Simulation Results Simulations were performed using SPICE and MATLAB to verify the design. Figure 10.34 displays the result of a parametric simulation where the load resistor was set to 4 and 8 ft, respectively. The output voltage converges to the nominal voltage of 3.3 V due to the tracking effect included in the additional dynamics. Notice that no overshoot is present during the start-up for R = 4 ft. A feedforward gain (empirically adjusted to —1.2) was added to improve the start-up transient. Figure 10.35 shows a magnified view of the inductor current waveforms corresponding to the two selected load resistors. The current reaches different steady-state values according to the load resistance. Notice that the waveforms repeat every 100 us without subharmonic oscillations and that the duty cycle changes to maintain the output voltage under different loading conditions. The transient response due to a load change from 4 to 3.48 ft at 5 ms is shown in Figure 10.36. Observe that after the initial transient, the output voltage returns to the nominal value with a zero steady-state error. In conclusion, the simulations show that the voltage-mode regulator is able to track the reference voltage with zero steady-state error. 10.3.8 Sensitivity of the Closed-Loop Poles Due to Load Variations The load resistance was changed in MATLAB simulations to test the sensitiv- ity of the closed-loop poles of the discrete-time model due to load variations. output voltage HVour) Os 0\5tns 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms ..HVou,) --1W -33 Tme Figure 10.34 Parametric simulation with different loading. Switching Converter Design: Case Studies 471 r . VJ/J Time (msec) Figure 10.35 Inductor current for different loading. 1.2 A 0s 1 ■V(V„J . 3.3 Figure 10.36 Transient response due to a load change at time = 5 msec. The feedback gains were calculated to set the closed-loop poles at: poles= {0.7615 ± y0.1813, 0.7340} for a nominal load resistance of 4ft. Without changing the feedback gains, the load was varied and the poles were recalculated. Figure 10.37 displays the pole locations for a load variation 472 Power-Switching Converters 8 10 12 Load resistance 14 16 18 20 x Orignal comple x pole 1 : O Original comple x pole 2 + Original real pole Figure 10.37 Closed-loop pole dependency versus load resistance. from 0.1 to 20 n. Notice that the system remains stable at a load resistance from 0.7 to 20 CI. For a load resistance smaller than 0.7 CI, one of the poles moves outside the unit circle. At this load value, the voltage-mode synchron- ous buck converter becomes unstable. For the nominal resistor value, the poles are located at {0.7615 ± jO.1813, 0.7340}. Finally, for a load resist- ance greater than 4 CI, the system is always stable and the pole locations do not change significantly. 10.3.9 Experimental Results The control algorithm was implemented in a Texas Instruments' TI320F240 DSP to drive the converter circuit. The internal PWM circuitry was set to emulate the external sawtooth and turn off the switch when the PWM counter reaches the value determined by v^. An internal timer was set to 100 us. The analog-to-digital converter (ADQ is activated for each period, during which the inductor current and the output voltage are sampled. The Switching Converter Design: Case Studies 473 Timer interrupt every 100 ps Switch ON Sample i L Sample v c additional dynamics: j/a(fc), xa(fc), ua(fc) Calculate new v re , Counter interrupt STW > v rel Switch OFF Figure 10.38 Block diagram of the algorithm implemented in the DSP. end of the conversion activates an ADC interrupt, where a new v ref value is calculated. The block diagrams of the interrupts are shown in Figure 10.38. Figure 10.39 displays the steady-state waveforms obtained under a nominal load condition. The trace on chl is the v ref used as the control variable, ch\ shows the inductor current, and cKi is the output voltage. Notice that the duty cycle is actually 72% and the switching period is fixed at 1 00 p.s. The transient response of the DSP-controlled synchronous buck converter under a small load variation is shown in Figure 1 0.40. It can be seen that when the load changes to a smaller resistance (i.e., 3.75 H), v ref adjusts the duty cycle to a new value, leading to a new steady-state duty cycle of nearly 90%. 1 0.4 DIGITAL CONTROL OF A CURRENT-MODE SYNCHRONOUS BUCK CONVERTER In Section 1 0.3, we discussed the design of a DSP-based voltage-mode synchro- nous buck converter. The same hardware is also used, without modifications, to implement a current-mode synchronous buck converter. This is accomplish- ed by changing the DSP software. This section discusses the design and experi- mental results obtained from the current-mode synchronous buck converter. 474 1 1.00V 2 500' Power-Switching Converters 50.0SI Av 12 RUN Vavg(1)=3.3363 V Period(2)=98.00us Figure 10.39 Steady-state response of the DSP-controlled VM synchronous buck converter. 1 1.00V 2 i.oov ; 40.08 5008/ Sngl J2 STOP iVk^>^Hu^)i^v'9v<r\'yw , cn^ vc ltM-j-ll-ll')+1-H(-j.|.|t>Hl-l-l+-l>-Htjl'l-l-llHH-l-jl-ll++(M-l vvwjwiMMM>vww\M A ' v r- i V1(1)=2.750V V2(1)=3.397V _Si_ AW(1)=646.9 mV Figure 10.40 Transient response of the DSP-controlled synchronous buck con- verter under load variation. 10.4.1 Continuous-Time State Model The continuous-time model for the synchronous buck converter is the same as in Equations (10.17) and (10.18). For an open loop converter, Switching Converter Design: Case Studies 475 *-[W?]- *-[!]■ (,0J9) 10.4.2 Obtaining the Discrete-Time Model The discrete-time model for the current-mode switching converter was cal- culated in Chapter 6 as *[(ii + l)rj = ®CMx[nT s ] + Toj p , (10.40) where the expression for the model components and their numerical values are: rcM-ro,3=[J;S], 0042, * = (#,- ft)17 = 5263.2, (10.44) T = e A{X - D)T >KT % = {! = [«, *> 2 ], 00-46) 0.50161 (1045) 0.1475 J' £4 = * = £ = _ 6 .3748, (10.47) Wl 0*, ? L (V d -V C )T S (0 2 = a4 = * = f_0_| = o.3385, (10.48) #4, * = J_ __L = 6 374g (10.49) 3 a/ P / p T s K d - K c 476 Power-Switching Converters 10.4.3 Current-Mode Instability The poles of the transition matrix in current-mode, <J> C m, were found from Equation (10.41) at {-2.3776, 0.7815}. Clearly, one pole lies outside the unit circle, predicting an unstable behavior for D = 0.72. The design technique used in this example permits the closed-loop poles to be located in any desired location, overcoming this problem. The practical limitation for choosing the closed-loop poles is that the control variable should not saturate. 1 0.4.4 Extended-State Model for a Tracking Regulator Additional dynamics, represented by 4> a , r a , L 2 , are added to yield a zero steady-state error. The extended-state model for a tracking regulator with additional dynamics implementing a digital tracking system that uses full- state feedback is given in Equation (10.50) d [r aC 4> ; :,]• Mo]- (10.50) where c relates the output to the states through y = ex; L 2 relates the output of the additional block to its states through y a = L 2 x a . x a is the state vector of the added dynamics. In this example, only one state is added. A regulator for (^d, T d ) can be designed and the vector of feedback gains can be partitioned as L = [L X L 2 ], (10.51) where L x consists of the first n elements of L, n being the order of the system to be controlled (for a synchronous buck converter n = 2). L 2 is the remain- der of L. L can be found by pole placement of the desired closed-loop poles of the regulator. The procedure to find (4> a , T a ) is covered in detail in Vaccaro [3], but for this case 4> a = T a = 1. The extended model for the current-mode synchronous buck converter becomes 4>d -2.3804 -0.0805 0.1099 0.7843 1 (10.52) r d = (10.53) Switching Converter Design: Case Studies 10.4.5 Feedback Gains The values for the elements of the feedback vector L were obtained by pole placement for an arbitrary desired transient response. The closed-loop poles were arbitrarily chosen to lie in the following locations of the Z plane: {-0.66, 0.66, 0.9} The resulting gain vector is: L = [-0.4709 O.1340 0.0183]. (10.54) 10.4.5.1 MATLAB Design File The MATLAB command file used to design the current-mode controller is: clear all Rs=0.8;%Ron RD = Rs; RL=1.34; R=4; L=1.3302e-3; cap=94.e-6; Ts=1.e-4; Vg = 7; Vref=3.3; Vd = 0.0; % diode voltage drop IM=Vref/R D = (Vref+Vd+IM*(RL+RD))/(Vg+Vd)% duty cycle with losses Vdrop = Vg-IM*(Rs+RL)-Vref deltal = (Vdrop*D*Ts)/L lvalle = IM-deltal/2 lpnom = IM+deltal/2; A=[-(Rs+RL)/L-1/L 1/cap -1/(R*cap)] fiA=expm(A*Ts) fiA; pol = eig(fiA) B1=[1/L 0] %during Ton B2 = [0 ];%during Toff Un = Vg; %input vector %discrete model K-(B1-B2)*Un fiB = expm(A*(1-D)* Ts)% transition matrix for GamaA GamaA=fiB*K*Ts 478 Power-Switching Converters %sensitivities fiD=expm(A*D*Ts); deltafiD = A*fiD; deltaGamaD = f iD*B1 ; x10 = IM-deltal/2; %lvalle nominal x20= Vref; %Vc nominal w1 = -fiD(1 , 1 )/( (deltaf iD(1 ,1 )*x1 0+deltafiD(1 ,2)*x20+deliaGamaD (1,:rUn)*Ts); w2 = -f iD(l ,2)/( (deltaf iD(1 ,1 )*x1 0+deltafiD(1 ,2)*x20+deltaGamaD (1,:rUn)*Ts); Omega = [w1 w2] %vector sensitivities % sensitivities alternative Omegaalt = [-L/(Vdrop*Ts) D/Vdrop 0] %w1 = -L/(Vdrop*Ts); %w2 = D/Vdrop; GamaB = (L/(Vdrop*Ts) )*GamaA % current mode f iCM = f iA+GamaA*Omega GamaCM = GamaB cCM = eye(2); dCM = zeros(2,1); pcm=eig(fiCM) % closed loop without compensator % complete state feedback % closed loop poles P = [-0.6626 0.8571' F = place(f iCM.GamaB, P) fiCL=fiCM-GamaB*F; pcl = eig(fiCL) % closed loop with compensator % compensator design fiComp = 1; GamaComp = 1 ; c = [01]; fiDesign = [fiCM[0 0]' GamaComp*c fiComp]; GamaDesign = [GamaCM 0]; P = [-0.6626 0.657 0.90]' % closed loop poles as tracking_regulator Ld = place(fiDesign,GamaDesign,P) f iCL = fiDesign-GamaDesign*l_d; pel = eig(fiCL) Switching Converter Design: Case Studies 479 10.4.6 Control Strategy The same control strategy used for the voltage-mode synchronous buck converter was used here, except that the control variable is the peak current flowing through the inductor J p . Like the others, this variable comprises of a steady-state term and a perturbation term. Then, we can write: /p = 7p + lp, < 10 - 55 > where I p is calculated at the beginning of the kth switching cycle as J P (k) = 7p(*) - Um + *(*), < 10 - 56 ) where y a {k) = L 2 x 3 (k), ( 10 - 57 > Xa {k) = * a x a (fc - 1) + T a u a (k), ( 1 °- 5 *) «.(*)= ^ -**(*). ( 10 - 59 > 10.4.7 Simulation Results Simulations were performed in SPICE to verify the design. The PSpice schematic of the test circuit is shown in Figure 10.41. Figure 10.42 displays the result of a load transient simulation where the load resistance was changed from 4 to 3.75 fl and back again to its original value. The smaller value of 3.75 O was selected because it is very close to make the switching converter unstable by driving one of the closed-loop poles outside the unit circle. The output voltage converges to the nominal voltage of 3.3 V due to the tracking effect included in the additional dynamics. Notice that no overshoot in die voltage waveform is present during the start-up. A feed- forward gain (empirically chosen as -0.1) was added to improve the start-up transient. Figure 10.42 also shows the inductor current waveforms corre- sponding to the two selected load resistors. The current reaches different steady-state values, according to the load resistance. The signal IJiold represents the samples of the inductor current taken at the turn on of the main switch. Notice that the waveforms repeat every 100 [is without any sub-harmonic oscillation. Also notice that the duty cycle for R = 4fl is 72%. In conclusion, the simulations show that the current-mode regulator is able to track the reference voltage while showing a stable behavior for a duty cycle greater than 50%. 480 Power-Switching Converters •J <D O i— EC (O 3 X> en 3 O c o o s -o o a -o o 9- a> Switching Converter Design: Case Studies 4.0- 481 0s 2 4 . VILHOLD) . M[|L) 6 8 10 Time (msec) 12 14 16 Figure 10.42 PSpice simulation of a load transient. 10.4.8 Sensitivity of the Closed-Loop Poles Due to Load Variations The load resistance was changed to test the sensitivity of the closed-loop poles due to load variations. The feedback gains were calculated to set the closed-loop poles at: {0.66, - 0.66, 0.9} for a nominal load resistance of 4 ft. The resulting feedback gains are: L = [-0.4709, 0.1340, 0.0183]. Then the load was changed and the poles were recalculated. Figure 10.43 displays the pole locations for a load resistance change from 0.1 to 20ft. Notice that the system remains stable at load resistances from 3.4 to 20 ft. For a load resistance smaller than 3.4 ft, one of the poles moves outside the unit circle. At this load resistance value, the synchronous buck converter be- comes unstable. For the nominal resistor value, the poles are located at {0.66, -0.66, 0.9}. Finally, for a load resistance value greater than 4 ft, the system is always stable. 10.4.9 Experimental Results The control algorithm was programmed into a Texas Instruments' TI320F240 DSP to drive the converter. An external' voltage comparator was used to trigger an external interrupt when the inductor current reaches the value determined by I p . An internal timer was set to 100 ]is. At each timer period, the ADC is activated, and the inductor current and the output 482 Power-Switching Converters 18 20 2 4 6 8 10 12 14 16 r- Originally at - 0.6; O Originally at 0.6; ■*■ Originally at 0.9 Figure 10.43 Magnitude of the closed-loop poles versus load resistance. voltage are sampled. The end of conversion activates an ADC interrupt, when a new J p value is calculated. The block diagrams of the interrupts are shown in Figure 10.44. Figure 10.45 displays the steady-state waveforms obtained under a nominal load condition. The trace on chl is the l p used as the control variable, chl shows the inductor current and cK> is the output voltage. Notice that the duty cycle is actually 72% and the switching period is fixed at 100 (is, without any suboscillations. This proves that the closed-loop System is stable as predicted. The transient response of the DSP-controlled synchronous buck con- verter under a small load perturbation is shown in Figure 10.46. It can be seen that when the load resistance changes to a smaller value (i.e., 3.75 £1), I p adjusts the duty cycle to a new value, leading to a new steady-state duty cycle of nearly 90%. Even under this condition, the converter remains stable. 10.4.10 DSP Program The complete listing of the main TMS320C-240 DSP program is shown below. After completing all the initializations, the main program goes into Switching Converter Design: Case Studies 483 Timer interrupt every 100 ms External interrupt i L > l p Switch ON Sample i L Sample v c additional dynamics: ya(K),xa(k), ua(fc) Calculate new l p Write lp to DAC Switch OFF Figure 10.44 Flow diagram of the interrupt routines. 1 500? 2 500? 3 1V -89.0S 50.0S / 12 STOP Freq(1)=9.804 kHz V^S)=326a V Figure 10.45 Steady-state waveforms of the current-mode synchronous buck converter. an infinite loop, waiting for the interrupts to occur. Once the external interrupt is triggered when the inductor current reaches the programmed peak value, the main switch is switched off. The second interrupt is activated by the internal timer at every switching period. The inductor current and the output voltage are sampled and the main switch is switched on. The control algorithm calculates the additional dynamics and the new value for the inductor's peak current is calculated. 484 1 500ip 2500'P 3 1V Power-Switching Converters r 6048 500SJ / SngU3 STOP ^^ ■ yp- 1. 1. 1. 1 | 1. 1- 1- 1 |. ,. ,. ,. ,. |. ,. ,. ,. v \ y V t t+ » > i » fa I I I J I I I I | I 1 • * \ Freq(1) not found V avg (3)=3.173V Figure 10.46 Transient response of the current-mode synchronous buck con- verter under a load step. #include "Perip240.h" #include "Inter240.h" #include "Reg_C.h" /* constants 7 r *ADC gains: * ch2(pin 5) for IL and ch1 0(pin 1 3) for Vc lanalog A 1A Vanalog 5V ADC hexa ADC dec Amplifier output 0x3FF 1023 5V 412 2.187V lanalogMax = 620mA ADC hexa ADC dec Amplifier output 0x1FB 507 */ #define ADCgain (2.075/418) /* ADC gain (DAC_input_volt age/ADC_count) */ Switching Converter Design; Case Studies 485 #define Ki_F #define Kv_F #define DAC_1v25 0x03FF #define DAC_2v5 0x07FF #define DAC_3v75 OxOBFF #define DAC_GAIN _F (1023/1.25) (1 .0/412) I* 0.43/0x2B3 multiply DAC reading by Ki to obtain the current value */ (5.0/0x1 FB) /'multiply DAC reading by Kv to obtain the voltage value */ r DAC value for-1 .25 V output */ /* DAC value for 2.5 V output */ r DAC value for 1 .25 V output */ #define 12 DACF (2.187* 1023/1.25) r new dac value = DAC_GAIN * volts */ I* 1789.84 counts/Amp used to generate Ip on the DAC */ /* floating-point parameters */ #defineRs_F 1.34 #defineL_F 1330.2e-6 #define CAP_F 94e-6 #define R_F 4.0 #defineTs_F 100e-6 #defmeVg_F 7.0 #define VREF_F 3.3 /* feedback gains */ #define L1_F -0.4709 #defineL2_F 0.1340 #defineL3_F 0.0183 #define GF_F -0.01 /* global variable definition */ int leds; int Isense_q12; int Vsense_q12; intVREF_q12; unsigned int Ip_q12 = 0; unsigned int lpnom_q1 2; unsigned int Imean_q12 = 0; unsigned int Ivalle_q12 = 0; unsigned int Vc_q1 2 = 0; unsigned int Isense = 0; unsigned int Vsense = 0; int L1_q15,L2_q15,L3_q15,GF_q15; 486 Power-Switching Converters int ua_q12 = 0; intxa_q12 = 0; intya_q12 = 0; intKi_q15,Kv_q15; int DAC_GAIN_q4; ioport int portOC; /* leds */ unsigned int dac_value; int !2DAC_q3; /* function prototypes 7 extern void meminit(void); interrupt void INT1_isr(void); interrupt void ADC_isr(void); main() { float lmean_F= VREF_F/R_F; float Vdrop_F = (Vg_F-lmean_ F*1.94)- VREF_F; /* inductor voltage drop 7 float D_F = (VREF_F+lmean_F*1 .94)/(Vg_F); float deltal_F = (Vdrop_F*D_F*Ts_F)/L_F; float lpnom_F= lmean_F+deltal_F/2; meminitO; /* initialize routine in ASM */ I* initialize variables */ I* Q-15 parameters range (-1,1) */ /* to convert to Q15: Z(Q155) = (int)(2*15*Z(Q0)) 2*15 = 0x80007 L1_q15= (int)(0x8000*L1_F); L2_q15= (int)(0x8000*L2_F); L3_q15= (int)(0x8000*L3_F); GF_q15= (int)(0x8000*GF_F); Ki_q15= (int)(0x8000*Ki_F); Kv_q15= (int)(0x8000*Kv_F); r Q-14 parameters range (-2,2) */ r to convert to Q1 4: Z(Q1 4) = (int)(2^1 4*Z(Q0) ) 2^1 4 = 0x4000V r Q-13 parameters range (-4,4) 7 r to convert to Q1 3: Z(Q1 3) = (int)( (2^1 3)*Z(Q0) ) 2*1 3 = 0x20007 /* Q-12 parameters range (-8,8) 7 /* to convert to Q1 2: Z(Q1 2) = (int)( (2*1 2)*Z(Q0) ) 2*1 2 = Ox 1 0007 VREF_q1 2 = (int)(0x 1 000*VREF_F); /* reference voltage 7 lpnom_q1 2 = (int)(0x 1 000*lpnom_F); Ivalle_q12= (int)(0x1000*(lmean_F-(deltal_F/2) )); /* Q-6 parameters range (-512,512) 7 Switching Converter Design: Case Studies 487 r to convert to Q6: Z(Q6) = (int)( (2*6)*Z(Q0) ) 2*6 = 0x407 I* Q-4 parameters range () 7 r to convert to Q4: Z(Q4) = (int)( (2M)*Z(Q0) ) 2M = 0x107 DAC_GAIN_q4=(int)(0x010 * DAC_GAIN_F) ; /* Q-3 parameters range () */ /* toconvert to Q4: Z(Q3) = (int)( (2*3)*Z(Q0) ) 2*3 = 0x08*/ l2DAC_q3 = (int)(0x08 * I2DAC_F); /* large numbers */ r initialize clock and wa'rt states */ *CKCR1 = OxOOBB; /* CLKIN (OSC) = 1 MHz, CPUCLK = 20 MHz*/ *CKCR0 = 0x00C3; /* CLKMD = PLL Enable, SYSCLK = CPUCLK/2 */ *SYSCR = 0x40C0; /* CLKOUT = CPUCLK */ WSGR = 0x0004; /* set wait state generator for: Program space: wait states, Data space: wait states, I/O space: 1 wait state */ /* initialize interrupts 7 *XINTA1CR =XINT1_value; /* set XINT1 */ *IFR = CLEAR_ALL_INT; /* clear flags 7 *IMR = INT_6 | INT_1 ; /* unmask ADC int and external int*/ asm("clrc INTM"); /*Enable unmasked interrupts.*/ r setup ADC for timerl driven interrupt 7 *ADCTRL1 = ADCTRL1_VALUE; /* ch2(pin 5) for IL and ch10(pin 13)forVc7 *ADCTRL2 = ADCTRL2_VALUE; r empty ADC FIFO 7 lsense = *ADCFIF01; lsense = *ADCFIF01; lsense=*ADCFIF02; lsense = *ADCFIF02; /* setup EV timer 7 *T1 CON = T1 CONVALUE; *GPTCON = GPTCON_VALUE; *T1 PR = 0x07D0; I* timer 1 period register 1 00 us for 1 kHz*/ *T1 CNT = 0x0000; /* timer 1 counter register 7 /* T1CMPR 7 /* timer 1 compare register 7 I* setup portB 7 *OCRB = OxOOOC; /* portB is I/O 7 *PBDATDIR = OxFFOO; /* portB is output FF, all outputs low 00 7 488 Power-Switching Converters I* main loop 7 leds = 32; portOC = leds; DAC0 = (int)(DAC_GAIN_F*2.0);/* set dac out to 3 V) 7 DACupdate = UPDATE; *PBDATDIR = OxFFFF;r switch ON 7 for (;;) /* infinite loop */ { r wait until IL>lp this is tested by an external comparator that sets the INT1 7 } r end for 7 }/* end main 7 FUNCTIONS interrupt void INT1_isr(void) f external interrupt for IL > Ip 7 { *PBDATDIR = OxFFOO;/* switch OFF 7 } interrupt void ADC_isr(void) { r switch on 7 *PBDATDIR = OxFFFF; r read ADC 7 lsense=7ADCFIF01; Isense = lsens»6; /* shift 10-bit ADC data to low byte 7 Isense_q12 = (int)( ( (long)(lsense) * (long)(Ki_q15) )«(32-15-10 +6)/* q127 ) »(16) ); /* scale input to represent Amps 7 Vsense = 7ADCFIF02; Vsense = Vsense»6; Vsense_q1 2 = (int)( ( l (long)(Vsense) * (long)(Kv_q15) |i )«(32-1 5- 1 0+6) I* q1 2 7 I; > »(i6> I ); /* scale input to represent Volts 7 Switching Converter Design: Case Studies 489 I* calculate additional dynamics */ xa_q1 2 = xa_q1 2+ua_q1 2; ua_q1 2 = VREF_q1 2-Vsense_q1 2; ya_q12=(int)((((long)(L3_q15)* (long)(xa_q12))«1)»16); I* calculate Ip */ Ip_q12= lpnom_q12 + ya_q12 -(int)( ( ( (long)(L1_q15r (long)(lsense_q12-lvalle_q12) )«1 ) -<int)( ( ( (long)(L2_q1 5)* (long)(Vsense_q1 2-VREF_q1 2) )«1 ) »m16) +(int)((((long)(GF_q15r(long)(VREF_q12))«1)»16); /* set DAC with new Ip value */ dac_value=(int)( ( (long)(lp_q12) * (long)(l2DAC_q3) )«(32-16-15) ) »(16) ); r scale input to represent Volts 7 DACO =dac_value; DACupdate = UPDATE; } 10.5 UC3842-BASED FLYBACK DESIGN A universal input voltage power supply was designed using a current-mode discontinuous-conduction-mode, flyback converter, based on the UC3842 PWM controller [4]. The controller was previously discussed in Chapter 5 and the flyback topology was discussed in Chapter 4. Current-mode control has the advantage that an excellent line regulation can be achieved without considering the dynamic range of the error amplifier. Therefore, the error amplifier is dedicated to correcting for load variations. The current-mode discontinuous-conduction-mode operation was selected because the flyback converter behaves as a first-order system with a left-half-plane zero. The right-half-plane zero, present in the continuous-conduction mode, which contributes to a nonminimal phase response, is shifted to high frequencies in current-mode discontinuous-conduction-mode. Therefore, the current- mode discontinuous-conduction-mode flyback converter is easier to control. The main drawback of this configuration is that the switches are subject to higher stresses than those of an equivalent continuous-conduction mode flyback converter (Figure 10.47). 490 Power-Switching Converters PARAMETERS: TF = 2n -±- PW = 5-Su -0 PER = 20u Figure 10.47 Open-loop schematic diagram of the flyback converter. 10.5.1 Design Specifications The universal power supply should accept any standard AC input voltage between a minimum of K ACm in = 85K ac and a maximum of ^AQ»« = 265K ac . The input frequency may be either 50 or 60 Hz. The output voltage should be within 5V±5%. The normal load current is 750 mA, but a maximum current of 1 A is considered for the design. The switching frequency should be selected as 50 kHz. The flyback transformer has-a primary of 89 turns with an inductance, Lp, of 1 .9 mH. The secondary winding has four turns and the bias winding has 12 turns. The input EMI filter should be designed to provide a stable converter behavior. 10.5.2 Discontinuous Conduction Mode The voltage conversion ratio can be calculated by evaluating the volt-second balance on the transformer coils. During the interval 0<t<t on , current flows through the primary inductor, L p . The voltage across L p ideally is equal to V d . During the interval t m <t<t2, current flows through the secondary in- ductor, L s . The voltage across L s , ideally equal to V m is reflected to the primary by the transformer ratio, so Switching Converter Design: Case Studies 491 The current through the primary inductor reaches its maximum value, 7 !pk at on Kd = Lp V (10.61) to ■on The average primary current, /i a v g > is _fon/lpk (10.62) ■«Iavg — ~™ • When the primary transistor turns off at t on , the current in the primary inductor drops down to zero instantaneously and the energy is transferred to the secondary inductor. The current of the secondary inductor starts from the peak value, / 2p k, and decreases in amplitude until all the energy stored in the magnetic field is released to the load at t = t 2 . From this point up to the end of the switching period, the current on both inductors are zero. The peak value of the secondary current is i r N v (10.63) The average value of the. secondary current is equal to the average load current, then i - & ~ f °"> ^p 7 'P k (10.64) T N s 2 ' The ideal average output voltage is j, r n p 7 'pk (10.65) °~ s N s (t 2 - ton y The on-time can be calculated from Equation (10.61) as , _ T ^ipk (10.66) /on - H y d and the off-time can be calculated from Equation (10.64) as (t,-t ->-2r ^ ( 1067 > 492 Power-Switching Converters Substituting Equations (10.66) and (10.67) into Equation (10.60), we obtain an expression for the peak value of the primary current 7 "* = /^" (1068) According to Equation (10.68), the peak current on the primary winding is inversely proportional to the primary inductance and the switching fre- quency. An expression for the voltage conversion ratio can be obtained by replacing Equation (10.68) into Equation (10.61) 2° = D flE. (10.69) v d Y 2 V Therefore, the nominal duty cycle is n^Kl.l^L (10.70) V d V TR- 10.5.3 Preliminary Calculations Preliminary calculations can be performed to estimate the peak current and the duty cycle in the circuit without losses. From Equation (10.68), the peak current flowing through the primary inductor is /2(K +K f )/ o r _ /2 . „-„- /2(5 + 0.7)x 1 x20x 1Q- 6 /,pk = ^"l" = V 1.9 x 10- 3 = 0.346 A. ( 10 - 71 > Since the diode voltage drop is significant in comparison with the output voltage, the voltage drop across the output diode was added in Equation (10.71) to obtain a more accurate result. Using this value for 7ip k , , on = L p ^= 1.9x10-^ = 5.48^ (10.72) and the duty cycle is D '» = ^ = 0.274. (10-73) T 20 Switching Converter Design: Case Studies 493 The inductances of the secondary and bias windings of the transformer can be calculated from the design specifications as r = —h— = 19m ** = 4.2076M.H (10.74) and Lh = ** = K9mH , = 37.869 f,H b (N v /N b ) 2 (85/12) 2 (10.75) 10.5.4 Open-Loop Simulations Open-loop PSpice simulations were performed to estimate the required duty cycle to maintain the nominal output voltage, V„ = 5 V, when the component losses were included. Figure 1 0.48 demonstrates that the switch has to be on for a longer time to compensate for the modeled circuit losses, i.e., t =59^, compared with 5.48 \xs obtained previously without considering losses. With this duty cycle, D = 29.5%, the average output voltage is close to 5 V and the voltage ripple, AK , is less than 15mV. 9.960 '(Oil) 9.965 9.970 9-975 Time (msec) 9.980 9.985 Figure 10.48 Simulated waveforms for the open-loop flyback converter. 494 Power-Switching Converters In this simulation, the output capacitor's ESR was neglected. If it was considered, the output voltage would have been affected by a larger voltage ripple. The current on the primary side of the flyback transformer increases linearly during t on until it reaches its peak value, 7, pk = 0.376A. When the switching transistor is switched off, current starts to flow on the secondary winding and the primary current goes down to zero. The energy stored in the magnetic field is transferred to the load while the secondary current de- creases. When the secondary current reaches zero, all the energy stored in the magnetic field has been released and the load current is provided solely by the output capacitor. The output capacitor is charged only when the sec- ondary current is higher than the load current. This explains the output ripple voltage waveform. This simulation also shows that the flyback converter operates in the discontinuous-conduction mode even under the worst-case condition, i.e., during smallest input voltage and largest output current. The secondary current becomes zero before the end of the switching period. 10.5.5 Current Loop The internal current loop produces the current-mode control. For current- mode control, the duty cycle is controlled by the peak current of the primary inductor, according to D = I^-^. (10.76) Therefore, by changing I lpk , the output voltage can be controlled: Ko = /,p k ^p. (10-77) 10.5.6 Voltage Loop The external voltage loop transforms the current-mode controller into a voltage regulator. The error amplifier of the UC3842 calculates the neces- sary primary peak current as /com = {[V ref + {V ta A 1 - VtAiA - 1.4 V}^ (10.78) or /co nt = KEAO : L4K . (10-79) Switching Converter Design: Case Studies 4 ^ This value is saturated at IV by having the Zener diode connected at the inverting input of the comparator. 10.5.6. 1 Current-Sensing Resistor and Filtering The current-sensing resistor, J^e, was calculated for the worst-case condition that would generate the maximumauty cycle. This condition occurs when the minimum input voltage, V, = 85 K ac , and the maximum output cur- rent, 7 =1A, are met simultaneously. The current-sensing resistor is calculated so that the maximum dynamic range of the PWM modulator is used . For the worst-case condition, the voltage across /{sense should be 1 V. Hence R --^- = 2 7fl (10.80) The previous value was obtained based on 100% efficiency. A more realistic value can be obtained by estimating the typical efficiency of a flyback converter at 75%. Therefore, the input current would be 43% larger than the ideal value. Thus n 1V -I9n (10.81) Rx ™- 1.43(0.36 A) _1V The maximum average input current /a max is /dn,a*= V ° Ioma% = 5VxlA «60mA. (10.82) idmax 07K . m . n 0.7 X 120V Consequently, the maximum average power dissipated in the current-sensing resistor is A = 4„ax* S ens e = 6.84mW. (10-83) A noninductive metallic resistor of 1/4 W is chosen as the current-sensing resistor. There is a fast transient at the turn on of the switching transistor due to the rectifier recovery and the interwinding capacitance of the flyback transformer. The amplitude of this spike may be larger than 7i pk and it has to be filtered, otherwise it may prematurely terminate the conduction of the switching tran- sistor. A simple R-C filter is usually sufficient to attenuate this spike. The time constant of the filter is calculated to be equaUhe duration of the spike. R was chosen to be 1 kfi and C was calculated to be 470 pF for a time constant RC= 470 ns. Figure 10.49 shows the waveforms corresponding to the current flowing through the primary inductor, the voltage across the current-sensing 496 Power-Switching Converters 400 mA 200 mA ^SENSED) 9.97200 9 Time (msec) 9.98400 9.98786 Figure 10.49 Conditioning the current sample. resistor and the same voltage after passing through the low-pass filter to attenuate the spike. Originally, the spike was larger than the peak current. After passing through the RC filter, the spike has been completely removed. 10.5.6.2 Dissipative Snubber A dissipative snubber, shown in Figure 10.50, is usually connected across the primary winding to alleviate the voltage stress of the switching transistor. When the transistor turns off, the primary inductor produces an inductive kick that increases the voltage at the drain of the transistor above the DC bus voltage level. When this happens, D 14 is forward-biased and charges C 2 through R y , transferring the energy from the inductive kick to the capacitor. The inductive effect disappears when the diode connected to the secondary winding becomes forward bias. The energy stored in C 2 is dissi- pated into ft, during 1^. The time constant Rj-Ci should be smaller than the time taken by the output rectifier to achieve full conduction. The time constant R4-C2 should be smaller than f ofr . The values of C 2 and R n should be adjusted by parametric transient simulations to yield an acceptable tran- sient on the drain of the transistor. The final values for these components are R 7 = 100 ft and C 2 = 1000 pF. 10.5.6.3 The Error Amplifier The schematic diagram of the error amplifier is shown in Figure 10.51 and the voltage conversion ratio is shown in Figure 10.52. The error amp- Switching Converter Design: Case Studies 497 PARAMETERS: Rsn = 100 Csn = 1000p Lq = 10u IRF830'n Figure 10.50 Dissipative smibber. Figure 1 0.51 Schematic diagram of the error amplifier. lifier output, EAO, reaches 1 V when the feedback voltage V f = 12.8 V and it decreases linearly to V for V f = 13.4 V. Therefore, V f has to be constrained between these two values to achieve full regulation. EAO is the control voltage that determines the peak value of the primary current and the duty cycle. This voltage must be equal to IV for K„=120V and / D =1A to generate the necessary duty cycle to regulate the output voltage to 5 V. 10.5.6.4 The Bias Circuit The UC3842 is initially powered from the input mains through a resistor divider. After a few switching cycles, the output voltage builds up and charges the bias capacitor C 4 , which continues supplying the power to 498 Power-Switching Converters 0.200 V V(EAO) 13.1 V_V,(V) Figure 1 0.52 Voltage conversion ratio of the error amplifier. the controller. The schematic diagram for the bias circuit is shown in Figure 10.53. The resistors in parallel with the diodes are used to improve conver- gence in the simulations. A zener diode, modeled with a DC voltage source, is connected in series with the bias winding to reduce the voltage to within the operating range of the controller. This was necessary because the avail- able transformer had a larger bias voltage than is needed. 10.5.7 Small Signal Model The current-mode flyback converter operating in the discontinuous-conduc- tion-mode behaves as a first-order system. The first-order pole is located at /„ = — — = - z = 64 Hz (10.84) Jp ttRC tt x 5 x 1000 x 10~ 6 *Vioo* fl 10 100/r Bias JTL-IH 100U Dbreak IFL ±a "\2k Dbreak Zener diode 1.9 V 4|lf ™*T 47u Controller load 1.9 "l3 ^2 ■ -WV g^ 1m r&J Pi ft "is J Wv- pi ■ « — T/VV 1 Jl COUPLING = -1 100 Me 9 4r ~0 L1_VALUE = 1.9m ~t L2_VALUE = 37.869 U Figure 10.53 Bias circuit. Switching Converter Design: Case Studies 499 and the left-half-plane zero is located at fz 2esr 2-irResrCo 2ir x 0.1 x 1000 x 1Q- 6 = 1592 Hz. (10.85) There is a right-half-plane zero, but it is located at high frequencies and can be neglected. The component Flyback_current-mode [5] (see Figure 10.54) is based on the averaged inductor model [6] and is used to perform PSpice simulations. The control voltage comprises of a DC value, which sets the operating point, and an AC value that yields the small-signal variations. 10.5.8 Frequency Compensation The frequency compensation was calculated based on small-signal PSpice simulations. The small-signal model, based on Ref. [5], used to measure the loop response, is shown in Figure 10.54. The transformer ratio is equal to N 2 /N l . The small-signal gain from the output to the bias voltage was obtained as the incremental gain for two different output voltages, as AK b ,as 13.097 - 13.020 _ fifrl? V AV„ 5.1253-5.0094 " V (10.86) 120 V t i U s FLYBACKCM -OOT1 FLYBACKCM MC=1 => no slope compensation Rr = current s '— *" . m GOT tCOMTROI BNDl "e 2 BP.V. JUL L=1.9m FS = 50* XFMR1 RATIO = 47.059 m ^ & 1Meg *0 0.1 1000 uF "T" 700p ioo)fJ 5m # 5^ T0.47UF ACMAG = 1 DC=0 -^-<F V ~ Figure 10.54 Small-signal model used to measure the loop gain. 500 Power-Switching Converters The transfer function of the proportional compensation network is TF = — * I— . R i6 //R llS C 2 R 2 +l Thus, the frequency of the pole of the compensation network is 1 /p = 2irR 2 C 2 (10.87) (10.88) Choosing / p to cancel the zero of the transfer function of the flyback converter, C 2 can be calculated as 1 1 C 2 = 2ifR 2 f v 2ir x 150& x \.5k = 700pF. (10.89) An AC analysis was performed to obtain the Bode plot of the loop gain shown in Figure 10.55. As shown, the magnitude of the loop gain decreases at -20 dB/dec after the pole frequency. The zero was cancelled by the pole of the compensation network and the best phase margin that can be obtained (with this compensation network) is 90°. The dB crossover frequency is 12.3 kHz, which is close to one fifth of the switching frequency. 10.5.8. 1 Closed-Loop Simulations Transient simulations were performed using the schematic circuit shown in Figure 10.56 to verify the design. Figure 10.57 shows the start-up transient 1.0 mHz lOmHz 100 mHz 1.0 Hz .P(V(VF)). -180 ^Hz 100Hz 1.0 KHz 10 KHz lOOKHz 1.0MHz Frequency Figure 10.55 Bode plot of the loop gain. Switching Converter Design: Case Studies 501 PARAMETERS: AC = 85 ii (Lq) _/y?m_ PARAMETERS: Rsn=100 Csn=1000p Lq=10u R, II (Vt%IN2)>H%IN1)A0 Figure 10.56 Closed-loop converter schematic for transient analysis. — , 10V- 5V- /^ ____ ov-l - V{>*°*) 1 1.0 V- \ \r- o.sv- ov- . V(CONTROL) 5.0 4.0 3.0 2.0 SEL» /^ )s 1.0 ms .V(OUT+,OUT-).5 1 2.0 ms 3.0 ms Time 4.0 ms 5.0 ms 6.0 m 5 Figure 1 0.57 Transient response with the calculated frequency compensation. 502 Power-Switching Converters of the flyback converter using the calculated compensation. The control voltage saturates at the beginning and then decreases to the calculated nominal value. The output voltage shows the response of a first-order system and finally settles to 5 V. Note that the bias voltage is within the calculated range. Figure 10.58 displays the transient response of the closed-loop flyback converter due to a load change. The load initially started at 10 A, and at 10 ms, the load was changed to 5 ft. For a 10-ft load resistor, the output voltage is 5.13 V. A steady-state error was expected due to the use of the proportional control. For the 5-ft load, the steady-state error goes to zero because this was the nominal load value used for the calculations. Never- theless, the regulation is within the specified 5%. 10.5.9 EMI Filter Design The EMI filter should prevent conducted EMI originated at the switching converter to reach the AC mains (Figure 10.59). The EMI filter was calcu- lated according to the guidelines given in Chapter 6. Therefore, the cutoff frequency of the filter was chosen to be at least one decade below the switching frequency and the output impedance of the EMI filter was designed to be much smaller than the input impedance of the closed-loop flyback converter. PSpice simulations based on the small signal model of the flyback converter were used to improve the design and verify its per- formance. Figure 10.60 shows the output impedance of the EMI filter, calculated using a corner frequency f c = 2.5 kHz. 13.45 V- 13.25 V- 13.00V • SEl» 4.5 l V. ' V(bias) V(CONTBOL) £ 513 V \ B=10 :777>w 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms • V(OUT+,OUT-) • 5 Figure 10.58 Transient response to a load step at 10 ms. Switching Converter Design: Case Studies 503 OVJZJVi 10m '100n 10m -^WV 3.5 I0K1 K_Linear COUPLING = 1 L1 = L1 L2 = L2 tout 10m 10u 1 A a 0A, l -oil. - J VW 3.5 Figure 10.59 EMI filter. -40 1.0 mHz 10mHz * DB(VtFOUT)) 100 Hz 1.0 kHz 10 kHz 100 kHz 1.0 MHz Frequency • Figure 10.60 Output impedance of the EMI filter. The PSpice small-signal model for the flyback converter, including the EMI filter is shown in Figure 10.61 and the simulation results of an AC analysis are displayed in Figure 10.62. These figures show that the cutoff 504 Power-Switching Converters ACMAG = DC =175 °<$> V - -Wk— 3.5 ft* HK1 K_Linear COUPLING =' L1=L1 L2 = L2 li o, 4=^ 10u * ft 10 m 170 V ■flfc- U5FLYBACKC M lcc*rrROL GNCI — MC=1 i©<4 fll = 1.9 t=1.9m FS = 50» MC=1 => no slope compensation Ri = current sense resistor U5 FLYBACKCM NDt Figure 10.61 Small-signal model used to measure the impedances. frequency of the filter is 2.2 kHz and that the output impedance of the EMI filter is much smaller than the input impedance of the flyback converter, as desired. Thus, the presence of the EMI filter should not compromise the stability of the flyback converter. 10.5.10 Printed Circuit Board Design Figure 10.63 shows the printed circuit board layout of the universal power supply. The bottom layer is displayed on the left and the top layer on the right. The top layer is used only for the ground plane. The plane is divided into two current paths. The left portion carries high switching currents, while the right portion carries low-level currents used for control signals. The ground plane does not reach the bottom part of the board to avoid interaction with the input AC voltage. The MOSFET is surrounded by the Switching Converter Design: Case Studies 505 Z, Flyback Z„ EMI liRer -foISS SS ^O^z S ^S WK 1.0*Hz 10kHz 100 kHz 1.0 MHZ => DB(1/I(V3)).DB(1/I(V4» Frequency Figure 10.62 Output impedance of the EMI filter and input impedance of the flyback converter. ® © @ @ ® O 9 o eo Figure 1 0.63 PCB layout of the universal power supply. 506 Power-Switching Converters ground plane that acts as a short-circuited coil to attenuate the radiation of noise to other circuit components. The bottom layer carries the rest of the connections, which are not tied to ground. The tracks are as short and wide as possible. The components are laid out in such a way that interaction between sensitive signals (e.g., control signals) and noisy signals (e.g., high voltage, high current, fast transients) are minimized. The output circuitry is located in the top portion of the board. The middle sector is reserved for the control and components of the primary side of the converter. The AC input, EMI filter, and the voltage rectifier are placed at the bottom of the board. The silk screen is shown in Figure 10.64 and a photograph of the prototype of the universal power supply is shown in Figure 10.65. 10.5.11 Experimental Results The primary current (as measured at the sensing resistor) and drain voltage waveforms of the flyback converter are shown in Figure 10.66. When the MOSFET is switched on, the current flowing through the primary inductor increases linearly until it reaches the peak value set by the controller. When the MOSFET is switched off, the current decreases rapidly to zero, transferring the conduction to the secondary winding. The drain voltage increases to a R4 *> ir ■* o o o s LIJ J2 O z 1 o CM Ul — FUSE O Figure 10.64 Silk screen of the PCB of the universal power supply. Switching Converter Design: Case Studies 507 Figure 1 0.65 Photo of the universal power supply. rm i U I 1 1 1 1 1 1 1 1 1 1 ■ 1 1 1 1 "- TI'IMT TTTTTTTTt H-- 1 ..... UL4 Primary current -:\A -U i^Jr • i 4\ ~~J r 1 * i - ■ > 1 f .1 J 1 ■ ■ if ■ » i i ■ i ■ 1 1 »■ ■ • i L.. _._■.. t 1 1 • 1 t 1 1 1 1 i ■ ■■*■■■ » \ / 1"" 2-J Drain voltage ■ i ■ i ■ ■ ■ i ■ ■ ■ ■ CH1 100 mV CH2 50.0 V M 2.50 jjs Figure 10.66 Primary current and drain voltage waveforms of the flyback converter. voltage larger than the input DC voltage. When all the energy stored in the magnetic field has been transferred to the output, the conduction on the secondary side ceases and an oscillatory drain voltage can be seen. Notice 508 Power-Switching Converters the large spike present on the current waveform at turn-on . This transient must be filtered using a low-pass filter before feeding to the PWM modulator. The measured output voltage ripple, with an amplitude of 146mV pp , is shown in Figure 10.67. The output voltage ripple may be reduced by re- placing the output capacitor adth an LC low-pass filter or by using an output capacitor with a lower ESR. The output voltage and current waveforms of the flyback converter during a load transient are shown in Figure 10.68. The load resistance was reduced from 10 to 5 ft. As can be seen, the output voltage drops to 150mV (which is a 3% variation from the nominal voltage) before recovering to its steady-state value after 300 ns. 10.6 TOPSWITCH-BASED FLYBACK DESIGN A universal input voltage power supply was designed using a current-mode discontinuous-conduction-mode flyback converter, based on the TopSwitch PWM controller [7]. The controller was previously discussed in Chapter 5 and the flyback topology in Chapter 4. This controller has a unique current- mode control scheme using variable switching frequency that skips pulses, when necessary, to achieve regulation. In contrast to the UC3842-based flyback design, which uses -a- primary-side regulation scheme (as shown in Section 10.5), this design uses a secondary-side regulation scheme. This means that the output voltage on the secondary side of the power trans- former is sensed and fed back to the controller through an opto-coupler. 1*: i i i i . i 1 1 i . i i i i ■ i i i i . i i i i i i i i i . i i i i ; i i ' ■ * i 1 1 1 ' t iii i j Output voltage ripple CH1 50.0 mV M 2.50 us Figure 1 0.67 Output voltage ripple of the flyback converter. Switching Converter Design: Case Studies 509 : i • : : : I I Output voltage -4 i- { j 4 1 » :-,ju.-L*. | Output current "> •> j j 1 1- CH1 200 mV CH2 2.00 V M 1 00 ns Figure 1 0.68 Output voltage ripple and current of the flyback converter during a load transient. This type of regulation scheme usually achieves a better regulation than that of the primary-side regulation. 10.6.1 Design Specifications The universal power supply should accept any standard AC input voltage between a minimum of K ACmi „ = 85 K ac and a maximum of V ACmm = 265V ac . The input frequency may be either 50 or 60 Hz. The output voltage should be within 5V ± 5%. The output power is 20 W. The nominal switching frequency is 135 kHz. The flyback transformer has 36 turns with a primary inductance of 490 u.H. The secondary winding has four turns and the bias winding has five turns. The input EMI filter should provide a stable converter behavior. A design efficiency of 17 = 0.8 is adopted. The estimated loss allocation factor, Z=0.5, assigns an even distribution of the losses between the primary and the secondary sides of the converter. 10.6.2 Preliminary Calculations As shown below, the flyback converter operates in the discontinuous- conduction mode; therefore, the design parameters will be evaluated using the discontinuous-conduction mode equations. The output voltage reflected back to the primary winding can be estimated as K or = 135 V; therefore, the clamping voltage of the zener diode is chosen to be 200 V. The maximum duty cycle can be estimated as 570 Power-Switching Converters n, = XsL = — — = 0.63, (10.90) "'" K^V^-V^+V^ 1(90- 10)+ 135 where V ds = 10 V for the TopSwitch. The primary peak current is /„= ^2 = 2x20 = 0.88 A. (10.91) P D^-nVniB 0.63 x 0.8 x 90 Thus, the primary RMS current is /rms= \f> m Jj = ^63^= 0.4 A. (10.92) The calculated primary inductance is similar to the primary inductance of the transformer 10 6 J> o Zjl-rfi + t, ^ /j>0.5/ smin v _ 10 6 x 20 0.5(1- 0.8) +y (10.93) _ (0.88 2 )(0.5)( 130000) 0.8 = 447nH. The secondary RMS current is /rms = h v ^^ = /sp/^ = 4-7 A, (10.94) where A" p is the primary current waveform parameter. It is equal to one for discontinuous mode. Figure 10.69 shows the schematic diagram of the universal power supply implemented using the TopSwitch controller. The EMI filter, Cxi - LI, attenuates conducted EMI from the converter from going to the mains. The voltage-clamping circuit, D x - D 6 , prevents the drain voltage on pin 7 of the controller to overshoot above K DC + V A + V T . The second- ary-side regulation is achieved by sensing the output voltage through the opto-coupler. The bias winding provides the supply power to the controller. The output voltage may be changed by adjusting the variable resistor, V R , which sets the voltage on the shunt voltage regulator, TL431 . 10.6.3 Experimental Results A prototype was built following the instructions provided in the data sheets. Switching Converter Design: Case Studies 511 c.k", v ° Figure 10.69 Universal power supply implemented with the TopSwitch. I 'l.J.J-M.U.U.2.!.fi.i-!- ' .AJ-t- CH1 5.00V M 2-50 ps Figure 10.70 Drain voltage waveform of the TopSwitch-based converter. Figure 10.70 shows the measured drain voltage waveform using a lOx voltage probe. This is the typical waveform of a flyback converter. The average value is 158 V and the overshoot is approximately 100 V. The switching frequency was measured to be at 133 kHz. The frequency of the output voltage ripple, shown in Figure 10.71, was measured to be 135.2 kHz, in good agreement with the design. The measured amplitude of output voltage ripple was 112mV pp . It should be noted that the output capacitor is charged during the off-time of the switching transistor. 512 Power-Switching Converters Output voltage ripple 144 1 M-l CH1 50.0 mV M 2.50 us Figure 10.71 Output voltage ripple of the TopSwitch-based converter. ri Output current (fSW mi Mfc«i|S>»<wH i & fijjf& i tfWvfrf&f i qfaftl f ntpto i &y t CH1 1 .00 V CH2 5.00 V M 25.0 ps Figure 10.72 Output voltage and current of the TopSwitch-based converter during a load transient. Figure 10.72 shows the output voltage and current waveforms during a load transient from 10 to 5fl. For the larger load current the average output voltage decreases and the switching ripple increases. As can be seen, the output voltage reaches its steady-state value after three switching cycles. Switching Converter Design: Case Studies 513 1 0. 6.3. 1 Line Regulation The line regulation was evaluated for a constant load of 5 £1. The experimental results are summarized in Table 10.1, as expected from a current-mode flyback converter, the line regulation is excellent, below 2%. 10.6.3.2 Load Regulation The load regulation was evaluated under a constant input voltage of 110V ac . The measured load regulation is better than 1% within the testing range of load (i.e., for the output resistance changing from 4.5 to 24 O). Table 10.2 shows the measured data. 10.7 TINYSWITCH-BASED FLYBACK DESIGN A third universal power supply was built based on a TinySwitch controller [8]. The power rating of this power supply is 5 W. The circuit, shown in Figure 10.73, is based on the typical application circuit given in the control- ler's data sheet. The rectified DC voltage is obtained from the mains through fuse R x and bridge rectifier t/ 3 . The low-pass filter comprises L Y -L 2 - C, - C 2 and has the dual function of filtering the rectified voltage as well as acting as the EMI filter. The TinySwitch, TNY266P, is connected in the primary side of the flyback transformer. The clamping smibber circuit, formed by R 4 -C 1 -R 3 -D 5 , is connected in parallel with the primary winding to sup- press the oscillations of the voltage across the MOSFET transistor of the TinySwitch. The output rectifier, D&, is connected in series with the second- ary winding of the flyback transformer. A ceramic capacitor, C 8 , is added in parallel with the output capacitor, C 4 , to compensate for theinductive response of the electrolytic capacitor. A bleeding resistor, .Rg, ensures that a minimum current is drawn from the output, thus leading to the normal operation of the circuit. The output voltage can be varied by adjusting the Table 10.1 Measured line regulation of the TopSwitch-based converter y Ar 85 90 100 110 120 130 140 V^ 11. 75 11.85 11.98 11.87 11.86 11-85 11-84 Table 10.2 Measured load regulation of the TopSwitch-based converter _ Load (XI) 4.5 5 7.5 9.5 14.5 19.5 20 24 Kdc(V) 11.93 11.9 11.93 11-93 11.96 11-96 11-93 11-97 514 Power-Switching Converters Q- Tl ' iF" 1 ^ fl,< C,-LlnF1 kV tp.j tt-, 1NS82 200KM2WJ T I ^WC—^— ■ — I — ■ Flyback I "a 100 D, 1N493S Flyback | Tiansfonnef IPrlSflOuH NP:BS turns Uskaoe kvkKlne*: 31 .6 uH ico6uFiov$X7r TNY266P pcafrA , LRr |S Tftl'uS 3 C8T7A i T &1 ISO -m c 4 i"- i2SO -q Figure 1 0.73 TinySwitch-based, 5 V, 1 A, 5 W power supply. variable resistor connected to the TL431. This changes the programmable reference voltage that is subtracted from the output voltage before it is fed back to the controller. 10.7.1 Experimental Results 10.7.1.1 Waveforms Figure 10.74 shows the voltage waveform measured at the drain of the TinySwitch, which is a typical waveform of a flyback converter. The over- shoot of 75 V is clamped by the snubber circuit. The average value is 165 V. Figure 10.75 shows the measured output voltage ripple waveform. The amplitude is 1.13F pp . CH150mV M10.0psec Figure 10.74 Drain voltage waveform of the TinySwitch-based converter. Switching Converter Design: Case Studies 515 CH1 200 mV M 25.0 us Figure 10.75 Output voltage ripple of the TinySwitch-based converter. To evaluate the transient response of the converter, the load was changed from 10 to 5 fl. Figure 10.76 shows the output voltage and current waveforms of the TinySwitch-based converter during the load transient. As the current increases, the switching frequency also increases to improve regulation. The controller recovers after one switching cycle. The average output voltage after the load transient is slightly smaller than that before the transient. Output voltage- Output current Mgwiftrjfr i fiigf S fiffifi3 iM5 a CH1 1.0 mV CH2 23 mV M 25.0 us Figure 10.76 Output voltage and current of the TinySwitch-based converter during a load transient. 516 Power-Switching Converters 5.005 130 140 Input voltage (V) Figure 1 0.77 Line regulation of the TinySwitch-based converter. 10. 7. 1.2 Line Regulation The line regulation was evaluated using a constant load resistance of lOfi. As can be seen from the measurements shown in Figure 10.77, the line regulation is excellent, i.e., better than 1%. 10. 7. 1.3 Load Regulation The load regulation was evaluated using a constant input voltage of 1 10V ac . The measurement results are shown in Figure 10.78. As can be seen, the load regulation is within the 3% specification. 1 0.8 SWITCHING AUDIO AMPLIFIER A different application of switching converters is described in this section. PWM switching audio amplifiers are more efficient than their class AB counterparts since their switching transistors are operating either in the saturation region or in the cutoff region. Output transistors in class AB audio amplifiers continuously dissipate power since they are operating in the active mode. Power dissipation in switching audio amplifier is a function of the transistor saturation voltage, its switching time, and parasitic resistances of the output filter. Distortion in switching audio amplifier is a function of the switching frequency, among other parameters. The switching frequency has to be at least one order of magnitude higher than the audio signal frequency to avoid overlapping sidebands in the PWM signal. On the Switching Converter Design: Case Studies 5.00- 517 25 3.3 51 Load current (A) Figure 10.78 Load regulation of the TinySwitch-based converter. other hand, distortion in class AB audio amplifier depends on the linearity of the current-voltage characteristics of the output transistors. Figure 10.79 shows a block diagram of a basic pulse-width-modulated (PWM) switching audio amplifier. An equivalent ABM implementation in PSpice is shown in Figure 10.80. As shown, there are three mam parts to a PWM switching audio amplifier. The front-end is the pre-amphfier that vcc audio /w_ i — w*— r i^ „ t> pre-amp&fier PWM modulator H>~T*i> Power stage VCC Figure 1 0.79 Basic block diagram of a PWM switching audio amplifier. V, = -10 V 2 =10 TD = TR=1.66u- TF=1.66u '0 PW=1n PER = 3.33 u H (M(%IN1)>Vt%IN2),1S,0) triang ji audio 2 <*>' „ VOFF = ■ v * VAMPL=8 FREQ = 20fc 1 i2v,g; v 3 «: II (V(%IN)=0.15,0) 'J 12 uH out, R Loutz 4 400 uH ^tu Figure 10.80 ABM schematic of a Class-D amplifier. 575 Power-Switching Converters conditions the signal level to be compatible with the next stage. In a closed- loop configuration, the pre-amplifier may be used as the error amplifier. Any compensation for the feedback loop can be added to this stage. The output of the error amplifier is fed to a comparator that compares the error signal to a fixed-frequency sawtooth or triangular signal to achieve pulse-width modulation. The on-time of the pulse is proportional to the amplitude of the input signal. In other words, when the amplitude of the input signal is greater than the mean value of the repetitive signal, the on-time will be greater than the off-time. Conversely, if the amplitude of the input signal is less than the mean value of the repetitive signal, then the on-time will be less than the off-time. Also, if no signal is applied, the on-time will be equal to the off-time. In the case of a sinusoidal input, the duty cycle is greater than 50% when the sinusoidal is positive going, and increases with the amplitude. Likewise, when the sinusoidal signal is negative, the duty cycle is less than 50%, as shown in Figure 10.81. If there is no input signal, the duty cycle is 50% giving a net output of zero volt. The load is an inductive speaker, represented by the inductor in series with the resistor. The speaker is connected between the differential outputs of the power stage. The output stage consists of two symmetrical halves, usually called half-bridge configuration. Each half-bridge is actually a syn- chronous buck converter. The topology formed by the two half-bridges is also known as a full bridge configuration. When the reference signal applied 10V -10 V SEL» 20 V 10V ■ V(PWM1) 15V- 10V : 1 1 5V , 1 1 564jOO ■ V(PWM) 566.00 568.00 570.00 Time (us) 572.00 574.00 575.75 Figure 10.81- Input and output waveforms of the PWM modulator. Switching Converter Design: Case Studies 519 to the PWM modulator is an audio signal instead of a DC value (as it is used for a DC-DC converter), then the output voltage will track the variations of the reference audio signal achieving power amplification. The switching converter is said to work in the inverter mode. This type of switching audio amplifier is classified as a class-D amplifier. In the full-bridge topology shown in Figure 10.79, Q\ and Q 4 conduct during positive output voltages and Q 2 and Q 3 conduct during negative output voltages. For the case of a sinusoidal input, Q t and Q 4 conduct for longer portions of each switching period during the positive part of the sinusoidal input than Q 2 and Q 3 . Likewise, for the negative portion of the sinusoidal, Q 2 and Q 3 conduct for a longer part of each switching period. It should be noted that Q, and Q 2 , or Q 3 and Q 4 , must never be switched on at the same time. Otherwise, a catastrophic "shoot-through" failure of the output transistors will occur. To avoid this situation, a dead time is intro- duced between the turn-off of one transistor and the turn-on of the other transistor on the same leg. Figure 10.82 shows the PSpice model for a dead time generator. The circuit accepts a PWM input and it generates the appropriate signals to drive the two MOSFETs on the same leg by adding a 180° phase shift and a 50 ns dead time between the turn-off of one transistor and the turn-on of the other. The dead time is programmable by changing the time parameter in the delay block. The circuit of Figure 10.82 also provides driver capabilities for the MOSFETs by amplifying the TTL output voltage levels of the logic gates up to 15 V and providing floating output voltages to connect to the gate and source of the MOSFETs. The connectors, gatelJHi, and gatel_Lo, should be connected to the upper MOSFETs gate and source pins, respectively. The connectors, gate2_Hi and gate2_Lo, should be connected to the lower MOSFET's gate and source pins, respectively. The high-frequency PWM train fed to the four transistors is amplified to the voltage rails of the power supply. The low-frequency component of J0.35 pwm_m H> DELAY 50ns U, AND2 GAIN = 4 AMI-IO - n ' < I GAIN = 4 MOR9 - r. I gate1_Hi gate1_Lo NOR2 - Figure 10.82 PSpice schematic of a dead time generator. - c I gate2_Hi gate2_Lo 520 Power-Switching Converters the amplified pulse train, namely the input signal, is usually recovered at an amplified state by a low-pass filter formed by L and C . The values for L and C are chosen such that the corner frequency is slightly above the upper audio range of 20 kHz. However, the low-pass filter increases the cost of the amplifier and introduces distortion due to nonlinearities of the components. A reduced bandwidth, known as phase distortion, is another important source of distortion. The switching frequency in an open-loop PWM switching audio amp- lifier is normally chosen to be at least two decades above the corner fre- quency of the output filter to reduce output switching ripple. Since the highest audible frequency is 20 kHz, the switching frequency should be at least 2 MHz to avoid excessive output switching ripple. Fortunately, nega- tive feedback can be used to reduce the switching frequency. The corner frequency of the output filter can be reduced to 2 kHz. Negative feedback is then used to extend the closed-loop gain bandwidth to 20 kHz. Thus, a switching frequency of 200 kHz is sufficient to obtain a low output-switching ripple. The use of negative feedback also renders the switching audio amp- lifier less sensitive to noise introduced by the power supply and nonideality of the sawtooth signal. The input and output voltage waveforms obtained from the circuit of Figure 1 0.80 are shown in Figure 1 0.83 for a 20 kHz input signal. The output 800 840 960 1000 880 920 Time (us) Figure 10.83 Input and output waveforms of the open-loop Class-D amplifier with an output low-pass filter. Switching Converter Design: Case Studies voltage waveform is 180° out-of-phase with respect to the input voltage waveform and some distortions can be clearly seen. However, the output current waveform is smoother due to the filtering effect of the speaker inductance. Notice that the ripple present in the output waveforms corres- ponds to the switching frequency, which is much higher than the audio signal frequency. 10.8.1 Case Study A PWM switching audio amplifier was designed for automotive applications with a nominal 12-V supply. The maximum output power was specified at 18 W for a 411 and 400 n-H speaker. The maximum output power can be readily increased by increasing the magnitude of the supply voltage. Also, the output ripple was minimized so that its total harmonic distortion (THD) was less than 0.05%. The number of components was kept to a minimum without sacrificing performance. A low-pass output filter was not used in this design; instead, the distortion in the output waveform was minimized by using negative feedback. Three nested feedback loops accomplish this task. Ultimately, the entire amplifier can be integrated into a single-chip inte- grated circuit. Figure 10.84 shows the block diagram of the multi-loop PWM switching audio amplifier. Starting with the inner loop, each loop was designed with the aid of PSpice simulations. A linear model was used to calculate the phase compensation of each loop. The phase shift due to the time delay at the crossover frequency of the loop gain was calculated and added to the unity-gain phase to obtain the phase margin. This procedure gives a good approximation if a close estimation of the time delay can be made. Once the frequency compensation is calculated, the results can be checked using time-domain simulations. '^ei^n-^^sj]-^ *(s) W S J *^ filter fc(s) low-pass filter Ms) low-pass filter * Figure 10.84 Block diagram .representation of the multiloop amplifier. (From Figure 3 of Oliva, A.R., Ang, S.S., Vo, T.V., A multi-loop voltage feedback fiterless Class-D switching audio amplifier using unipolar pulse-width-modulahon, IEEE Trans, on Consumer Electronics, Vol. 50, No. 1, February 2004, pp. 312-319. With permission.) 522 Power-Switching Converters 10.8. 1.1 The Output Stage An H-bridge configuration was chosen for the output stage because the switching amplifier must exhibit two-quadrant operation and have bi- directional current flow with respect to the load. The H-bridge configur- ation also allows the use of a single supply voltage for the output stage. HIP2060AS2 power MOSFETs in surface-mount packaging were chosen for their high switching speeds and simpler drive requirements compared to their bipolar counterparts. Using less expensive n-channel devices also eliminates the need for matched devices thereby minimizing cost. To turn on the high-side power MOSFET, a gate voltage higher than the drain voltage is needed. Since the drain voltage of the high-side power MOSFET is equal to the supply voltage, an International Rectifiers' IR2110 high- voltage MOS gate driver with independent high-side and low-side driving capabilities was used. The gate drive requirement for the high-side power MOSFET is achieved via a bootstrap technique using an external capacitor and a char- ging diode. The value of the bootstrap capacitor is dictated by the gate charge requirements, switching frequency, and duty cycle. Once the turn- on charge has been delivered to the gate of the power MOSFET, a minimum gate voltage must be maintained during the entire conduction period. The current drawn from the bootstrap capacitor, /q B s> is equal to the quiescent current of the high-side channel of the IR21 10. The minimum bootstrap capacitance, C B , is given as [9] C„> Z^QBSfon (1095) B (Kee-1.5-10)' where a voltage drop of 1 .5 V on the charging path of the bootstrap capaci- tor and a voltage drop due to the internal leakage, equal to half the excess gate voltage is assumed. Assuming a quiescent current of 100 uA, a switch- ing frequency of 300 kHz with a maximum duty cycle of 90%, and a supply voltage of 12 V, gives a minimum value of 0.6 nF for the bootstrap capacitor. A very conservative value of 0. 1 jiF was chosen for the bootstrap capacitor. A 1N4153 fast-switching diode, with a voltage rating of 75 V and a reverse recovery time of 2 ns, was chosen for the charging diode. To help reduce noise, and supply the transient current needed for switching the capacitive loads, bypass capacitors between V cc and common, and F DD and Kss phis in the IR2110 were used. All bypass capacitors, including the reservoir capacitors, should be connected as close to the IR2110 as possible. A 0.1 \l¥ ceramic disk capacitor in parallel with a 1 pF tantalum capacitor is recommended for V cc bypass [9]. Switching Converter Design: Case Studies -523 The reconstruction of the original signal was accomplished without a low-pass filter. The combined action of the three feedback loops and the inductive speaker was sufficient to achieve a high-fidelity (hi-fi) THD level. However, this topology is restricted for those applications where the ampli- fier can be kept close to the voice coil in a shielded environment, like in shielded powered speakers, to maintain EMI within admissible levels. As with any switching converter, a certain amount of output switching ripple will be associated with the switching frequency: The higher the switch- ing frequency, the lower is the output ripple. As a general rule, the switching frequency must be at least two decades above the upper frequency of the audio band. For audio applications, the upper frequency must be at least 200 kHz to provide a flat frequency response out to 20 kHz. Thus, the switching frequency was chosen at 300 kHz as a trade-off between the distortions that would be introduced by the dead time and the attenuations of the aliased frequency components. Another drawback of a very high switching frequency is that the linearity of the sawtooth waveform becomes hard to maintain, which adds additional distortion to the output. Such problems can be mitigated by using negative feedback. 10.8.1.2 The Error Amplifier The error amplifier of each feedback loop is a TLE2082 operational amplifier configured into a differential amplifier, as shown in Figure 10.85. A high slew rate amplifier is required because the error signal has very fast transients due to the absence of an output low-pass filter. Since a triangular carrier waveform of -5 to 5 V peak-to-peak is used, no offset voltage is needed to yield a duty cycle of 50% when there is no input signal. The stages following the error amplifier are used for phase compensation and to pro- vide additional loop gain. A 330 jjF input decouplingxapacitor is connected in series with R t to eliminate any DC voltage that the signal source might otherwise introduce. 10.8.1.3 PWM Modulator For the generation of the PWM waveforms, the unipolar-PWM modu- lator shown in Figure 10.86 was used. The input and output waveforms are shown in Figure 10.87. For the unipolar-PWM modulator, the triangular carrier is compared with the audio signal as well as the same signal shifted 180° to yield the unipolar-PWM signals. The main advantage of unipolar- PWM is that no spectral bins appear at the odd multiples of the switching frequency, and no multiples of the switching frequency are present. The first spectral bin that appears outside of the base-band corresponds to 2/ s — f , as shown in Figure 10.88. This essentially doubles the switching frequency, 524 Power-Switching Converters AA/V — ||i- Q. *- -r 3 .— co -* KT 13 < § w. *" ** > C h-s >"§ r&J t/3 "-» <yj ,r 60.9 c -^i <■§ r T3 oi 2 2 e j= « -o > -:r = s O o CO O 3 _ D< vo ~— i« 31 0> — - k. O 3 O. C o 55 V] .»-s - U. 3 C CO 5 c 1 o — u t- CO o. J3 t- - o o JS £ =3 c co C OS c a m (L> 1 D. O eN E ^ r*v O 3 o cd Q. co zSr 33 .5 -S J= o D. U o CM "§"* >» s M I- =8 «- ■? 3 lw CO Ch •— rt ea EX o bu C co _J- A CO fc- -r- 6 s S 2 t- — ID c o cr> J* . *r> 8 "o CO s> > o-S t-s T- ,d> ^CJ <+-. 3 cu o> — co — o U. > 53 Switching Converter Design: Case Studies 525 triangle_tn| pwm_oul_2 pwm_out_1 Figure 1 0.86 Schematic diagram of the unipolar-PWM modulator. SEL» -eav. 20V 10V ov 20 V 10V ov V(U2.audio_in)» V(L/2.triangte_in) 1 V (U2.pwm_out_1 ) uumiL D . n n n n ju '.„„ h neon 4 n'ceo 1 nR(Kl 1.0640 1.0680 1.0492 1-0520 1.0560 1.0600 1.0640 •= V (U2.pwm_out_2) -n me ( ms ec) Figure 1 0.87 Input and output waveforms of the unipolar-PWM modulator. 526 Power-Switching Converters Magnitude 2F S Frequency 2F s -f 2F+f Figure 10.88 Frequency spectrum of unipolar PWM. moving the unwanted frequency components far away from the audio band. A triangular carrier is preferred over a sawtooth carrier due to its lower harmonic contents. 10.8. 1.4 The Feedback Loop Because the speaker load in the H-bridge is floating so that neither side is referenced to ground, a differential amplifier must be used to sample the voltage across the load. Since there is no output filter, the voltage waveform at the load is a square wave. A low-pass filter was added at the input of the voltage-sensing amplifier to avoid slew rate distortion at this stage (Figure 10.89). This means that almost all unwanted upper frequency oscillations and distortion are attenuated by the filter. Thezgain of the differential amplifier is determined by resistors Ru, J?i4, i?is, : and R t 6 according to with I^out = (In+ - t \-^'3 R\3 = ^14, ^15 = R\6- (10.96) (10.97) The voltage gain was selected as 1 V/V to avoid slew rate distortion. 10.8.1.5 Evaluation The PWM switching audio amplifier was constructed on a double- sided printed-circuit board. All measurements wereperformed with a + 12 V Switching Converter Design: Case Studies 527 i* 2.2n -VA- T c 2 2.2n -<vVv- 100* -VW- 100* U204A n +12 ?100* ^S^ TLE2082/3( 1/T1 n, 3 A/V- lOul 100* -12 Figure 10.89 Voltage sensing amplifier. supply for the signal stage and a + 12 V supply for the output stage. THD+N characteristics were characterized using an Audio Precision System One Audio analyzer. Audio standards establish that the measurements of the hi- fi parameters of the audio amplifiers have to be performed within the audio band. As such, an active LPF with the required characteristics' was con- nected iii parallel with the load and measurements were taken at this output. All voltage and current measurements were performed using a Tektronix TDS540 oscilloscope and an AM503A current probe. A quiescent current of less than 10mA was measured at a 50% duty cycle or with no input signal for the output stage. 10.8. 1.5. 1 Open-loop response. The THD+N versus frequency re- sponse of the open-loop amplifier is shown in Figure 10.90. The distortion is below 0.7% up to 1 kHz and increases after this frequency. 10.8.1.5.2 Closed-loop response. The simulated and measured closed-loop frequency responses are shown in Figure 10.91 and Figure 10.92, respectively. The measurements were taken using a fourth-order low-pass filter having a corner frequency at 30 kHz. The simulation results show a flat magnitude response up to 100 kHz and a flat phase response up to 20 kHz, which is in good agreement with the calculations. However, the measured frequency response is flat up to 20 kHz and then decreases very rapidly due to the influence of the low-pass filter used for the measurements. 10.8.1.5.3 Total harmonic distortion plus noise analysis. Figure 1 0.93 to Figure 1 0.95 show the THD+N analysis for the closed-loop amplifier 1 Pass-band response deviation: £ + 0.1 dB for 10 Hz >60dBfor/">24kHz. s/£ 20kHz; stop-band attenuation: 528 Power-Switching Converters AUDIO PRECISION AMP-THD+N(%) vs FREQ(Hz) 3 0.1 0.010 0.001 20 100 1k 12 OCT 101 14:17:14 I I I ... Ap T ' ..J. - + ■ 10k 20k figure 1 0.90 THD+N versus frequency for the open-loop amplifier. (From Figure 1 1 of Oliva, AJL, Ang, S.S., Vo.T.V., A multi-loop voltage feedback filterless Class-D switching audio amplifier using unipolar pulse-width-modulation, IEEE Trans, on Consumer Electronics, Vol. 50, No. 1, February 2004, pp. 312-319. With permission.) Orf -60d -120d SEl^> -200d -20 phase (20.184K, 906.914m) n p ((V(out1) - V(out2))/V(in)) -40 magnitude (20.1 7K,423.304n ) 10 Hz 100 Hz 1.0 kHz ° db((V(out1)-V(out2)yV(in)) 10 kHz 100 kHz -■ 1.0 MHz 10 MHz Frequency Figure 10.91 Simulated closed-loop frequency response. Switching Converter Design: Case Studies 529 AUDIO PRECISION THD-FRQ AMPL(dBr) & PHASE(deg) vs FREQ(Hz) 04 JAN 88 06:22:08^ b.OOOO 4.0000 3.0000 2.0000 1.0000 0.0 -1.0000 -2.0000 -3.0000 -4.0000 1 I flf> -180 I PH iSI - -190 - -200 -■ -210 -■ -220 1 AR IPL l 1 T" \ * -■ -230 -- -240 J B- ■ - -250 -- -260 -I 270 ]J ..... 1 1 I-5.OOO0 20 100 1* 10 * 50k Fiqure 10.92 Measured closed-loop frequency response. (From Figure 9 of Oliva, A R Ang S S , Vo, T.V., A multi-loop voltage feedback filterless Class-D switching audio amplifier using unipolar pulse-width-modulation, IEEE Trans, on Consumer Electronics, Vol. 50, No. 1, February 2004, pp. 312-319. With permission.) 0.5 AMP-THD THD+(%) vs FREO(Hz) 07 OCT 101 14:43:49 0.010 0.001 10fc 20k Figure 1 0.93 THD+N versus frequency for one loop feedback. (From Figure 12 of Oliva A R , Ang, S.S., Vo, T.V., A multi-loop voltage feedback filterless Class-D switching audio amplifier using unipolar pulse-width-modulation, IEEE Trans, on C oralU m e r£tor O m«,Vol.50,No.l,Februar y 2004,p P .312-319.Withperm 1SS1 on.) 530 Power-Switching Converters AMP-THD THD+N(%) vs FREO(Hz) 07 OCT 101 14:0725 0.1 / Ap — /" *- J- ' ■__•' 0.010 ' n nm 20 100 1fr 10k 20k Figure 10.94 THD+N versus frequency for two feedback loops. (From Figure 1 3 of Oliva, A.R., Ang, S.S., Vo, T.V., A multi-loop voltage feedback filterless Class- D switching audio amplifier using unipolar pulse-width-modulation, IEEE Trans, on Consumer Electronics, Vol. 50, No. 1 , February 2004, pp. 312-319. With permission.) when one, two, and three feedback loops are closed, respectively. The meas- urements were taken using a 1 kHz 10 V pp sinusoidal input. Notice that the curves are fairly flat up to 1 kHz but they start to increase after this frequency. Also, notice that every time a loop is added, the distortion reduces. As can be seen, there is not much of an improvement in THD+N in going from the two- loop configuration to the three-loop configuration. We attribute this to the background noise and the influence of the low-pass filter used to make these measurements, which has a THD of 0.008% in the audio band. 10.8.1.5.4 Input and output wavefonns. Figure 10.96 shows the input audio signal and output current waveform across the speaker load for a frequency of 1 kHz. As can be seen, there is a phase shift of 43° between the input voltage and output current signals due to the inductive nature of the speaker. The output-switching ripple is barely visible on the output current waveform. It should be noted that an increase in the audio input signal increases the amplitudes of both the output voltage and output current, with a concomitant increase in output power. Switching Converter Design: Case Studies AMP-THD THD+(%) VS FREO(Hz) 07 OCT 1 01 1 4:32:45 531 0.5 0.1 0.010 0.001 I ' I Ap .... \\ .. I I 20 100 U 10k 20fc Figure 10.95 THD+N versus frequency for three feedback loops. (From Figure 14 of Oliva, A.R., Ang, S.S., Vo, T.V.,A multi-loop voltage feedback filterless Class- D switching audio amplifier using unipolar pulse-width-modulation, IEEE Trans, on Consumer Electronics, Vol. 50, No. 1 , February 2004, pp. 312-319. With permission.) J2 RUN Figure 10.96 Input voltage and output current waveforms. 5$2 Power-Switching Converters REFERENCES 1. K. G. Pohlmann. Infinity DPA-275 150-W Class D Amplifier, Car Stereo Review, Vol. 6, 1993, 65pp. 2. L594 data sheets, SLVS052F, Texas Instruments Inc., Dallas, Texas 75265, April 1988, revised November 2003. 3. R. J. Vaccaro. Digital Control: A State-Space Approach, McGraw-Hill, 1995. 4. Unitrode, UC3842/3/4/5 Provides Low-Cost Current-Mode Control, Application note U-100A, Texas Instruments Inc., 1999. 5. C. P. Basso. Switch-Mode Power Supply SPICE Cookbook, ISBN: 0071375090, McGraw-Hill Professional, 2001. 6. B. Yaakov. Average simulation of PWM converters by direct imple- mentation of behavioral relationships, IEEE Applied Power Electronics Conference, 1993, pp. 510-516. 7. TOP232-234, TOPSwitch-FX Family Design Flexible, EcoSmart®, In- tegrated Off-line Switcher, Power Integrations Inc., 2001. 8. TNY264/266-268 TinySwitch-II Family data sheets, Power Integrations Inc., April, 2003. 9. International Rectifier Application Notes AN-978A, International Rec- tifier, El Segundo, CA, 1990. index A Amplifier class AB, 440, 516,517 class D, 517-531 closed-loop response, 400* 527 distortion, 516, 517, 520, 521, 523, 526, 527, 530 error, 3, 162,227, 231 inverting error, 231 magnetic, 131 open-loop response, 400, 527 output stage, 518, 522, 527 switching audio, 516-531 block diagram, 517 multi-loop, 521 PWM modulator, 523 Waveforms, 520 THD, 521,523,527-531 Average output voltage basic inverting SCC, 345 basic step-up SCC, 342 basic step-down SCC, 344 boost converter, 36, 41 buck-boost converter, 47, 48, 51 buck converter, 18, 21 , 28, 29, 1 64, 453 with losses, 63 Cflk converter, 57 flyback converter, 150, 491 forward converter, 135 fundamental switching converter, 8 half-bridge parallel-loaded resonant converter, 120 interleaved boost with current-mode control, 332 n-Stage Step-Down SCC, 355 n-Stage Step-Up SCC, 355 533 534 Index step-down SCC, 351 step-up SCC, 353 Step-Up Step-Down SCC, 359 parallel-loaded resonant converter, 120 push-pull converter, 140 ZCS QR buck, 84 ZVS QR boost, 105 ZVS QR buck, 99 Averaged models, 207, 209, 248 B Base driver, 3, 4, 6, 130, 137, 181 Behavioral modeling, 388 Bode plot, 200, 217, 219, 220, 226, 281, 407, 412, 414, 419, 430 Boost converter, 32 average inductor current, 39 average input current, 36 average output voltage, 36, 41 closed-loop, 167, 169, 170, 401, 403, 417, 420 continuous-mode, 33 critical inductance, 39 current-mode, 170, 223, 331 discontinuous-mode, 38 inductor ripple current, 36 interleaved, 331 open-loop, 217, 387, 407 output ripple voltage, 37 PSpice simulations, 387, 399, 402, 407 state-space averaged model, 268, 274 transfer functions, 280 voltage conversion ratio, 36, 41 voltage-mode, 223 waveforms, 43 Boost-derived converter, 17, 145 Buck converter, 18 average inductor current, 22 average input current, 24 average output voltage, 21, 27 closed-loop, 452 continuous-mode, 19 critical inductance, 25 current-mode, 173 current-mode quasi resonant, 77 design, 441 discontinuous-mode, 24 inductor ripple current, 20, 21 input EMI filter, 23, 294, 301 magnitude response, 238, 240, 284, 286,443 open-loop, 375, 381 output ripple voltage, 22 PSpice simulations, 375, 381, 444, 452 state-space averaged model, 248, 255, 263, 278 transfer functions, 282 voltage conversion ratio, 21, 27, 28 waveforms, 23, 30 Buck-boost converter, 42 average inductor current, 49 average input current, 49 average output voltage, 47, 50 continuous-mode, 45 critical inductance, 50 discontinuous-mode, 49 EMI filter, 292 inductor ripple current, 46, 47 output ripple voltage, 48 voltage conversion ratio, 47, 50 waveforms, 44 Buck-derived converter, 17, 18, 130, 136, 140, 143 Capacitive tum-on losses, 69, 75 Capacitor bootstrap, 190, 522 bypass, 522 DC blocking, 141 energy-transfer, 55, 56, 58-60, 352-356, 359, 365, 366 ESR, 63, 212, 214, 216, 221, 230, 232, 236, 240, 263, 413, 442, 443, 508 filter, 23, 108, 141, 143, 215, 243, 245, 299, 495 Index 535 model, 63 output, 22, 31, 38, 48, 59, 135, 212, 268, 381, 382, 442 resonant, 71, 72, 75, 80, 86, 366 timing, 177, 181 Characteristic impedance EMI filter, 297 output filter, 212 parallel-loaded resonant converter, 119 series-loaded resonant converter, 109 ZCS QR boost converter, 90 ZCS QR buck converter, 80 ZCS QR half-bridge converter, 154 ZVS QR boost converter, 103 ZVS QR buck converter, 96 Comparator, 163-165, 169, 177, 202, 397 Compensation network, 227 lag, 229, 285 lead-lag, see P1D PI, 229, 418, 499 PID, 232, 413, 446, 448 Constant volt-second requirement, 1 3 boost converter, 36, 39 buck converter, 21, 27 buck-boost converter, 46 Cflk converter, 56 flyback converter, 150 forward converter, 135 full-bride converter, 144 half-bridge converter, 142 push-pull converter, 140 ZCS QR boost converter, 92 ZCS QR buck converter, 84 ZCS QR half-bridge converter, 155 ZVS QR boost converter, 105 ZVS QR buck converter, 99 Control law, 277 Convergence problem, 381, 422-427 Corner frequency, 78, 215, 247, 284 Critical inductance, 24 boost converter, 39 buck-boost converter, 50 buck converter, 25 Critical load resistance, 25 boost converter, 39 buck converter, 25 Cflk converter, 52 average input current, 57 average output voltage, 57 inductor ripple current, 56, 57 input EMI filter, 59 output ripple voltage, 59 voltage conversion ratio, 57 Current-mode control, 169, 473, 489 Current-mode instability, 171, 476 Current-time product, 14, 58 average, 386 boost converter, 37 buck-boost converter, 48 buck converter, 22 Cflk converter, 58 D Damping factor, 219 Damping ratio, 212, 285 DC transformer, 255 Diode antiparallel, 74, 108, clamp, 77, 94, 184,510 freewheeling, 20 Digital control, 460 Digital signal processor, 440 Discrete-time model, 306 Distortion, 337, 516, 520, 521, 527 Duty cycle, 8 boost converter, 37, 42 buck-boost converter, 50, 51 buck converter, 21, 28 Cflk converter, 60 with losses, 63 Efficiency, 1, 5 buck converter, 24, 31 class AB amplifier, 440 class D amplifier, 440 resonant converter, 69 series-pass regulator, 6 shunt regulator, 7 536 Index Electromagnetic interference (EMI), 10, 162 buck converter, 302 common mode, 293 Cfik converter, 59 design, 502, 510 differential mode, 293 filter, 7, 292, 301 switching capacitor converters, 359, 365 Equivalent circuit boost converter averaged-switch model, 208, 217 linearized, 274 linearized using DC transformer, 276 load reflected, 276 nonlinear continuous, 272 source reflected, 275 buck converter averaged-switch model, 208 discrete-time model, 307 linearized, 254 linearized discontinuous-mode, 263 linearized using DC transformer, 255 linearized using DC transformer with ESR, 255, 269 linearized with ESR, 269 nonlinear continuous, 251 nonlinear continuous discontinuous mode, 258 nonlinear continuous with ESR, 267 source reflected, 255 Error amplifier, see Amplifier error Error voltage, 162-164, 177, 209, 400 Equivalent series resistance (ESR), 63, 212, 214, 230, 232, 236, 240, 405, 408, 442, 508 LC, 18, 70, 508 low-pass, 10, 17, 22, 202, 21 1, 245, 462, 520 output, see low-pass corner frequency, 78, 215, 245, 247, 284, 325 frequency response, 21 1 second-order low-pass, 211 Flux imbalance, 140, 141, 144 Flyback converter, 145 continuous mode, 149 . discontinuous mode, 150, 489 Flyback transformer, 150, 159, 490, 509 Forward converter, 1 30 Fourier analysis, 380-382 Fourier series, 9 Frequency modulator, 161, 397 Frequency response, 211, 230, 244, 398, 401,408,430,462,529 Full-bridge converter, 143 Gain-factor compensation, 283 Gain margin, 226-229 H Half-bridge converter, 140 Hard switching, 69, 365 Harmonics, 9, 381, 382 'H-bridge converter, see Full-bridge converter High-frequency pole, 230, 236, 239 High-side, 144, 522 Hybrid modeling, 254 Hysteresis control, 172, 331, 335 loop, 134, 140 band, 175, 332 Feedback compensation, 169, 177, 211, 236, 240 Filter EMI, 7, 292, 301 input EMI, 7, 292, 301 Ideal switch, 383, 384 Inductive kick, 20, 496 Inductor coupled, 67, 145, 489 input, 41, 49, 335 Index 537 model, 61 output, 18, 22, 31, 117, 257 resonant, 74, 78, 365 Input impedance, 294-297, 409, 502, 505 Input voltage susceptibility, 276, 281 Inrush current, 41, 51 Interleaved converters, 321 Inverse turns ratio, 131, 150 Inverting converter, 42, 345, 347 KirchhofPs current law KirchhofTs voltage law N Natural frequency, 212, 219, 237 Nyquist, 229 O Off-line switching converter, 1360, 140, 143, 185, 190 Open loop gain factor, 283 Output current susceptibility, 281 Output impedance, 243 Output ripple voltage, see Output switching ripple Output switching ripple, 60, 247, 520, 530 Overdamped, 212, 243, 284, Lag compensation, 285 Laplace transform, 12, 246, 277, 391 Lead-lag compensator, see PID compensation network Leakage inductance, 132, 134, 143, 151, 514 Ledge current, 139, 142 Line regulation, 161, 452-459, 513, 516 Load-line trajectory, 75 Load modulation, 276, 377 Load regulation, 161, 452-460, 513, 516 Loop compensation, 276, 283, 285 Loop gain, 200, 223, 226, 228, 239, 283, 411,446,455,499 Low-frequency zero, 230, 239 Luo converter, 359 M Macromodel, 422 Magnetic core, 61, 131, 134, 140 Magnetizing inductance, 146, 151 Magnitude response buck converter, 236, 240, 443 compensation network, 230, 232, 235 error amplifier, 229, 239 output filter, 212 Matlab matrices, 431 Simulink, 433 transfer functions, 428 Parallel-loaded resonant converter, 116 above-resonant mode, 121 below-resonant mode, 123 continuous mode, 121 discontinuous-mode, 117 voltage conversion ratio, 125 Peak-to-peak capacitor ripple current boost converter, 38 buck-boost converter, 48 buck converter, 22 Cuk converter, 59 Peak-to-peak ripple voltage, see Output switching ripple Phase boost, 230, 233, 415, 448 Phase lag, 214, 230-241, 284 Phase lead, 231 Phase margin, 226-228, 238, 242, 243 Phase response buck converter, 284 compensation network, 230 output filter, 212 Phase shift, 212, 226, 238, 322, 521 Power-packing density, 1, 7, 69, 439 PSpice functions, 395 operators, 394 parts, 390-394 538 Index PSpice simulations ABM blocks, 390 Behavioral modeling, 388 boost converter, 387, 399 buck converter, 375 convergence problems, 422 Creating capture symbols, 422 input impedance, 409 output impedance, 409 small-signal analysis, 403 Small-Signal Transient Analysis, 409 vendor models, 402 Vorperian models, 404 Power factor correction, 334 PWM current-mode, 169, 203, 473 voltage-mode, 162, 202, 460 PWM controller, 162-195 Pulse-width modulator, 165 L6598, 190 SG3524, 177 TinySwitch, 185 TL497, 180 UC3842, 181 Push-pull converter, 136 Quasi-resonant switches, 73 current mode, 75 full wave, 75, 76 half wave, 75, 76 L-type, 75, 76 M-type, 75, 76 voltage mode, 76 R Regulator linear, 3 series-pass, 3 shunt, 5 voltage, 1-7, 21, 186, 221, 242, 288, 308, 312, 494 Relative stability, 226 Resonant capacitor voltage, 78-125, 154 parallel-loaded resonant converter, 119 series-loaded resonant converter continuous mode, 112 discontinuous mode, 109 ZCS QR boost converter, 90, 91 ZCS QR buck converter, 80, 82 ZCS QR half-bridge converter, 154 ZVS QR boost converter, 103 ZVS QR buck converter, 96, 97 Resonant circuit parallel, 71 series, 72 Resonant converters, 69, 365 Resonant frequency EMI filter, 295 parallel resonant circuit, 71 parallel-loaded resonant converter, 125 self, 61 series resonant circuit, 73 series-loaded resonant converter, 109 ZCS QR boost converter, 90 ZCS QR buck converter, 80 ZCS QR half-bridge converter, 154 ZVS QR boost converter, 103 ZVS QR buck converter, 96 Resonant inductor current parallel-loaded resonant converter, 119 series-loaded resonant converter, 109 continuous mode, 1 1 1 discontinuous mode, 109 ZCS QR boost converter, 89 ZCS QR buck converter, 80 ZCS QR half-bridge converter, 154 ZVS QR boost converter, 103 ZVS QR buck converter, 96 Resonant tank, 74, 80, 1 10, 124 Right-half-plane zero, 283, 489, 499 Ringing-choke converter, see Boost converter Root-mean-square, 9 Routh-Hurwitz stability criterion, 297, 299, 300 Index 539 Sampling network, 180, 236, 443 Sawtooth signal, 163, 166, 400, 443 Series-loaded resonant converter, 107 above-resonance mode, 110 below-resonance mode, 113 continuous mode, 110, 113 discontinuous mode, 108 Shoot-through, 519 Small-signal models, 222-225 Snubber, 496 Source coefficient matrix, 246, 250, 266, 271 Source vector, 246 Stability considerations, 293, 296 State coefficient matrix, 246, 249 State equation, 248, 249, 304, 311 State-space averaged model, 248 boost converter, 268 buck converter discontinuous mode, 255 with ESR, 263 ideal, 248 State variable, 245 State vector, 246 State-space averaging, 247 Steady-state, 13, 18 Step-down converter, 18, 344, 348, 353 Step-up converter, 268, 342, 352, 355 Step-up step-down converter, 356 Switched-capacitor converters, 341 Switching frequency, 8, 12, 13, 18,22, 31, 69, 77, 163, 175, 209, 229, 247, 294, 307, 321 Switching losses, 24, 31, 69, 70, 195 Switching noise, 230, 239 Switching ripple, 23, 60, 229, 247, 407, 520 Synchronous Rectifier, 31, 460, 473 THD,521,527 Thermal runaway, 140 Time constant, 12, 29, 166 Topology, 17 Total harmonic distortion, 521, 527 Totem-pole, 141, 166, 188 Transfer function open loop boost converter, 219, 283 buck converter, 282 output filter, 21 1 source-to-state boost converter, 279 buck converter, 278 Transient analysis, 374, 376, 409, 423, 426, 501 Transient response, 292, 433, 462, 465, 470,474,484,501, 502 Turns ratio, 151 U Underdamped response, 212, 284 Unity-gain crossover frequency, 229, 237, 446 Variable-frequency controller, see VCO VCO, 187, 189, 397 Versine function, 80, 119 Voltage-controller oscillator, see VCO Voltage conversion ratio boost converter, 36, 41 buck-boost converter, 47, 50 buck converter, 21, 27, 28 forward converter, 135 full-bride converter, 144 half-bridge converter, 143 push-pull converter, 1 40 ZCS QR boost converter, 92 ZCS QR buck converter, 84 ZCS QR half-bridge converter, 157 ZVS QR boost converter, 105 ZVS QR buck converter, 99 Voltage regulator, 3, 31 1, 314 Volt-second requirement, 1 3 W Weighting factor, 248 540 Index Z, Zero frequency, 236 Zero-current-switching (ZCS) quasi- Zero-voltage-switching (ZVS) quasi- resonant (QR) boost converter, resonant (QR) boost converter, 87 101 Zero-current-switching (ZCS) quasi- Zero-voltage-switching (ZVS) quasi- resonant (QR) buck converter, 77 resonant (QR) buck converter, 94